Achronix Technology and Product Overview Presented: November 15, 2005 – NASA Goddard Space Flight...

Achronix Technology and Product Overview

Presented: November 15, 2005 – NASA Goddard Space Flight Center

The World’s Fastest CMOS FPGA for Commercial and Extreme Environments

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Legal Disclaimers

Safe Harbor NoticeThis document is not a prospectus and is for informational purposes only. The document contains "forward looking statements" which are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward looking statements are generally preceded by words such as "will," "expects," or "anticipates." Investors are cautioned that all forward-looking statements in this release involve risks and uncertainty, including without limitation the risk that the Company's products may not be available according to the current schedule.

Securities Act of 1933 and Blue Sky NoticeNothing contained herein shall be deemed to create an “offer” to sell interests or securities, public or private, as such terms is used and construed in and under the Securities Act of 1933 or the Securities Exchange Act of 1934, or any related law or any “Blue Sky” law of any State.

Export Control NoticeThe information contained in this document is not considered Export Controlled by the United States, as defined in the International Trafficking in Arms Regulations (ITAR), and is therefore exempt from restrictions of disclosure to non-US Persons.

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Agenda Company OverviewOverview of Asynchronous CircuitsAchronix Technology & Solution OverviewProduct Architecture and Specifications

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Achronix Semiconductor Overview

HistoryFounded 2004 in Ithaca, NY

Founders include original developers of technology at Cornell Univ. - Dr. Rajit Manohar, Dr. Clinton Kelly, IV, Dr. Virantha Ekanayake - and John Lofton Holt

All founders except Dr. Ekanayake are full time employees of Achronix presently

Financed with owners capital to date. Company is currently working with several private equity groups to fund production in 2006.

Product SpaceWe make the world’s fastest Field Programmable Gate Arrays (FPGAs) in two product lines:

– Achronix-ULTRA: GHz Speed Ultra high performance FPGA

– Achronix-XTREME: GHz Speed Extreme environment (temperature and radiation) FPGA

Competitors:– FPGA Vendors: Xilinx,

Altera, Actel, Lattice, etc.– ASIC Vendors: LSI Logic,

Fujitsu, IBM, Hitachi

Status and GoalsCompleted first successful prototype of product in early 2005, a 674 MHz FPGA fabricated in TSMC 180nm CMOS

Completed second prototype in October 2005 (due back in January 2006), a 1+GHz FPGA fabricated in ST Microelectronics 90nm CMOS

Goal:– Ship first product in 2006– Achieve profitability in

2007

Achronix’ technology is based on asynchronous logic

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Our goal is to build GHz-speed FPGAs for commercial and extreme environments

Achronix Key GoalsUltra fast Speed

– Support system throughputs in the 1+GHz (2006) to 2.5 GHz (2008) range through our asynchronous FPGA fabric

Competitive Density and Power Performance– While operating at GHz speeds, provide competitive density and power performance to state of

the art devices from Xilinx, Altera, Actel, and Lattice

Synchronicity and Interoperability– At the system level, look and feel just like a traditional synchronous FPGA from Xilinx, Altera,

Actel, Lattice, and others by surrounding our fabric with traditional synchronous I/Os

Support the Existing EDA Landscape– Support existing EDA tools used by FPGA and ASIC designers to ensure that our products can be

integrated easily and immediately and replace slower parts from or competitors

*Source: Simulations of Achronix 90nm design. Real results to be determined in January 2006

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Asynchronous circuits are not new in the research community or in the commercial world

Introduction of first commercial

RS232 asynchronous serial interface

(Bell)

1946 … 1969 … … … 1989 1998 2003 2004 2005

First theory of an asynchronous

computational machine (Princeton)

Fabrication of first asynchronous

microprocessor (Caltech)

Fabrication of fastest asynchronous

microprocessor (Caltech)

Introduction of first asynchronous

commercial product (Fulcrum

Microsystems)

Introduction of fastest reconfigurable logic

module in CMOS (Cornell

University/Achronix)

Introduction of first microprocessor for sensor networks

(Cornell University/Achronix)

Design of first GHz asynchronous FPGA

(Achronix)

*Source: A.W. Burks, H.H. Goldstein, and John von Neumann. Preliminary discussion of, the logical design of an electronic computing instrument. Institute for Advanced, Study, Princeton, N.J., June 1946., Wikipedia “RS232”, Manohar “The Impact of Ascynchrony on Computer Architecture”, 1998, Naffziger, et al, “The Implementation of a 2-CoreMulti-Threaded Itanium Family Architecture”, ISSCC 2005

Introduction of asynchronous interface logic in next generation

Itanium processor(Intel)

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Asynchronous circuits operate in a fundamentally different way that their traditional synchronous counterparts

Traditional Synchronous Circuit Behavior:

Discrete Time, Discrete VoltageAsynchronous Circuit Behavior:

Continuous Time, Continuous Voltage

Sender Receiver

Clock

Sender ReceiverDATADATA 1

DATA 0

ACK

DATA “1”

DATA “0”

DATA “1”

DATA “0”

ACK

CLK

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This asynchronous method of operation allows computations to be “pipelined”, which reduces the complexity of operations, and facilitates more efficient parallel computation

Synchronous Computation

Asynchronous Computation

c:= h(g(f(x)))a:= f(x)b:= g(a)c:= h(b)

The result: Faster execution, no registers required to store values, no power wasted waiting for previous instructions to complete

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The asynchronous approach has numerous advantages over traditional synchronous circuits, and significant advantages in extreme environments, but there are challenges

Asynchronous AdvantagesSpeed: Circuit speed is no longer limited by a clock

Power: Because circuits only operate when they need to, standby power is dramatically reduced and operating power is highly optimized

Redundancy: Data is encoded, therefore redundancy can be exploited to locate permanent faults and tolerate transient faults

Scaling: Circuits scale more efficiently as there are not clock distribution issues and NO GLOBAL SIGNALS (As the circuits scale, density increases versus synchronous counterparts)

Delay Insensitive: Circuits do not depend on, or make assumptions about delays.

Asynchronous ChallengesDensity: Increased number of wires for logic functionality results in small area penalty in individual circuits (mitigated by lack of clock distribution logic required)

Synchronous Interfaces: The world of electronics is synchronous, so asynchronous systems must have synchronous “edges” to interoperate with other synchronous devices in a system

The Achronix solution leverages the benefits while addressing the challenges to present a product that can be used by customers today, using

their existing designs and infrastructure

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Achronix has already built a 180nm prototype that operates at 674MHz system throughput, over twice as fast as similar devices from FPGA industry leaders

Measured Performance - 180nm Prototype FPGA

0

200

400

600

800

1000

1200

0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3

Operating Voltage (Nominal = 1.8V)

Mea

sure

d Sy

stem

Thr

ough

put (

MHz

)

T=-196C

T=21C

T=127C

180nm Prototype Layout

180nm Prototype Die Photograph

180nm Achronix Measured system

throughput of 674 MHz at room temperature at nominal operating

voltage of 1.8V

90nm 1.8V Xilinx Virtex-4 maximum

internal clock speed (system throughput significantly lower)

130nm 1.8V Xilinx Virtex-2 maximum

internal clock speed (system throughput significantly lower)

Source: Xilinx Virtex-II and Virtex-4 data sheets. “Twice as fast” is conservative considering system throughput of Achronix device versus maximum throughput (25% - 80%of internal clock speed) of Xilinx devices.

180nm Prototype Performance

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The 90nm prototype (October 2005) will operate at 1+GHZ speeds at lower power and comparable densities as state-of-the-art FPGAs from Xilinx, Altera, Actel, and others

180n

m

130n

m

90nm

65nm

(200

7)

45nm

(201

0)

32nm

(201

3)0

500

1000

1500

2000

2500

3000

3500

Internal Clock Speed (MHz.,

Stated)

Speed - Achronix measured in System Throughput, Others measured in Maximum Internal Clock Speed

FPGA Speed

ASIC Speed

Achronix FPGA

Achronix PerformanceSpeed:

– 180nm prototype: 674 MHz (measured)– 90nm test chip: 1.4 - 1.6 GHz (Jan 2006)

Power (based on 180nm prototype):– Consumes the same amount of power as

a conventional FPGA operating at 33%the speed (Two thirds less energy per cycle)

Density (based on 180nm prototype):– Competitive with existing state-of-the-art

devices from industry leaders– Will be monotonically higher in 90nm test

chip

*Source: SOCCentral.com Datasheet archive and Xilinx, Altera, Actel, Lattice Datasheets. Power not compared because reliable metrics unavailable, trends likely to mimic speed and density, 45nm and 32nm figures estimated based on trend analysis Years expected for 65,45,and 32nm processes courtesy of “ITRS Roadmap for Semiconductors 2004”

Measured 674MHz with

180nm prototype

Simulated for 90nm test chip

layout (due back from Fab in Jan

06)

No need to migrate to

these processes

now – Maybe ever

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We believe that these levels of speed will be unmatched by Xilinx, Altera, Actel, Lattice, and even most ASIC vendors regardless of which fabrication processes are used

180n

m

130n

m

90nm

65nm

(200

7)

45nm

(201

0)

32nm

(201

3)0

500

1000

1500

2000

2500

Internal Clock Speed (MHz., Stated)

Speed - Achronix measured in System Throughput, Others measured in Maximum

Internal Clock Speed

FPGA Speed

ASIC Speed

Achronix FPGA(Q1 FY06)Achronix FPGA(Q2 FY08)

*Source: SOCCentral.com Datasheet archive and Xilinx, Altera, Actel, Lattice Datasheets. Power not compared because reliable metrics unavailable, trends likely to mimic speed and density, 45nm and 32nm figures estimated based on trend analysis

The Achronix Differentiators: SPEED and COST

By offering unprecedented

speed in an economical 90nm

process with competitive power and

density performance, we will take the high

performance FPGA market

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Asynchronous dataflow computation

Fundamentally, our FPGA operates like a traditional FPGA, but using a different model– Asynchronous dataflow– Tokens hold data values– Tokens flow through pipeline stages– Pipeline stages transform token values

Performance– Latency = input to output delay– Throughput = rate at which tokens are processed

Computation is data-driven not clock-driven– Power savings when circuits are not doing computation– Every gate is “clock gated”

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Fundamentally, the components of the Achronix FPGA are identical to Altera and Xilinx

Switch Boxes (SB) routes channels between logic block

“Logic Blocks” contain the reprogrammable logic, typically in the form of a 4-input Look Up Table (LUT) and other combinational logicThe “Interconnect” provides the infrastructure for communication between switch boxes on the FPGA

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The Achronix FPGA, both at the architectural level and at the logic block level, has a very similar design to typical Xilinx and Altera FPGAs

*Source: Altera Stratix-II datasheet, Xilinx Virtex-4LX Datasheet

High speed synchronous I/Os

Dedicated multiplier blocks

Embedded RAM modules

Asynchronous high speed

programmable logic cells

Altera Stratix-II Architecture and Logic Block Diagram

Xilinx Virtex-4 Architecture and Logic Block Diagram

Achronix Architecture and Logic Block Diagram

Entire unit is called “ALM –

Advanced Logic Module”

4-input LUT plus register is called

“LE – Logic Element”

Entire unit is called “Slice” 4-input LUT plus

register is called “LC – Logic Cell”

Four-Input LUT

State/ConditionalUnit (Token)

4-input LUT plus Conditional unit is called a “logic block” and is very similar to a Xilinx

“LC”

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The detailed circuits that comprise our logic blocks are similar to Xilinx’ “LC” Logic Cells and Altera’s “LE” Logic Elements

Components present in Xilinx LC or Altera LE (plus clock distribution and register logic)

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Our aggressive pipelined interconnect significant increases our performance

Long wires through switches have poor performance– Limits performance of traditional FPGA architectures

ASIC solution: add repeaters/buffers– Improves signal integrity, latency

Aggressive solution– Add pipeline stages to keep throughput high– Synchronous: requires complete design re-timing because data arrives at

different clock tick

Asynchronous pipelining– Adding pipeline stage is “almost always” safe; for deterministic computation it is

always safe

*Source: [MM98] R. Manohar and A.J. Martin. “Slack Elasticity in Concurrent Computing.” Proc. 4th International Conference on the Mathematics of Program Construction, Lecture Notes in Computer Science 1422, June 1998.

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Our switch box architecture is nearly identical to a conventional switch box, but when combined with our interconnect, dramatically increases our speed

Traditional Synchronous “Layered” Interconnect

Achronix Asynchronous Pipelined Interconnect

Traditional FPGA DeficienciesIncreased Latency: Adding pipeline stage encounters one cycle of latency

Interconnect Timing: Requirement of matching numbers of flip-flops after place and route makes pipelining impossible

Increased Complexity: Long-haul routes with increased switch box complexity fundamentally limits complexity and density

Achronix AdvantagesReduced Latency: Adding pipeline stage adds 0.125 cycles of latency

Pipelined Interconnect: Token-based model enables variations in interconnect hop counts, minimizing latency in the interconnect

Modular Design: Elimination of long-haul routes and global signals enables massive scalability

*Source: W. Tsu et al. "HSRA: High-Speed Hierarchical Synchronous Reconfigurable Array." Proc. FPGA 1999

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We tested our 180nm prototype using a variety of well known FPGA benchmarks, and achieved unusually high throughput across a wide range of benchmarks

0

100

200

300

400

500

600

700

Throughput(MHz)

16-b

it Add

er8-b

it Sca

ling A

ccum

ulato

r4x

4 Arra

y Mult

iplier

8-bit 8

-tap F

IR Fi

lter

MIP

S Writ

ebac

k Uni

tSy

stolic

Con

volu

tion

Auto

Cros

s-Cor

relato

r

Benchmarks Performance

0.00%10.00%20.00%30.00%40.00%50.00%60.00%70.00%80.00%90.00%

100.00%

Utilization of Maximum

Throughput

16-b

it Add

er8-b

it Sca

ling A

ccum

ul...

4x4 A

rray M

ultipl

ier8-b

it 8-ta

p FIR

Filte

rM

IPS W

riteb

ack U

nit

Systo

lic C

onvo

lutio

nAu

to Cr

oss-C

orrel

ator


050

100150200250300350400450500

Throughput(MHz)

Max

imum

Inter

nal C

lock

16-b

it Add

er Tr

eeBa

rrell S

hifter

DIP-

4 Par

ity C

heck

erDE

S Enc

rypt

ion18

x18 M

ultip

lier (

DSP)

18x1

8 Mul

tiplie

r (LE

)M

ultp

ly an

d Ac

cum

ulate

Mul

tiplex

er


0.00%10.00%20.00%30.00%40.00%50.00%60.00%70.00%80.00%90.00%

100.00%


Throughput

Max

imum

Inter

nal C

lock

16-b

it Add

er Tr

eeBa

rrell S

hifter

DIP-

4 Par

ity C

heck

erDE

S Enc

rypt

ion18

x18 M

ultip

lier (

DSP)

18x1

8 Mul

tiplie

r (LE

)M

ultp

ly an

d Ac

cum

ulate

Mul

tiplex

er


Achronix Average 636 MHz Altera Stratix-II

Average 334 MHz

Altera Stratix-II Average 66.9% Utilization

Achronix Average 94.4% Utilization

Achronix Measured Performance (180nm)

Altera Stratix-II Measured Performance (90nm)

*Source: Altera Stratix-II “Design Building Block Performance”, August 2005, No data available for Xilinx, but performance is comparable to Altera Stratix-II

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Using the same asynchronous circuit core in 90nm CMOS technology, Achronix has designed an identical FPGA that operates at over 1GHz system throughput

180nm 130nm 90nm

0

200

400

600

800

1000

1200

1400

1600


Stated)


FPGA Speed

ASIC Speed

Achronix FPGA

Measured 674MHz system throughput with

180nm prototype

Simulations of 90nm prototype range from 1.4 – 1.6GHz system

throughput

90nm Simulation Data180nm and 90nm Prototype Performance

10.0

410

.21

10.3

810

.55

10.7

210

.89

11.0

611

.23

11.4

11.5

7

11.7

4

11.9

1

12.0

8

12.2

5

12.4

2

12.5

9

12.7

6

12.9

3

13.1

13.2

7

13.4

4

13.6

1

13.7

8

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

FPGA Output

Nanoseconds

SPICE Simulation Data

Compensated simulations predict performance in the 1.4-1.6 GHz range. We will verify the actual system throughout when the 90nm devices

return from fabrication in January 2006, but we conservatively expect performance well over 1GHz.

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0.00%10.00%20.00%30.00%40.00%50.00%60.00%70.00%80.00%90.00%

100.00%


Throughput

16-b

it Add

er8-b

it Sca

ling A

ccum

ulato

r4x

4 Arra

y Mult

iplier

8-bit 8

-tap F

IR Fi

lter

MIP

S Writ

ebac

k Uni

tSy

stolic

Con

volu

tion

Auto

Cros

s-Cor

relato

r


0

200

400

600

800

1000

1200

1400

Throughput(MHz)

16-b

it Add

er8-b

it Sca

ling A

ccum

ulato

r4x

4 Arra

y Mult

iplier

8-bit 8

-tap F

IR Fi

lter

MIP

S Writ

ebac

k Uni

tSy

stolic

Con

volu

tion

Auto

Cros

s-Cor

relato

r


We expect this prototype to perform at an average throughput of at least 1.3GHz (based on simulations)

050

100150200250300350400450500

Throughput(MHz)

Max

imum

Inter

nal C

lock

16-b

it Add

er Tr

eeBa

rrell S

hifter

DIP-

4 Par

ity C

heck

erDE

S Enc

rypt

ion18

x18 M

ultip

lier (

DSP)

18x1

8 Mul

tiplie

r (LE

)M

ultp

ly an

d Ac

cum

ulate

Mul

tiplex

er


0.00%10.00%20.00%30.00%40.00%50.00%60.00%70.00%80.00%90.00%

100.00%


Throughput

Max

imum

Inter

nal C

lock

16-b

it Add

er Tr

eeBa

rrell S

hifter

DIP-

4 Par

ity C

heck

erDE

S Enc

rypt

ion18

x18 M

ultip

lier (

DSP)

18x1

8 Mul

tiplie

r (LE

)M

ultp

ly an

d Ac

cum

ulate

Mul

tiplex

er


Achronix Average 1.32 GHz Altera Stratix-II

Average 334 MHz

Altera Stratix-II Average 66.9% Utilization

Achronix Average 94.4% Utilization

Achronix Expected Performance (90nm) Altera Stratix-II Measured Performance (90nm)

*Source: Altera Stratix-II “Design Building Block Performance”, August 2005

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Our architecture also allows for temperature insensitivity

Key features of class of asynchronous circuits we are using– Tolerant to arbitrary variations in gate delay– Tolerant to conductivity changes in wires

CMOS devices have a wide operating range

Nominal net effect of temperature change– Delay change– We have no PLLs, oscillators, or other analog circuits for clock distribution

Asynchronous circuits are naturally temperature insensitive– Change in temperature impacts performance, but circuits still operate correctly

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Temperature Insensitivity

26

Temperature Insensitivity

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Measured Peak Performance with Temperature (180nm)

AFPGA Performance

0

200

400

600

800

1000

1200

0 0.5 1 1.5 2 2.5Voltage

Freq

uenc

y 12K77K294K400K

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Radiation tolerance will be achieved by a RADHARD by design approach on SOI

Technology + design approach

Asynchronous self-correction for event upsets– When a gate has an event upset (logic fault), we can wait for the upset to self-

correct and locally stall the computation

Circuits are encoded– Data representation used has redundancy– Redundancy can be used for cross-checking values with a simple circuit

technique

Deep sub-micron SOI allows us to use “RADHARD by design” methods– Gate layout geometries

We are investigating this experimentally in 2006, but plan to support 100krad – 300krad TID

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Since our announcement about our prototype in September we have spoken to over 20 potential customers. This has driven our architecture road map.

Achronix 90nm Product Road Map

Predicted Performance – 90nm

140% increased in speed30% reduction in power consumption

30% increase in density50% Risk

Shipping in 1H2008

10% decrease in speed65% reduction in power consumption


Shipping in 2H2007

No decrease in speedNo reduction in power consumption


Shipping in 1H2008

Speed Focus

Power Focus

Density Focus

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High Performance FPGAs

0

500000

1000000

1500000

2000000

2500000

0.00 0.20 0.40 0.60 0.80 1.00 1.20

Cost Per Device (A.U.)

ASI

C E

quiv

alen

t Gat

es

Stratix II

Virtex-4

Using our familiar architecture with an asynchronous core, our first product will significantly outperform industry leaders’ products in terms of speed and power

…and while our unit density is lower, our ability to scale density enables us to build devices with comparable density as industry leaders, but at

lower cost

180nm 130nm 90nm

0

200

400

600

800

1000

1200

1400

1600


Stated)


FPGA Speed

ASIC Speed

Achronix FPGA

Speed Performance

Power Performance (Historical Data for Asynchronous Circuits)

Density Performance (Expected @ 90nm)

*Source: Achronix testing of 180nm device, Achronix simulations of 90nm device, Pricing and density data from Xilinx and Altera Websites and AVNET list pricing from website

Achronix density band

Achronix expected circuit power performance: 36%-63% lower

Device Type Sychronous Asyhcnronous Metric Sychronous Asyhcnronous Asychronous D

Processor Orion R4600 MiniMIPS2V (1998) MIPS2/ E 1125 3100 63.71%16-bit Adder MCC Adder MCC Async Adder E/ ins 4.7 3 36.17%

Device Type Power Performance

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High Performance FPGAs

0

500000

1000000

1500000

2000000

2500000

0.00 0.20 0.40 0.60 0.80 1.00 1.20

Cost Per Device (A.U.)

ASI

C E

quiv

alen

t Gat

es

Stratix II

Virtex-4

Since we can scale our density with die size, our supported density becomes a business decision for our first lines of products, rather than a technical challenge

Achronix-ULTRA

density-pricing band

Achronix-XTREME density-

pricing band

Target Product SpecsAchronix-ULTRA Specs

– Speed: 1.4 – 1.6 GHz throughput– Power: Not a pricing factor. Will be

lower than Altera Stratix-II and Xilinx Virtex-4

– Density: 1M to 1.5M AEG (80k-120k LUTs)

– Op. Temp = -264 to + 130 C

Achronix-XTREME Specs– Speed: 1.0 – 1.2GHz throughput– Power: Not a pricing factor. Will be

lower than Actel RTAX-S– Density: 1+M AEG (80k LUTs)– Op. Temp = -264 to + 130 C– Radiation Tolerance = 100-300 krad

33

Because the Achronix FPGA is based on a familiar architecture, and utilizes synchronous interfaces, customers can leveraging existing software infrastructure

Accepts input from any type of description language

Achronix Tool Chain

Example: Celoxica Interface

Example: Synplicity/Cadence/Mentor Graphics Interface

BehavioralVerilog

C-Like Input

High-level functional input

(MATLAB, LABVIEW)

Verilog Asychronous

Translator

RTL-level Functional Description

Easy

Easier

Easiest

Bit level netlist generator for data

flow

Place and Route Tool

Sim

ulat

or

FPGA Mapped, Placed, and

Routed

Achronix software development efforts will focus on the entire tool chain, but particularly

on these component in 2006

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This aggressive hardware and software strategy will allow us to accomplish our key goals

Achronix Key GoalsUltra fast Speed

– Support system throughputs in the 1 GHz (2006) to 2.5 GHz (2008) range through our novel asynchronous FPGA fabric

Competitive Density and Power Performance– While operating at GHz speeds, provide competitive density and power performance to state of

the art devices from Xilinx, Altera, Actel, and Lattice

Synchronicity and Interoperability– At the system level, look and feel just like a traditional synchronous FPGA from Xilinx, Altera,

Actel, Lattice, and others by surrounding our fabric with traditional synchronous I/Os

Support the Existing EDA Landscape– Support existing EDA tools used by FPGA and ASIC designers to ensure that our products can be

integrated easily and immediately and replace slower parts from or competitors

*Source: Simulations of Achronix 90nm design. Real results to be determined in January 2006

We would like to understand what other specific features/goals that the extreme environment community would like to see in our product, and

when you would like to see the product

Achronix Semiconductor Corporation427 East Seneca Street, Suite 100Ithaca, NY, 14850USA

Phone: +1.877.GHZ.FPGA (877.449.3742)Fax: +1.413.280.9887Internet: http://www.achronix.comEmail: [email protected]

Achronix Technology and Product Overview Presented: November 15, 2005 – NASA Goddard Space Flight...

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Transcript of Achronix Technology and Product Overview Presented: November 15, 2005 – NASA Goddard Space Flight...