ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Low-Power CMOS Design For Advanced...

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Low-Power CMOS Design

For Advanced VLSI Design and VLSI Signal Processing Courses

12-04-2002

台大電機系吳安宇教授

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 2

Data SourceData Source

“Low-power Circuit Design Basics,” by Prof. Jan M.

Rabaey, UC Berkerly, in tutorial of ISCAS, London,

1994.

“Can we simultaneously achieve High Speed and L

ow Power in IC Design?” by Prof. Wentai Liu in 7th

VLSI/CAD Symposium, 1996.

Chapter 17 of Textbook “VLSI Digital Signal Proces

sing Systems: Design and Implementation," by K. K.

Parhi, Wiley-Interscience Publication, 1999.


pp. 3

Low Power Design – Low Power Design – An Emerging DisciplineAn Emerging Discipline

Historical figure of merit for VLSI design – performance (circuit speed) and chip area (circuit density/cost). But

Power dissipation is now an important metric in VLSI design. No single major source for power savings across all design

levels – Required a new way of THINKING!!! Companies lack the basic power-conscious culture and

designers need to be educated in this respect.

Overall Goal – To reduce power dissipations but maintaining adequate throughput rate.


pp. 4

Motivation - MicroprocessorMotivation - Microprocessor


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Motivation - MicroprocessorMotivation - Microprocessor


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Competitive Reasons – Low PowerCompetitive Reasons – Low Power Battery Powered Systems – Extended Battery Life an

d reduce weight and size. High-Performance Systems

CostPackage (chip carrier, heat sink, card slots, plenum, …)Power Systems (supplies, distribution, regulators, …)Fans (noise, power, reliability, area, …)Operating cost to customer – Energy Star issue.

ReliabilityFailure rate increase by 4X for Tj @ 110C vs 70CMission critical operation at 100C

Size and Weight – Product footprint (office and deskspace)


pp. 7

The Power Crisis : PortabilityThe Power Crisis : Portability

Expected Battery Lifetime increaseOver next 5 years: 30-40%

PDA, Cellular Phone,Notebook Computer,etc.


pp. 8

A Multimedia Terminal – The InfopadA Multimedia Terminal – The Infopad

Present day battery technology (year 1990) – 20 lbs for 10hrs


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IC Design SpaceIC Design Space


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Low Power DesignLow Power DesignSource of power disspation

P = P switching + P short-circuit + P leakage + P static

Definitions:Switching power P = CV2fαShort circuit power P = IscV

Leakage power P = IleakageV

Static power P = IstaticV

α : switching activity factor

Low power design would look at the trade-offs of the above issues


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Dynamic Power ConsumptionDynamic Power Consumption

Not a function of transistor sizes!Need to reduce CL, Vdd, and f ti reduce power

Reduce the probability, P0 -> 1

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f


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Dynamic Power Consumption - ExtendDynamic Power Consumption - Extendeded

Power = Energy/transition * transition rate

= CL * Vdd2 * f0->1

= CL * Vdd2 * P0->1 * f

= CEFF * Vdd2 * f

Power Dissipation is Data Dependent Function of Switching Activity

CEFF = Effective Capacitance = CL * P0->1


pp. 13

Ultra Low Power System DesignUltra Low Power System Design Power minimization approaches:

Run at minimum allowable voltageMinimize effective switching capacitance


pp. 14

ProcessProcess Progress in SOI and bulk silicon

(a) 0.5V operation of ICs using SOI technology (b) 0.9V operation of bulk silicon memory, logic, and

processors

Increasing densities and clock frequencies have pushed the power up even with reduce power supply


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Choice of Logic StyleChoice of Logic Style


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Choice of Logic StyleChoice of Logic Style

Power-delay product improves as voltage decreases The “best” logic style minimizes power-delay for a given del

ay constraint


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Power Consumption is Data Power Consumption is Data DependentDependent

Example : Static 2 Input NOR Gate

Assume : P(A=1) = ½ P(B=1) = ½Then : P(Out=1) = ¼ P(0→1) = P(Out=0).P(Out=1)

=3/4 * 1/4 = 3/16

CEFF = 3/16 * CL


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Transition Probability of 2-input NOR Transition Probability of 2-input NOR GateGate

as a function of input probabilities


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Switching Activity (Switching Activity (αα) : Example) : Example


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Glitching in Static CMOSGlitching in Static CMOS


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At the Datapath Level…At the Datapath Level…ReusableIrregular


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Balancing OperationsBalancing Operations


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Carry RippleCarry Ripple


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Data RepresentationData Representation


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Low Power Design Consideration (cont’)Low Power Design Consideration (cont’)

(Binary v.s. Gray Encoding)


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Resource Sharing Can Increase Resource Sharing Can Increase ActivityActivity

(Separate Bus Structure)


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Resource Sharing Can Increase Resource Sharing Can Increase Activity (cont’d)Activity (cont’d)


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Operating at the Operating at the Lowest Possible Voltage!Lowest Possible Voltage!

Desire to operate at lowest possible speeds (using low supply voltages)

Use Architecture optimization to compensate for slower operation

Approach : Trade-off AREA for lower POWER


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Reducing VReducing Vdddd


pp. 30

Lowering VLowering Vdd dd Increases DelayIncreases Delay

• Concept of Dynamic Voltage Scaling (DVS)


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Architecture Trade-offs : Reference Architecture Trade-offs : Reference Data PathData Path


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Parallel Data PathParallel Data Path


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Pipelined Data PathPipelined Data Path


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A Simple Data Path : SummaryA Simple Data Path : Summary


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Computational Complexity of DCT Computational Complexity of DCT AlgorithmsAlgorithms


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Power Down TechniquesPower Down Techniques• Concept of Dynamic Frequency Scaling (DFS)


pp. 37

Energy-efficient Software CodingEnergy-efficient Software Coding Potential for power reduction via software

modification is relatively unexploited. Code size and algorithmic efficiency can significantly

affect energy dissipation Pipelining at software level- VLIW coding style Examples -


pp. 38

Power Hunger – Clock Network Power Hunger – Clock Network (Always Ticking)(Always Ticking)

H-Tree – design deficiencies based on Elmore delay model

PLL – every designer (digital or analog) should have the knowledge of PLL

Multiple frequencies in chips/systems – by PLLLow main frequency, ButJitter and Noise, Gain and Bandwidth, Pull-in and Lock

Time, Stability …

Local time zone Self-Timed Asynchronous => Use Gated Clocks, Sleep Mode


pp. 39

Power Analysis in the Design FlowPower Analysis in the Design Flow


pp. 40

Human Wearable Computing - PowerHuman Wearable Computing - Power Wearable computing – embedding computer into clothing

or creating a form that can be used like clothing Current computing is limited by battery capacity, output

current, and electrical outlet for recharging


pp. 41

ConclusionsConclusions High-speed design is a requirement for many applications

Low-power design is also a requirement for IC designers.

A new way of THINKING to simultaneously achieve both!!!

Low power impacts in the cost, size, weight, performance, an

d reliability.

Variable Vdd and Vt is a trend (DVS and DFS)

CAD tools high-level power estimation and management

Don’t just work on VLSI, pay attention to Microelectromechanical Systems (MEMS) – lots of problems and potential is

great.


pp. 42

ApplicationsApplicationsPortable Multimedia TerminalWireless C&CSystem on Chip (From Dr. Yang of Windbon

d)


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Applications IApplications IWireless Computing/CommunicationWireless Computing/Communication


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Applications IIApplications IIA Portable Multimedia TerminalA Portable Multimedia Terminal


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Applications IIIApplications IIISystem Value of IC ProductSystem Value of IC Product

Concept of lays


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Applications IVApplications IVSystem on ChipSystem on Chip

Entire system functionLogic + MemoryMore than two types of devices

Allow more freedom in architectureConst/Performance trade-off


pp. 47

Applications VApplications VNew Opportunity for Taiwan IC IndustryNew Opportunity for Taiwan IC Industry

PASTDigital ICµ PIBM Compatible + MD-DOS

FUTURESystem On Chip

Reduce head-on competition on standard productsTechnology will be availableManufacturing Service availableSame starting point as other countriesCan have more R/D focus

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Low-Power CMOS Design For Advanced...

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