Accelerate Your IoT DesignTony Qian. Design Engineering Group Director, DDR. Design & Reuse IP SoC...
Transcript of Accelerate Your IoT DesignTony Qian. Design Engineering Group Director, DDR. Design & Reuse IP SoC...
Tony QianDesign Engineering Group Director, DDRDesign & Reuse IP SoC ShanghaiSeptember 2, 2016
Accelerate Your IoT Design
2 © 2016 Cadence Design Systems, Inc. All rights reserved.
Wearables
GlassesCameras
FitBitHearing aid
Smart watches
Smart Home
HVAC/climate control
Lighting controlSurveillance and access control
Appliances
Healthcare
Professional heathcareequipmentOutpatient heathcare
devices/monitors
Automotive
Operation controlHazard sensingKeyless entry
Infrastructure
AMI/smart metersConcentrators
Accessories
Remote controlAudio speakersMotion sensors
Gesture recognition
Voice recognition
The Market Challenge – Diversity in IoTIoT ranges from Simple to Complex
3 © 2016 Cadence Design Systems, Inc. All rights reserved.
Crypto TIE
DSP TIE
CommsTIE
SensorFusion TIE
Fusion DSP
On-Chip FlashMemory
PLL/Clock
PMU/Charging/ LDO
PVT SensorDAC/ADC
PHY
Low-PowerWiFi
BT/BLEAFE
Sensor Peripheral HubUSB2Device
Charging
BT/BLERF
WirelessBT/BLE
Only
ThermostatLightMEMS
MoistureSensor
Sen
sors
DACDAC
ADCADC
VoiceTrigger
AccelerometerGyro
On-Chip SRAMMemory
UA
RT
I2C SP
I
I2S
Sou
ndW
ire
Sen
sorW
ire
PW
M
Low-power Sensor IoT PlatformDeep embedded, connecting to various sensors
4 © 2016 Cadence Design Systems, Inc. All rights reserved.
Display
Crypto TIE
DSP TIE
CommsTIE
SensorFusion TIE
FusionHiFi DSP
LPDDR4/3
QSPI
PLL/Clock
PMU/Charging/ LDO
PVT SensorPHY
Low-PowerWiFi
BT/BLEAFE
Peripheral HubUSB2OTG
Charging
UA
RT
I2C SP
I
I2S
Sou
ndW
ire
Sen
sorW
ire
BT/BLERF
Wireless Partners
BT/BLEOnly
802.11nRF
WiFiOnly
ComboRF
BT/WiFiCombo
Sen
sors
GenericCPUCore
DACDAC
ADCADC
Camera Sensor
VoiceTrigger
AccelerometerGyro
On-Chip SRAMMemory
WirelessMAC
D-RAM
DMA
I-RAM
I-Cache
Vision DSP CoreV
isio
n/D
ispl
ay
PHY
MIPICSI
PHY
MIPIDSI
PW
M
High-performance Wearable IoT PlatformVoice, vision, motion, sensors
5 © 2016 Cadence Design Systems, Inc. All rights reserved.
The IoT Solution
6 © 2016 Cadence Design Systems, Inc. All rights reserved.
Power
Radio
uP
SensorsActuators D
ifferentiation
Breaking Down an IoT SoCFrom Concept to Building Blocks
Major functional blocks (IoT)− uP
− Microcontroller, CPU, and/or DSP
− Radio− BLE, WiFi, wireless connection or radio design
− Sensor/mems− I2C, MIPI I3C, SPI, or sensor integration
− Power/timing− PLLs, OSCs, USB Type-C, PMU, programmable voltages,
VT sensor, shut off, sleep modes, clock gating
− Differentiating IP− LPDDR, NAND flash, MIPI SoundWire (audio), CSI
(camera), DSI (display), security, others
7 © 2016 Cadence Design Systems, Inc. All rights reserved.
Key IP to enable IoT SoCs− PHYs, controllers, drivers− Proven integration and interoperability− Ability to customize and differentiate your product
Tailored for IoT applications− Low power and small area− Low risk, low effort− Fast time-to-market
Subsystem solutions− Sensors: I2C, MIPI I3C, SPI, UART− Audio: SLIMbus, SoundWire, I2S, Tensilica® HiFi− Video/display: MIPI CSI/DSI, D-PHY, Tensilica
Vision P5− Memory/storage: LPDDR, SD, eMMC− Interface: USB, PCIe®, Ethernet− Radio: ADC/DAC/AFE, SDIO, Dig-RF− Timing: PLLs, OSCs, monitors
Memory
LPDDR 2/3
LPDDR4 eMMC
SD/SD Card
AMS
ADC/DACAFE
PLL/OSC
VTmonitors
Interfaces
DSI
CSI
UniPro
SoundWire
USB 2/3
USB 2 PHY
USB OTG
10/100 PHY
SDIO
D-PHY LP DDRPHY
Tensilica Processing
Audio Imaging
Peripherals
I2CI3C I2S UART SPI
QSPI PWM
I3C
10/100 MAC
SD/eMMCPHY
IP enablement for quick integration, system differentiation, and broad application
Cadence IoT SoC Design IPCustomizing Your IoT Product
8 © 2016 Cadence Design Systems, Inc. All rights reserved.
55ULP/40 ULP
Application-optimizedprocesses
Design IPIoT solutions
Referenceflows and scripts
Optimizeddesign solutions
Applications Processor
CustomLogic
Memory
DDR/LPDDR
W IDE IOHBM, HMC
SD/SDIO/eMMC, UFS
NAND,ONFI, Toggl
e
Ethernet
PCIe®
USB
SSIC
System
sPeripherals
MIPI
HDMI, MHL,
DP/eDP
M-PCIe™
AFE
ADCDAC
PVTLDO, POR, PLL/OSC
Xtensa ®
Embedded control & DSP
Communications
Customer-owned Instruction Set
Sensor Fusion
Vision / Imaging
Audio / Voice / Speech
GPU
Lowest riskShortest time-to-silicon
Low cost and fast developmentMost advanced technologyreadiness and innovation
The most advancedIoT processors
Designing IoT SoCs Faster and CheaperAchieved through Collaboration
TensilicaDSP Processor
TensilicaHigh-Performance
DSP Processor
9 © 2016 Cadence Design Systems, Inc. All rights reserved.
HDS: Hosted Design Services
• Enablement– Complete SoC tool flow enablement– Customer proven, secure, and in use
• Productivity/flexibility– Start to design from day one in proven environments– Screen sharing between multiple sites and teams– Environment upgrade on demand: hardware, storage, licenses
• Support– Application support without need for testcase creation– Design and methodology support– 24x7 IT support
Customer Site
Cadence Hub
Design Team CadenceRemoteDesktop
VPN
CAD and IT
VPN
Design Database
Customer Hosted Design Solution
PackagedDesign
Environment
Services Experts
ComputeResources
Tools andPlatforms
IT
3rd-Party
Software
DesignServices
Methodology Services
VCAD Productivity Packages
Hosted Design
SolutionEducational
Services
DFMServices
Optimized low-cost tool flow and methodology for IoT enablement
Cadence Hosted Design ServicesTool Enablement – Fast and Easy
10 © 2016 Cadence Design Systems, Inc. All rights reserved.
Cadence System Design EnablementTools from Design to Product
*CPU
Cadence
*PDK
Third Party
SiP
*IoT SDKs
Cadence/CPU IoT RTL
Software Development
kits
C Code
CPU Instructions
Virtuoso® ADE Schematic & RTL
Spectre® / Incisive®
Simulation & Verification
Low-Power Intent
(CPF/UPF)
Verified Design
VDI / Innovus™ OA Flow
Floorplanning
AnalogBlock
DigitalBlock
Chip Integration
Tempus™/Voltus™/
Quantus™ Solutions
Genus™ Synthesis and Test
Third-PartyIP
Flash MemorySRAM
MEMS+
CadenceSiP Layout
Cadence®
IP *PDK Catalog Parts
Allegro /OrCAD® Solutions
Allegro®/ PSpice® Solutions
Verified Design
Design/IP/Software SoC PCB
Sigrity™
Solution
MCAD /Enclosure
SoC hostedSystem hosted
• Complete system design environment
– IP and software– SoC design tools– Packaging tools– PCB tools
• No hardware, IT, or infrastructure overhead
– No servers to be purchased –host on Cadence servers
– No IT requirements –maintained by Cadence, just log in
• No tools mainenance andupgrades
– Managed by Cadence– Update to latest versions as
needed
11 © 2016 Cadence Design Systems, Inc. All rights reserved.
Cadence System Design EnablementTools from Design to Product
*CPU
Cadence
*PDK
Third Party
SoC hostedSystem hosted
Optimal time-to-productivityReady-to-go design environ.
Risk mitigationSecure, known set-up
Lowered TCO & cash flowPayment based on level of use
ScalabilityHardware and software can
react to needs
SiP
*IoT SDKs
Cadence/CPU IoT RTL
Software Development
kits
C Code
CPU Instructions
Virtuoso® ADE Schematic & RTL
Spectre® / Incisive®
Simulation & Verification
Low-Power Intent
(CPF/UPF)
Verified Design
VDI / Innovus™ OA Flow
Floorplanning
AnalogBlock
DigitalBlock
Chip Integration
Tempus™/Voltus™/
Quantus™ Solutions
Genus™ Synthesis and Test
Third-PartyIP
Flash MemorySRAM
MEMS+
CadenceSiP Layout
Cadence®
IP *PDK Catalog Parts
Allegro /OrCAD® Solutions
Allegro®/ PSpice® Solutions
Verified Design
Design/IP/Software SoC PCB
Sigrity™
Solution
MCAD /Enclosure
12 © 2016 Cadence Design Systems, Inc. All rights reserved.
Enabling System DesignFrom Chip to End Product for IoT, Automotive
Vision and leadershipBroad portfolio
Commitment to innovationCustomer success
© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. PCI-SIG®, PCI Express®, and PCIe® are registered trademarks and/or service marks of PCI-SIG. All other trademarks are the property of their respective holders.