IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 9, SEPTEMBER 2008 1059

Abrupt NMOS Inverter Based on Punch-ThroughImpact Ionization With Hysteresis in the

Voltage Transfer CharacteristicsKirsten E. Moselund, Student Member, IEEE, Didier Bouvet, and Adrian Mihai Ionescu, Senior Member, IEEE

Abstract—In this letter, an abrupt NMOS inverter based onpunch-through impact ionization is demonstrated for the firsttime. The slopes for both the rising and the falling edge of theID(VGS) device characteristics are less than 10 mV/decade steepwhich translates into a gain of −80 for the inverter. In addition,the voltage transfer characteristic shows a hysteresis whose widthdepends on the biasing. The output swing is approximately twicethe input voltage swing, which assures proper cascadability oflogic gates.

Index Terms—Avalanche breakdown, impact ionization,inverters.

I. INTRODUCTION

ONE OF THE fundamental limits of the MOSFET is the60-mV/decade minimum value of the inverse subthresh-

old slope at room temperature imposed by the drift–diffusiontransport mechanism, which determines the ability to turn offthe device. With continued scaling and reduction of bias volt-ages, the inverse subthreshold slope deteriorates even furthercompared to this ideal value. Thus, in the past couple of years,there has been a rising interest in alternative devices such as theimpact ionization MOS (IMOS), which is first presented in [1]in which the slope is reduced by an amplification of the on levelby avalanche multiplication.

The IMOS presented in [1] and [2] is basically a gated p-i-nstructure, where the gate voltage is used to adjust the break-down voltage. The main advantage is the ability to amplify Ion

while keeping Ioff low; however, reliability is an issue due to theproximity of the avalanche-generated carriers to the gate oxide,although this can be improved by a vertical structure [3].

Recently, we proposed the punch-through IMOS (PIMOS)in [4]–[6] which, like the IMOS, relies on avalanching to obtainslopes of less than 10 mV/decade. In addition, the PIMOS alsopresents a hysteresis profile in both the ID(VDS) and ID(VGS);the latter, shown in Fig. 1, is of main interest for the inverter.For low drain voltages, this device operates as a conventionalshort-channel MOSFET, but when VDS attains the breakdownvoltage VDBD, an abrupt switch and hysteresis are observed.

Manuscript received May 19, 2008. The review of this letter was arrangedby Editor C. Bulucea.

The authors are with Nanoelectronic Devices Laboratory, NanoLab at theSwiss Federal Institute of Technology (EPFL), 1015 Lausanne, Switzerland(e-mail: Kirsten.Moselund@epfl.ch; didier.bouvet@epfl.ch; adrian.ionescu@epfl.ch).

Color versions of one or more of the figures in this letter are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LED.2008.2001632

Fig. 1. Experimental abrupt switching and hysteresis in ID(VGS) for aPIMOS device of L = 1.4 µm and W = 10 µm. Increasing VDS widens thehysteresis by displacing the down transition D → E, whereas the up transitionA → B remains more or less fixed. Two curves for normal MOS operationare shown with VDS = 0.2 and 8.3 V, respectively. The point C is shiftingcorresponding to a simultaneously increasing VGS and decreasing VDS.

When VDS is further increased, the hysteresis widens until thepull-down is no longer reached within a reasonable value ofVGS, and the output stays latched in the high level. In thisletter, we will present an NMOS inverter based on the PIMOS,which is able to reproduce the abrupt swing and hysteresis inthe voltage transfer characteristics (VTCs).

II. PIMOS DEVICE AS ABRUPT HYSTERETIC SWITCH

The PIMOS structure is identical to that of a MOSFET,even though the optimization of device parameters differs fromconventional CMOS. The principle of operation is very similarto the floating-body effect in partially depleted SOI [7]–[9]. Inthe PIMOS, the condition of punch-through, i.e., merging ofthe two depletion zones, in subthreshold creates an electrostaticsaddle point near the channel at the drain side. At high drainbias, avalanche-generated holes will accumulate here, therebycreating a virtual floating-body effect [10] which will reduce thedevice threshold voltage. The saddle point also has the effectof pushing the electron current toward the bulk, as shown inFig. 2. Another part of the holes constitutes a substrate current,which causes a voltage drop across the substrate resistance,Rsub, which will eventually forward-bias the source–substratejunction and turn on a parasitic bipolar structure. The bipolaraction will further amplify the drain current, leading to a

0741-3106/$25.00 © 2008 IEEE

1060 IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 9, SEPTEMBER 2008

Fig. 2. TCAD simulation (DESSIS) showing the electron current distributionat breakdown in a PIMOS device with the schematic of the parasitic bipolar inparallel. The hole pocket at the interface pushes the electron current toward thebulk. VDS = 11.5 V, NA = 5 × 1014 cm−3, and tox = 10 nm.

positive feedback loop. This effect is self-limiting; as the bodypotential increases, the drain saturation voltage will increase,thereby reducing the electric field and the impact ionization.In our case, the condition of punch-through is met, and impactionization is gradually initiated well before breakdown, so itis the turn-on of the parasitic bipolar which determines thepoint of breakdown. The hysteresis is caused by the parasiticbipolar transistor combined with the hole pocket, which keepsthe current in the high level as long as the source–substratejunction is forward biased.

As short-channel effects are inherent to device functionality,i.e., the punch-through condition, the device presents a fairlylarge subthreshold leakage. Basically, the leakage is a tradeoffagainst reduced breakdown voltage VDBD. Both depend onthe device parameters, particularly device length. When L isreduced, VDBD is reduced as well, but Ioff increases. De-tails of device fabrication and electrical characteristics can befound in [5].

III. NMOS IMPACT IONIZATION INVERTER

An NMOS inverter based on hybrid PIMOS and MOSFET isimplemented on-chip along a single body-tied silicon wire (seeFig. 3). The two top NMOS devices connected to VDD serveas resistive loads, whereas the input device is a PIMOS. Thedual-load architecture is solely a result of the availability ofdevices with PIMOS functionality; an optimized single pull-upload would be preferable.

The used bias scheme employs a grounded VDD and anegative VCC. This is due to limitations connected with themeasurement setup and the number of probes available. Be-cause the device is symmetrical, there is no particular advantageto an alternative biasing scheme, such as it is the case for theIMOS [11].

One of the peculiarities of the PIMOS consists in the twodifferent modes of operation. When VDS < VDBD, the devicewill work as a conventional short-channel MOSFET, whereasfor VDS > VDBD, it works in impact ionization mode. The valueof VDBD is determined by VGS and device parameters.

Fig. 3. SEM image of the NMOS inverter with two-transistor resistive loadon a body-tied wire and schematic of biasing scheme. The inset shows a crosssection of the actual device, showing the shape of the silicon core/channelsurrounded by gate oxide and the polysilicon gate.

This translates into the following three distinct modes ofoperation for the input device. 1) The input transistor is off(Vin < VT ); while the two loads are conducting in saturation,and VDD is passed to the output. 2) The input device operates inthe PIMOS mode, VDD > VDBD, and Vin > VGPU. The outputwill be pulled abruptly down to the value of VDBD. 3) The inputtransistor conducts in normal mode. Here, all devices are on; thevalue of the output will be determined by the resistive dividerchain, and the value of Vin compared with VDD.

Thus, the PIMOS inverter VTC (Fig. 4) is different fromboth that of a conventional CMOS and an IMOS-based in-verter, in that it incorporates three distinctly different regionsof operation. A qualitative schematic of the PIMOS ID(VGS)characteristic is shown beneath to improve the comprehension.The transitions A → B and D → E correspond to the abrupttransitions, whereas the mobile point C will continue to de-crease with increasing Vin = VGS because this will decrease thevalue of Vout = VDS.

Unlike an IMOS [2], [12], the PIMOS should be able toobtain a full NMOS inverter swing because, after the PIMOSoperation ends, the conventional MOSFET operation will con-tinue to pull down the output until the point determined by theload network, i.e. a resistive divider in the case of an N-PIMOSinverter. The hysteresis width in the VTC can be optimized bythe value of the supply voltage.

The VTC in Fig. 4 shows the following two curves: VDD −VCC = 7 V for the normal NMOS inverter and VDD − VCC =8.1 V where the input device operates in the impact ionizationregime, resulting in a very abrupt transition and hysteresis. Thewidth of the hysteresis is determined by the VDS value, i.e., thevalue of Vout − VCC when the PIMOS is on. The inverter gaindefined as dVout/dVin increases as impact ionization sets in.Values up to −80 are achieved at the transition point, uniquelydue to the abruptness of I(V ) off–on and on–off transitions.Note that such abruptness of the VTC is not possible using anIMOS [2], [12] because this device does not saturate.

The PIMOS inverter has not only a high gain but also anoutput swing (∆Vout ∼ 1 V) that is larger than the minimuminput swing (∆Vin ∼ 0.5 V), ensuring possible cascadabilityof logic gates.

While the PIMOS inverter has potential for lower dynamicpower consumption and improved speed compared with CMOSdue to reduced swing, its standby power will be significantly

MOSELUND et al.: ABRUPT NMOS INVERTER BASED ON PUNCH-THROUGH IMPACT IONIZATION 1061

Fig. 4. PIMOS inverter VTCs for the NMOS inverter, and beneath it is aschematic of the related ID(VGS) characteristics for the PIMOS device. TheVTC shows two characteristics; normal MOS operation, close to avalanchebreakdown VDD − VCC = 7 V, and biased at the center of the hysteresisloop, VDD − VCC = 8.1 V. Transition A → B is at high VDS ≈ 8.1 V,whereas transition C → D is at low VDS ≈ 7.3 V; both VDS values arewithin the hysteresis window. The voltage step for the measurement is 10 mV.L = 1.4 µm and W = 2 µm.

higher because of the large Ioff . Target applications will thus befor high speed or analog, where the unique abrupt slopes andhysteresis are exploited.

IV. CONCLUSION

A hysteretic impact ionization NMOS inverter with abruptswitching in the VTCs has been demonstrated for the first time.

The inverter has a gain of −80 and a hysteresis width which de-pends on the supply voltage VDD − VCC. The PIMOS inverterincorporates three distinct regimes of operation, namely, off,PIMOS mode, and MOSFET mode, and has an output swinglarger than the input one, enhancing cascadability.

REFERENCES

[1] K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, “I-MOS: A novelsemiconductor device with a subthreshold slope lower than kt/q,” inIEDM Tech. Dig., 2002, pp. 289–292.

[2] K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, “Impact ionizationMOS (I-MOS)—Part I: Device and circuit simulations,” IEEE Trans.Electron Devices, vol. 52, no. 1, pp. 69–76, Jan. 2005.

[3] U. Abelein et al., “Improved reliability by reduction of hot-electron dam-age in the vertical impact-ionization MOSFET (I-MOS),” IEEE ElectronDevice Lett., vol. 28, no. 1, pp. 65–67, Jan. 2007.

[4] K. E. Moselund, V. Pott, D. Bouvet, and A. M. Ionescu, “Abrupt currentswitching due to impact ionization effects in Ω-gate MOSFET on lowdoped bulk silicon,” in Proc. ESSDERC, 2007, pp. 287–290.

[5] K. E. Moselund, V. Pott, D. Bouvet, C. Meinen, M. Kayal, andA. M. Ionescu, “Punch-through impact ionization MOSFET (PIMOS):From device principle to applications,” Solid-State Electron. to be pub-lished, ESSDERC 2007 special ed.

[6] K. E. Moselund, V. Pott, D. Bouvet, and A. M. Ionescu, “Hystereticinverter-on-a-body-tied-wire based on less-than-10 mV/decade abruptpunch-through impact ionization MOS PIMOS switch,” in VLSI Symp.Tech. Dig., Taiwan, R.O.C., 2008, pp. 22–23.

[7] C.-E. D. Chen et al., “Single-transistor latch in SOI MOSFETs,” IEEEElectron Device Lett., vol. 9, no. 12, pp. 636–638, Dec. 1988.

[8] J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI,2nd ed. Norwell, MA: Kluwer, 2002.

[9] J. G. Fossum, R. Sundaresan, and M. Matloubian, “Anomalous sub-threshold current—Voltage characteristics of n-channel SOI MOS-FETs,” IEEE Electron Device Lett., vol. EDL-8, no. 11, pp. 544–546,Nov. 1987.

[10] A. Boudou and B. S. Doyle, “Hysteresis IV effects in short-channel sili-con MOSFETs,” IEEE Electron Device Lett., vol. EDL-8, no. 7, pp. 300–302, Jul. 1987.

[11] W. Y. Choi, J. Y. Song, J. D. Lee, Y. J. Park, and B.-G. Park, “A novel bi-asing scheme for I-MOS (impact-ionization MOS) devices,” IEEE Trans.Electron Devices, vol. 4, no. 3, pp. 322–325, May 2005.

[12] F. Mayer, C. Le Royer, G. Le carval, L. Clavelier, and S. Deleonibus,“Static and dynamic TCAD analysis of IMOS performance: From thesingle device to the circuit,” IEEE Trans. Electron Devices, vol. 53, no. 8,pp. 1852–1857, Aug. 2006.