About FlexSDR and My Projects

Shyu Lee (Xu LI)FlexSDR project organizer

Agenda

• Purpose of the project

• Technical details

• Current status

• Wish list

• About Shyu

Very Basic Background

• I used to be an amateur radio fan;

• Was working on EME (Moon bouncing)communication during university time. Never succeed, but the failure just stimulate me keep going;

• Made a lot of test boards including embedded system, FPGA (DSP), AD/DA as well as the RF frontend;

Background (continued)

• Worked as an RF Design Engineer in RFMD for four years, but never stop the researches SDR techniques during the time;

• My time of working with SDR is scatter by regular work in company;

• Now I give up the promotion and counter offer, quit my job and put full time on my favorite topic and style of research life;

Purpose

• Finish the SDR hardware test platform, make eligible for most SDR application verification missions;

• Create a set of basic software building blocks, to let people quick get their work hand on;

• Make the project open source under GPL;

• Help to let the open project contributors connected as a community.

A too brief introduction of current status for the gears

SDA-20F SDR Frontend

1. Part Numbered as SDA-20F;

2. Baseline level Stratix II FPGA based DSP;

3. Using Quartus II web edition as the developing IDE;

4. AD9957 as the TX DAC;

5. AD6655 as the dual-RX ADC (purpose of diversity receiving)

6. RX signal lever + ADC Driver + Anti-aliasing filer attached;

7. 128MiB 133MHz SDRAM;

8. DXB expansion slot;

9. All hardware design by Shyu on the expense of his own salary during his spare time in 2009;

10. All finished by Shyu’s hand soldering and assembly;

TCV-100 SDR Frontend

1. Part Numbered as TCV-100;

2. EP2C50 Cyclone II FPGA based DSP;

3. Using Quartus II web edition as the developing IDE;

4. AD9957 as the TX DAC;

5. AD6655 as the dual-RX ADC (purpose of diversity receiving)

6. 8MiB 133MHz SDRAM;

7. All hardware design by Shyu on the expense of his own salary during his spare time in 2007;

8. All finished by Shyu’s hand soldering and assembly;

FCS-300 Synthesizer Complex

1. Part Numbered as FCS-300;

2. 5MHz~40MHz reference;

3. Bypass-able on board 10MHz TCXO reference;

4. 320MHz ultra low phase-noise VCXO locked by reference with AD9518;

5. DDS based ADC/DAC Encoding;

6. AD9912 DDS output;

7. All hardware design by Shyu on the expense of his own salary during his spare time in 2009;

8. All finished by Shyu’s hand soldering and assembly;

ENC-310 Synthesizer Complex

1. Part Numbered as ENC-310;

2. Superseded by FCS-300;

3. All hardware design by Shyu on the expense of his own salary during his spare time in 2008;

4. All finished by Shyu’s hand soldering and assembly;

FCS-200 Synthesizer Complex

1. Part Numbered as FCS-200;

2. My first dream of making an ultra-low phase noise, low spur level signal source comparable to Agilent’s $20000.00 items;

3. Superseded by FCS-300;

4. All hardware design by Shyu on the expense of his own salary during his spare time in 2007;

5. All finished by Shyu’s hand soldering and assembly;

RF Frontend test bed

1. Developed during my time in college from 2005~2006;

ARM embedded controlling system

1. Part Numbered as ESX-85;

2. Samsung S3C6410X ARM11 CPU + EP3C40 SDR optimized IO Bridge;

3. Full set of modern I/O purpose, including: Ethernet, USB Device/Host, RS-232(all 8 lines), Optical SPDIF and conventional AC97 audio;

4. Work as DXB expansion host;

5. Using industry standard JTAG port to connect with debugging tools;

6. LCD supported with OpenVG;

7. Ported to Linux 2.6.3x;

8. All hardware design by Shyu on the expense of his own salary during his spare time in 2011;

9. All finished by Shyu’s hand soldering and assembly;

ARM embedded card

1. Part Numbered as SEM-641;

2. The S3C6410 SEM module shown on ESX-85 board;

3. All hardware design by Shyu on the expense of his own salary during his spare time in 2011;

4. All finished by Shyu’s hand soldering and assembly;

5. “Designed by Shyu” noted on metal layer;

ARM embedded card

1. Part Numbered as SEM-T36;

2. STM32 Cortex-M3 CPU

3. 88W8686 Wi-Fi module;

4. Wi-Fi stack code finished by another community member;

5. SEM module, supported by ESX-85;

6. All hardware design by Shyu on the expense of his own salary during his spare time in 2011;

7. All finished by Shyu’s hand soldering and assembly;

Early versions of embedded cards

1. My works during my university time before 2006;

2. Based on S3C2440 ARM9;

3. Does not compatible with SEM standard, but these parts are my early thoughts of how an embedded module should be like;

Block diagrams

The slides are prepared just within an hour, Please give me some extra time for the block diagrams.

Patents

• SEM Embedded Connection – a standard of the interconnection between embedded controllers and SDR hardware, including the mechanical specifications and signal and timing specifications;

• DXB Expansion - a standard of the interconnection between the replaceable AD/DA frontend and SDR motherboard, including the mechanical specifications and signal and timing specifications;

Wish List

• I can hear other people’s voice, like suggestions, contributions and criticisms, on the FlexSDR project.

• I can have all aspects of the documents of the project organized and finished.

• I can use my gadgets to fulfill my wish of making a successive EME communication. That will be really really cool!

• I can effectively help other people with my knowledge;

• I can put full of my strength on a field I am so interested in, that I have spent at least 6 years time on.

Wish List

• A business model could be found by opening the knowledge and selling service for customized commercial demands;

• I wish I can help with the “Inter-Planet” and “Outer space” wireless communications at lower cost and higher performance level.

About Me

• My name is Shyu Lee (Shyu is pronounced like |sh oō|. Pinyin: LI XU, but never mind.)

• Worked for RFMD from 2008 to 2011 as RF Engineer, RF Design Engineer, Staff Design Engineer and perhaps I can be Engineering Manager if I don’t quit. My job was design RF frontend IC and MCM modules for base-stations. There are harsh demand of performance specifications like IP3, noise figure, gain, isolation and many others for the the products I was concern with. I also have one year design experience of VCO and PLL in Sirenza (With the members of Vari-L team), frequency covering from 1GHz ~ 7GHz with coil tanked and micro-strip tanked structures;

• I quit the my company job and plan to start FlexSDR;• I have to eat something in order to live everyday, so I help my

friends started one company called Meteroi, a company design and manufacturing multi-meters with varies of innovative ideas;

Thanks for your time

• I really appreciate you can finish checking out my slides.

• Maybe you have some questions, please feel free contact me with me@shyul.com or call me at +86-1860-1678-068.

For Graduate Program Application

• Having Bachelor degree of Electronics Engineering and Master degree of Computer Application;

• GRE: 520/800/3 (Gosh! something must be wrong and crazy for 3)

• TOFEL: 20/26/23/24