Abdullah Aldahami(11074595)

Feb26, 2010 1

1. Introduction

2. Feedback Switch Logic

3. Arithmetic Logic Unit Architecture

a. Ripple-Carry Adder

b. Kogge-Stone Adder

c. Han-Carlson Adder

4. Results

a. Arithmetic Operation

b. Logical Operation

5. Conclusion

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This paper presents the design of 32-bit Arithmetic Logic Unit (ALU) which performs addition, subtraction, logic operations and shifting operation using Feedback Switch Logic (FSL) and static CMOS logics at 90nm CMOS process.

This ALU combines adder, shifter and logical units which are having low power consumption, less delay and uses lesser area.

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Recently a new dynamic like static circuit family called Feedback-Switch Logic (FSL) has been proposed.

FSL is suitable for high speed and low power applications because it offers fast switching, reduced capacitance and input-switching dependent activity factor without the need of clock connection.

The major advantages of FSL are fast switching and reduced capacitance.

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FSL is a differential circuit family that provides the output and its complement from a single side of the gate.

There are two possible ways of FSL structures:

(a) (b)

The FSL structure shown in (a) is the one that is considered. The structure in (b) can be useful for FSL tree implementations since it allows transistor sharing between complementary networks.

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Since FSL is a combination of static and dynamic logic, the power consumption of logic gates using FSL is very much close to the power consumption of static CMOS gates. And also FSL having less delay compared to static CMOS logic because FSL offers reduced capacitance and fast switching.

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Design of low power and high speed microprocessors requires reduction in power consumption to improve performance of all components of microprocessors.

Arithmetic and Logic Unit (ALU) is one of most power consuming components in microprocessor that performs an arithmetic (addition, subtraction, etc.) and logic operations (Exclusive OR, AND, etc.) between two numbers.

Adders are basic components of any arithmetic circuit and are frequently on the critical path.

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There are several levels of hierarchy which can improve addition operations.

A Ripple carry adder is the first and the most fundamental adder.

Using a faster carry propagation method such as prefix tree adder schemes (Kogge-Stone & Han-Carlson adder), delay can be reduced.

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a. Ripple carry adder: Is a simple adder that is known as a slow adder since each

full adder must wait for the carry bit to be calculated from the previous full adder (Calculates one carry for each bit at a time).

Si = Ai ⊕ Bi ⊕ ci Ci+1 = Bi.ci +Ai.Bi + Ai.ci

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b. Kogge-Stone Adder:

The Kogge-Stone adder is a parallel prefix form of carry look-ahead adder.

It is widely considered the fastest adder design possible. It is the common design for high-performance adders in industry

It takes more area (large area) to implement but it has a lower fan-out at each stage, which increases performance.

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An example of a 4-bit Kogge-Stone adder is shown to the right. Each vertical stage produces a "propagate" and a "generate" bit, as shown. The culminating generate bits (the carries) are produced in the last stage (vertically), and these bits are XOR with the initial propagate after the input (the red boxes) to produce the sum bits. E.g., the first (least-significant) sum bit is calculated by XOR the propagate in the farthest-right red box (a "1") with the carry-in (a "0"), producing a "1". The second bit is calculated by XOR the propagate in second box from the right (a "0") with C0 (a "0"), producing a "0".

“http://en.wikipedia.org/wiki/Kogge-Stone_adder”

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c. Han-Carlson adder:

Han-Carlson adder combines the Brent-Kung adder (with a small area and big delay time) and Kogge-Stone adder (with a large area and small delay time) merge trees to achieve a balance both with respect to speed and area.

Han-Carlson adder has the same principle of Kogge-Stone Adder with structure that has minimum logic depth, resulting in a fast adder (but slower than Kogge-Stone) with a medium size area.

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The design of the ALU can be divided into four parts as control unit, arithmetic unit, logical unit, and shifter unit.

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The 2x4 decoder is used as control unit to select the different units for desired operation using control signals S3 and S2.

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The arithmetic unit consists of adder unit and 4x1 multiplexer unit.

Adder unit is used for addition of two operands while multiplexer unit is responsible for selecting appropriate input operand for adder unit according to the control signal S2 and S1.

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Different logical and shifting operations are selected by another 2x4 decoder having S1 and S0 control signals.

Shifting values for shifter unit are adjusted by Sh5, Sh4, Sh3, Sh2 and Sh1.

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All the outputs of different units of ALU are combined with output OR array in which 3 input OR gates are followed by buffer to provide output as ‘Y’.

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a. Arithmetic Operation From the results, we can conclude that Kogge-Stone adder

architecture gives high performance in terms of speed in both CMOS and FSL Logics. In terms of power, ripple carry adder consumes least among other architecture.

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b. Logical Operation From the results, we can conclude that in FSL Logic, about 14

% delay reduction is obtained as compared to delay in CMOS logic; but about 6% increase in power consumption is found in FSL.

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This paper has implemented 32-bit ALU using Feedback Switch Logic (FSL). FSL combines the high performance with the activity-dependent low power consumption of static circuits.

FSL has the advantages of reduced capacitance and fast switching speed.

Simulation results show that ALU designed using FSL achieves 14% reduction in delay compared to static CMOS logic and its power consumption is comparable to that of ALU with static CMOS logic.

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