ABC130 testing

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ABC130 testing Bruce Gallop and Peter Phillips 15 Jan 2014

description

ABC130 testing. Bruce Gallop and Peter Phillips 15 Jan 2014. FIB. Enable on transmit is inverted Fixed Data and XOFF direction Now works with Direction = 1 Received packets tested Register read L1 data Trivial R3 (empty data). FIB repair by NanoScope (Bristol ). - PowerPoint PPT Presentation

Transcript of ABC130 testing

Page 1: ABC130 testing

ABC130 testing

Bruce Gallop and Peter Phillips15 Jan 2014

Page 2: ABC130 testing

FIB

• Enable on transmit is inverted• Fixed Data and XOFF direction• Now works with– Direction = 1

• Received packets tested– Register read– L1 data– Trivial R3 (empty data)

Page 3: ABC130 testing

FIB repair to XOFFR(short enable to VDD)

FIB repair to DATAR(short enable to GND)

CHIP FIB2

FIB repair by NanoScope (Bristol)

Page 4: ABC130 testing

XOFF fix seen close up:M3 accessed, not yet modified

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XOFF fix seen close up:Enable line cut, shorted to VDDD

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DC measurementof DATA and XOFF

Dir=0, Drive=4 Dir=0, Drive=7 Dir=1, Drive=4 Dir=1, Drive=7

XOFFR_N 0.620 0.619 0.619 0.618

XOFFR_P 0.620 0.619 0.619 0.618

DATAR_N 0.767 0.890 0.768 0.890

DATAR_P 0.405 0.317 0.405 0.317

DATAL_P 0.617 0.615 0.415 0.323

DATAL_N 0.617 0.615 0.773 0.887

XOFFL_P 0.357 0.315 0.617 0.615

XOFFL_N 0.754 0.879 0.617 0.615

V V V V

Þ For this chip, DATAR is permanently enabled as a driver (as expected).Following pages refer to output from DATAR when dir=1 (for dir=0 it does not work)

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Example (decoded) packets• ST [44] abc130_ReadRegs()• Configuring stream 14• Variable 10022 unknown to ABC130 configure• op: d008 seq: 33 len: 739• Stream: 8• Format: 100• DatSrc: 0• [No. : chip type L0:BC StpBt : StripData (as per type) ]• 000 : 20 8:Reg 00:00 0 : 00000000• 007 : 20 8:Reg 01:00 0 : 00000000• 019 : 20 8:Reg 02:00 0 : 1f000000• 031 : 20 8:Reg 03:00 0 : 00000000• 043 : 20 8:Reg 07:00 0 : 00000000• 061 : 20 8:Reg 10:00 0 : 00000000• 073 : 20 8:Reg 11:00 0 : 00000000• 085 : 20 8:Reg 12:00 0 : 00000000• 097 : 20 8:Reg 13:00 0 : 00000000• 109 : 20 8:Reg 14:00 0 : 00000000• 121 : 20 8:Reg 15:00 0 : 00000477• 133 : 20 8:Reg 16:00 0 : 00000000• 145 : 20 8:Reg 17:00 0 : 00000000• 157 : 20 8:Reg 18:00 0 : e042b039• 169 : 20 8:Reg 19:00 0 : 8a502842• 181 : 20 8:Reg 1a:00 0 : c0969d22

• op: d008 seq: 34 len: 739• Stream: 8• Format: 100• DatSrc: 0• [No. : chip type L0:BC StpBt : StripData (as per type) ]• 000 : 20 8:Reg 1b:00 0 : 9822010f• 012 : 20 8:Reg 1c:00 0 : db8ab15b• 024 : 20 8:Reg 1d:00 0 : c3212180• 036 : 20 8:Reg 1e:00 0 : c08c4843• 048 : 20 8:Reg 1f:00 0 : c4310180• 060 : 20 8:Reg 20:00 0 : 00001f10• 072 : 20 8:Reg 21:00 0 : 00000777• 084 : 20 8:Reg 22:00 0 : 0000000f• 096 : 20 8:Reg 23:00 0 : 00000000• 108 : 20 8:Reg 30:00 0 : 00000000• 120 : 20 8:Reg 31:00 0 : 00000000• 132 : 20 8:Reg 32:00 0 : 0000001b• 144 : 20 8:Reg 3f:00 0 : 00000000

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Tune configuration (Use MUX to tune to nominal values)

• Delay DelStep VThr VCal CalPol– 0 3 72 34 0

• BVREF BIREF B8REF COMBIAS– 11 10 10 9

• BIFEED BIPRE LDOD LDOA– 8 17 0 0

• Power at 1.3V, LDO set for minimum drop– Gives 1.24 on VDDD, VDDA

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How a scan works

• Series of triggers with different configurations• Setup configuration– Each trigger• Send L0• Send L1 (with appropriate L0ID)

– Driven by software, no optimisation• About 1ms between L0 and L1• 10s ms between triggers

– Loop over cal-line (ie 0001, 0010, 0100, 1000)

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Single Channel mask scanshowing mask bit ordering in 2 banks of 128

Mas

k bi

t

Channel decoded from packet

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Trig Delay Scanadjusting timing of L0 with respect to CAL

Polarity 0

Polarity 1

112

120

=> Spacing consistent with cal pulse 8 wide. Reading 3BC, no 01 detect.

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First look at Gain – polarity 0

1.2fC

2.4fC

30

65

35 counts -> 80.5mV -> 67 mV/fC (design value 90 mV/fC)

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3-point gain polarity =0 (preliminary)

• preamp feed gain (DAC counts) mv/fC noise• 17 8 27.4 63.0 347• 15 8 27.7 63.7 443• 19 8 28.1 64.6 349• 10 8 27.6 63.5 437• 17 10 27.4 63.0 642• 17 6 29.1 66.9 432• 0 8 28.8 66.2 450• 31 8 28.2 64.9 443• 17 0 34.7 79.8 379• 17 13 25.6 58.9 470• 17 31 19.2 44.2 584

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3-point gain plots

Gain (DAC counts per fC)

0 32 64 96 128 160 192 224 25605

10152025303540

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Summary

• Lots more to test• More thorough R3 testing• Trims• Tuning LDO• Another chip may be helpful

- Is gain of FIB2 typical or not?

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Backup: MUX measurementsMUX0 TEST_TRDAC

0 428 7310 10318 1341f 160c 88e 96 -> leave here

MUX1 TEST_VR0 338 4710 6118 741f 86b 52 -> leave here

MUX2 TEST_IR0 338 4710 6118 741f 860a 50 -> leave here

VR=1F VR=10 VR=08 VR=0a VR=0c VR=0bMUX6 VCS 978 933 851 881 903 893MUX7 VCD 404 548 633 611 590 601MUX8 VCSP 398 542 627 605 584 595MUX9 VBASE 773 571 444 476 508 492MUX10 VB 715 516 402 430 459 445

MUX3 TEST_R8B0 338 4710 6118 741f 860a 50 -> leave here

MUX4 TEST_IPRE0 878 10310 12018 1351f 14911 122 -> leave here

MUX5 TEST_IFEED0 188 30 -> leave here10 4318 551f 659 36 -> leave here

MUX11 - bandgap 620mV (nominal 592).

MUX12 CALLINE00 620 2140 3660 5280 68a0 84c0 100e0 116ff 132

MUX13 TEST_THDAC00 520 2140 3660 5280 68a0 83c0 99e0 114ff 129

TESTCOM0 258 3510 4418 541f 63