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Design and Implementation of SAR ADC

Weibin WuCollege of Engineering, South China Agricultural University Guangzhou, China

[email protected]

Tiansheng Hong†, Joseph Mwape Chileshe, Jieyu LU, Benquan MO, Chaohong LAI

College of Engineering, South China Agricultural University Guangzhou, China

[email protected]

Abstract—The successive approximation register analog to

digital converter (SAR ADC) technique is not yet mature in

China mainly because of the imperfect analog module of the

SAR ADC. The purpose of this design was to optimize theanalog module by designing and making a 8-bit 1MHz SAR

ADC and testing a 12-bit SAR ADC theoretically and by

simulation. The design of the 1MHz SAR DAC, which

consists of analog circuit and digital circuit, was designed

according to the positive design method and the specific

standard. And the ADC circuit was designed according to

the sub-module layout. By the time the project design was

finished, its hardware which was made of discrete

components by welding printed circuit board (PCB) was

debugged. The hardware’s physical properties were

analyzed by using a SAR DAC test platform created in

LabVIEW8.6 interfaced with data acquisition cards. This

designed SAR ADC can be applied to sensor interface, data

acquisition system, portable test instrument, low powercontrol system and some aspects of communication. Its

absolute average error is about 1% in the laboratory tests

which meet the expectations of high accuracy requirement.

When it was used in the ropeway project of agriculture

engineering project, it reached a good accuracy of 91.5%. It

is recommended that PCB automatic routing function be

used to reduce the error and interference in the further

study from the tests result.

Index Terms—ADC, successive approximation register, Multisim,

LabVIEW

I. I NTRODUCTION

This paper is aimed at describing the design of adiscrete-component, successive approximation registeranalog to digital converter (SAR ADC). Its resolution is12-bit, 5V single-phase power supply. Its maximum power consumption is 93.456mW with 0~5V analoginput ranges, which can be broadened from 0V to 10V.Its conversion time is 13.01us, and the output levelconformed to the level of transistor transistor logic (TTL).This ADC can be used in the interface of sensors, dataacquisition system, portable test instruments, low powercontrol system and communication [1].

SAR ADC has many advantages, such as low power

consumption, high resolution, high accuracy, no delays

associated with the output data and it is compact. Themain limitation of the successive approximation structure

is the low sampling rate and its demand for the same

accuracy between the whole system and each constituent

unit, such as DAC and the comparator. Because of these

characteristics, they are applied to the moderate or high

resolution ADC whose resolution requirement is between

8-bit to 16-bit and its sampling rate is below 5Msps [2].

Consequently, SAR ADCs are widely used in portable

battery-powered meters, pen quantizers, industrial control

and data and signal acquisition devices.ADC converter has been developed to a very high level

in the world. For instance, its highest resolution factormay reach 16 bit, and the power consumption is very low.However, due to the analog modules, such as thecomparator and the voltage reference module, it has not been optimized. In addition the development of ADC inChina is still in its infancy. The purpose of this design is

to find out an optimization design of the ADC analogmodule and perfect it in the future [3].

II. DESIGN OF THE SAR ADC

A. Structure Schematic

The 12-bit SAR ADC consisted of control logic circuit,timing generator, shift register, DAC and voltage

comparator. The filtered analog input goes through thesample and hold circuit in the sample hold device module.

The numerical approximation was obtained after beingquantized and coded. The SAR process includes several

comparisons made between analog input signal and thereference voltage, and until the converted valuenumerically approaches the corresponding analog inputs.

B. The whole ADC Circuit

The ADC layout design is shown in Fig 1. The wholelayout design consists of 8 modules, the clock circuit,ADC module, DAC module, sample holder module,reference voltage selector, input filtering device,comparison circuitry and the latch module. The clockcircuit provides 1 MHz clock signal and 76.923 kHz

† Corresponding author:

Tiansheng Hong, South China Agricultural University, Guangzhou

(E-mail: [email protected])

JOURNAL OF COMPUTERS, VOL. 6, NO. 12, DECEMBER 2011 2631

© 2011 ACADEMY PUBLISHER doi:10.4304/jcp.6.12.2631-2638

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initiating signal for the whole circuit, and controls signalfor the shift register, SAR and the sample holder module.

The ADC module generates shift signal to control theD-flip-flop’s working sequence, and temporarily storesand updates the 12-bit converted digital output. Two

DAC modules generate the approximated wave and thelatch output wave, which was made a comparison withthe analog input wave. Signals of the analog inputmodule could be sine wave input, DC input, or a hybridwaveform of sine wave input DC input.

Figure 1. Diagram of 12-bit ADC integrated circuit

The sin-wave frequency could range from tens to tens

of thousands hertz. Filtering device filters ambient noise.

However it must be noted that the filtering circuit may

introduce two-period delay, which could affect the output

waveform; but it is negligible. The 8 channels sample

hold device Module provides 8 channels analog input.

Besides the sample and hold function, it has voltage drift

function but only the voltage is positive. The referencevoltage selector provides 5V and 10V optional reference

voltage that can increases the accuracy. The latch module

records the 12-bit converted numerical output in real time,

and provides data for the DAC2 to convert, so as to

acquire a wave approximation. The comparison circuitry

makes a comparison between the analog input signal after

being sampled and held and the converted signal after

being converted by ADC and DAC. The result returns to

the ADC module and renews the converted output. To

ensure accuracy, the LF400 is chosen as the comparator

device.

C. The DAC Module

The DAC module is an important part. Speed of thewhole ADC depends on the converting speed and

accuracy of DAC module. There are several types ofDAC such as weighted resistance DAC, R-2R ladderresistor DAC which is only using R and 2 R resistances,and R-2R inverse-ladder resistance DAC. The last typewas chosen in this paper, as shown in Fig 2.

2 R

V REF

2 R 2 R2 R 2 R

R R R

A 0

S0 S1 S2S3

0d

2d 3

d 1

d

(LCB) (MSB)

I

RF

Summing

Junction

16

I

8

I

4

I

2

I

8

I

4

I

2

I

R

R2 R2 R2 R2 R

Figure 2. Function diagram of R-2R Inverse-Ladder Resistance DAC

Using R-2R inverse-ladder resistance DAC cansimplify the design which can handle different conditionssuch as reference power supply with high voltage anddifferent switching speed of analog switch. The two

through connection points of the analog switch weregrounding point and input current summing junction andthe electric potential of the summing junction was

Ⅰ Ⅱ Ⅲ

Display1

Display2

Ⅴ

ⅥⅦ

Ⅷ

Ⅸ

Ⅹ

.Latch and display circuitⅠ .Shift register display circuitⅡ .Waveform display circuitsⅢ .DAC1Ⅳ Ⅴ.DAC2

.Reference voltage selection moduleⅥ Ⅶ.Sample hold device .Comparator Ⅷ .Fliter Ⅸ .ADCⅩ

2632 JOURNAL OF COMPUTERS, VOL. 6, NO. 12, DECEMBER 2011

© 2011 ACADEMY PUBLISHER

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approximate with grounding point, so only between twoapproximate electric potentials could the switch shift.Though the arithmetic amplifier’s input current changesalong with the input data, for the whole resistance group,current is provided by the reference power resource

which is stable, so is that of each branch. That meanscurrents of branches ere synchronize and increased theconverting speed [4].

III. A NALYTICAL SIMULATION AND ELEMENTAL

IMPLEMENTATION OF SAR ADC

A. DC Simulation Waveform

Multisim 10.0 from National Instruments Company(NI) was chosen as the simulation software. Setting theDAC reference voltage 5V and input DC voltage 1V, thesimulation waveform showed that, at the 13.02μs, thedigital converted value D11~D0 was 001101000000. Thisvalue corresponds to analog voltage 1.015625V.Compared to the actual input DC voltage 1V, thecomparative error was just 1.56%. The converted outputof the latch made the approximate waveform. The valuedisplays as 1.040V and the approximate one was 1.040V.

Error value was zero. 12-bit numerical value displays as110010111111, and its negation was 001101000000.

Successive approximate ADC’s converting time relatedto its clock-pulse frequency and its bit. The smaller the bit and the higher the frequency, the shorter theconverting time [5].

B. Sine Simulation Waveform

The simulation result showed that, the latch’s outputwaveform was a step-shape, each step being 13.01μs. Its

waveform envelope was similar to the sine, andresembles the sine-wave of the input analog signal. Therewas only 13.01μs delay between them. The output data ofthe Latch, converted by DAC, approximated the shape ofladder, which reflects the approximation process and time

consumption.

C. Power Analysis

The formula P=U×I was used to calculate thesimulation power. Joining all the grounding points of thissimulation circuit together and testing them using themultimeter, the maximum stable current value was 18.9

mA. According to the formula, the result of the power is93.465 W. This ADC circuit used two DAC modules and

a few external circuits. The power consumption of theADC module itself was even lower [6-7].

D. Physical Circuit on PCB

When the design was completed, this ADC wasimplemented physically with elements on PCB, as shownin Fig 3.

IV. ADC FUNCTION TESTING PLATFORM AND DATA

A NALYSIS

A. ADC Testing Platform

Based on the NI data acquisition cards such asPCI6259, USB6221, PCI6022, and so on, a platform forADC function testing was built. The platform is as shownin Fig.4.

Input part

Output part

Switch selections

of 5V, 2.5V, Diret current

Power source

Voltage refference

of +5V or +10V

Interfaces of

LF400 OUT, DC IN, AI, GND

Figure3. Physical circuit diagram of the 8-bit SAR DAC circuit



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Figure 4. Hardware test platform of ADC

The clock signal was generated and collected byPCI6022 and displayed on template. The data acquisitioncard separately collected analog input, including directand indirect current signal, clock signal, initiating signal,sampled and held waveform and the latch outputwaveform after DAC converted. Then the 8bit digitallatch output, power spectrum, power spectrum density,

converted signal, analog input voltage, approximatedvoltage and comparative error were displayed. All ofthese data could be chosen in real time to record, forfurther analysis.

V. TEST R ESULT A NALYSIS

The test result analysis of the circuit with DC voltage

input signal was shown as in Table Ⅰ.

The test result analysis of the circuit with differentfrequency, such as 500Hz, 1000Hz and 2000Hz,

sinusoidal input was shown as in Table Ⅱ.

From Table.1, the maximum comparative error is

0.697464% and the absolute average error is about

0.198339%. From Table Ⅱ, the maximum comparative

error is 4.4412% and the absolute average error is about

1.0684%. Different input signals have different maximum

comparative error, but the absolute average error is about1%. The expectation was that the maximum comparative

should not be more than 5% and the absolute average

error should be around 1%. So the test results were within

the expected range.

TABLE Ⅰ TEST R ESULT A NALYSIS WITH DC A NALOG I NPUT

Latch voltage(V) DC analog input voltage(V) Comparative error

5.001313 5.000001 0.026263%

5.003746 5.000000 0.074922%

4.99003 4.980392 0.193515%

4.992394 5.000000 0.152120%

4.690146 4.686275 0.082617%

4.696889 4.705882 0.191106%

4.695424 4.686275 0.195246%

3.497503 3.490196 0.209350%

3.504077 3.509804 0.163165%

2.000679 2.000000 0.033959%

1.997902 2.000001 0.104914%

0.990021 1.980392 0.486218%

0.493615 0.490196 0.697464%

0.508958 0.509804 0.165888%

TABLE Ⅱ TEST R ESULT A NALYSIS OF SINUSOIDAL I NPUT

Actual sine wave voltage(V) Tested voltage(V) Comparative error

0.488317 0.510004 4.4412%

0.744709 0.745800 0.1465%

1.001091 1.010004 0.8903%

1.441187 1.400850 -2.7989%

1.637066 1.633304 -0.2298%

Power source

Physical Circuit

on PCB

Waveform

generator

Part of NI

data

acquisition

Screen



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1.925201 2.000125 3.8918%

2.021271 2.051021 1.4718%

2.499701 2.586293 3.4641%

2.667217 2.666667 -0.0206%

2.733009 2.725491 -0.2751%

2.926899 2.921569 -0.1821%

3.028088 3.019608 -0.2800%

3.356137 3.352941 -0.0952%

3.383683 3.392157 0.2504%

4.098719 4.098039 -0.0166%

4.141406 4.137255 -0.1002%

4.380690 4.372549 -0.1858%

5.023431 4.998774 -0.4908%

VI. ADC APPLICATION IN I NDUSTRY AND

AGRICULTURE PROJECT

A. ADC and Axle Fatigue Test

The digital signal was converted into analog value and

provided the input signal for the hydraulic cylinder in

axle fatigue test. This input signal drove the hydrovalve’

movement, and imitated a test that was about the fatigue

damage of axle movement. On the other hand, the

collected analog value was converted into digital quantity

to so as to process the signal and analyze the data basedon LabVIEW interface [8]. The interface is shown in

Fig5.

Figure 5. Experimental Platform for Axle Detection

When carrying out the hydrostatic test, experiment

completing, one important step was preloading, aiming at

eliminating external interference. Only after three

repetitions of the preloading could the sine wave be

loaded. In the course of the experiment, the preload

signals were channeled through PCI-6259 dataacquisition card and generated a simulation by

Multisim10.0. Since the preload procedure frequency was

low that was usually from 2Hz to 3Hz, the process of the

approximation lasted long. The collected data is as shown

in Table Ⅲ. After this, the data was analyzed t to

determine its operating force and deviation.

Data in Table Ⅲ showed that, the maximum

comparative error is 3.3461%, and the absolute average

error is about 1.0294%. In this test, the SAR ADC also

met the expectation either the maximum comparative

error or the absolute average error. In addition, the

sampled and held voltage values and the approximated

ones were able to meet the 8bit converting requirement.

Accurate positioning of the hydraulic valve is another

essential step in axle test. However, this DPZO-L-270-L5

40 type ATOS hydraulic valve does not have such

functions. So a slow ADC approximate procedure helps

achieving the accurate positioning function. During the

test, corresponding to the assumed location offset 186mm,

the converted voltage is 4.23V, the actual approximated

voltage value is 4.120V and the comparative error is

0.945%. The accurate positioning requirement is met.

Around all these axle tests, the designed SAR ADC

met the expectations at all. The low absolute average

error is the one of the major characters for designing this

SAR ADC, and the absolute average error from the testswas about 1% which met the expectation. In other words,

it has reached the required accuracy.

B. Application in Agriculture Engineering Projects.

The transportation of citrus orchards and agricultural

fertilizers in South China rely on human labor. But this

kind of transport is inefficient especially in the period of

citrus harvest. Due to its strong transportation capacity

and good terrain adaptability, the ropeway has a very

good application prospect in the southern citrus orchards

[9], which is a project, the technological study and

demonstration of circular chain ropeway in mountainouscitrus orchards, belonging the Special Fund for Agro-

scientific Research in the Public Interest of the Chinese



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Ministry of Agriculture. In this project the strength of

steel wire is important in the safe use steel rope in the

ropeways being developed for the citrus orchards in south

China. The SAR ADC was applied to this ropeway

project, especially in the sensor of a non-destructivetesting device of steel wire which can help in predicting

failure in steel wire [10]. Using the designed SAR ADC,

91.5% of the likely points of failure could be determined.

It reach a good accuracy and even higher than expected

about the project.

It has been also applied to another project in detection

of leaf area index (LAI) based on spectrum, which is a

project belonging to National Natural Science Foundation

of China. It was used in a data acquisition platform and

some parts of the Analysis System for Citrus LAISpectrum Data. The fitting equation of LAI and spectral

information obtained is Y=1.5106X+0.7869 and the

calculation error is 0.0378%. Its accuracy is high enough

to reach the requirement of the project.

TABLE Ⅲ DATA A NALYSIS IN PRELOADING PROCEDURE

Reference voltage(V Tested Approximated voltage(V) Comparative error

4.989 4.912 1.5434%

4.832 4.775 1.1796%

4.624 4.601 0.4974%

4.591 4.581 0.2178%

4.465 4.444 0.4703%

4.371 4.289 1.8760%

4.179 4.133 1.1007%

4.093 4.090 0.0732%

4.120 4.112 0.1941%

4.121 4.112 0.2184%

4.009 3.956 1.3220%

3.896 3.820 1.9507%

3.862 3.820 1.0875%

3.828 3.806 0.5747%

3.678 3.644 0.9244%

3.500 3.499 0.0285%

3.435 3.352 2.4163%

3.414 3.352 1.8161%

3.314 3.313 0.0302%

3.203 3.196 0.2185%

3.043 3.020 0.7558%

2.825 2.902 -2.7257%

2.765 2.746 0.6871%

2.571 2.570 0.0390%

2.137 2.103 1.5910%

2.064 2.051 0.6298%

1.964 1.941 1.1711%

1.752 1.749 0.1712%

1.490 1.479 0.7382%

1.302 1.287 1.1521%

1.281 1.277 0.3122%



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1.046 1.011 3.3461%

1.011 0.997 1.3848%

0.504 0.503 0.1988%

0.359 0.347 3.3426%

VII. CONCLUSIONS

This paper described the 8-bit SAR ADC’s designing

process and the tests of the 12-bit SAR ADC in detail. As

the simulation waveform and the physical circuit testing

result showed, conclusion could be carried out. Firstly,

this SAR ADC achieved analog-digital converting.

Secondly, its resolution could reach 8-bit and 12-bit ADC

requirement. Thirdly, when powered by 5V single-phase

resource, its maximum power consumption was93.451mW and the average current was 1.37mA. Its

absolute average error is near 1% in the tests in

laboratory which could meet the expectation at all and

reach the accuracy requirement. When it was used in the

ropeway project of agriculture engineering project, it

reached a good accuracy of 91.5%. And its accuracy is

high enough to reach the requirement of the project in

detection of LAI based on spectrum.

However, some improvement could be made. It is

better to use bandgap-reference as the reference voltage

VREF in the circuit structure.In order to have a better

connection with ELVIS, manual welding on breadboardwas adopted. It is also recommended in the further study,

that the PCB auto routing function be improved for

reducing the unnecessary error and interference.

ACKNOWLEDGMENT

This work was supported by the National Natural

Science Foundation of China with the Serial Number of

30871450.And it was also supported by the project with

the number of 200903023-01, the technological study and

demonstration of circular chain ropeway in mountainous

citrus orchards, which belongs to the Special Fund for

Agro-scientific Research in the Public Interest of the

Chinese Ministry of Agriculture with the serial number of

200903023.

R EFERENCES

[1] J. Zhang, “Design a 10-bit SAR A/D Converter Based on

CMOS Technology,” University of Electronic Science

and Technology of Xi’an, 2008.

[2] L. Zhang, “The Design of 10 Bit SAR ADC, Shenyang

University of Technology,” 2006 .

[3] X.L. Yang, “Research and Design of 10-bit SAR ADC

Based on CMOS Technology,” HeFei University of

Technology, 2007.

[4] C.Y. Chang, N. Zhao, Z.J. Liu, “A Study and Simulation

of D/A Converter Based on Electronics Workbench

EWB,” Modern Electronic Technique 2004, (9): 87-88.

[5] W.T. Zhou, “A 10bit 580ksps Successive Approximation

Register ADC in 0.18um CMOS,” Shanghai Jiao Tong

University, 2007.

[6] E.J. Sun, “Fundamental research of DAC and design of 8-

bit DAC,” University of Electronic Science and

Technology of China, 2003.

[7] T.P. Huang, “Design of a high accuracy and low power

consumption 8-bit DAC,” University of Electronic

Science and Technology of China, 2005.

[8] Z.S. Lei, L. Wei, and C.G. Zhao,et al, High-level

programming with LabVIEW and application of virtual

instruments in Engineering, China Railway Publishing

House, 2009.

[9] Z.Q. Lun, “Design of Ropeway and Steel Wire Detection

Device”, South China Agricultural University, 2009 .

[10] R. Quan, S.H. Quan, L. Huang, C.J. Xie, “Fault Diagnosis

and Fault-Tolerant Control for Multi-Sensor of Fuel Cell

System,” Journal of Computational Information Systems.

2010, 6 (11) : 3703- 3711.

Weibin Wu, Male, born in 1978,

Guangzhou, is an associate professorin College of Engineering, SouthChina Agricultural University. He

obtained bachelor degree of machinedesign & manufacturing andautomation, South China

Agricultural University, July 2001;Master's degrees of mechanizationengineering, South China

Agricultural University, June 2004;

and Ph.D in mechanizationengineering, South ChinaAgricultural University, June 2007.

Afterwards, he became a Post Doctor researcher in College of

Mechanical and Automotive Engineering of South ChinaUniversity of Technology, majoring in mechanization andfocusing on electronics, information and computer applications.

He is now engaged in the teaching and research of soil-plant-machine systems, electronic information and computertechnology applications in agriculture, precision agriculture, and

vehicle engineering, in South China Agricultural University. Hehas published more than 30 papers, of which 12 were compiled

into EI and 3 were compiled into ISTP. He has gained 2 utilitymodel patents, 1 invention patent and 2 computer softwarecopyright registration numbers.

Prof. Wu is now an IEEE member. He received the title ofoutstanding graduates of Guangdong Province in China fortwice, in 2004 and 2007. In 2006, he won Bronze Award of

National Challenge Cup business competition. He also



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participated in the tenth essay contest of virtual instrumentationapplications held by NI Company in China in 2009 and won theweb popularity award.

Tiansheng Hong, Male, born in 1955, obtained his bachelor's degree in 1982 at South China AgriculturalUniversity. In 1987 and 1990, Professor Hong received his

Master's and Ph.D degree in France. Afterwards, he has studiedand worked in France and Canada as a senior visiting scholar.

At present, Professor Hong holds concurrent positions as the

Dean of College of Engineering in South China AgriculturalUniversity, Director and Chief Scientist of National Citrus

Industry Technology Research System Machinery Laboratory.For his spare time, Professor Hong serves as member of theScience and Technology Committee in the Ministry of

Agriculture of China, member of the Chinese Society ofAgricultural Engineering, senior member for life in the Chinese

Society for Agricultural Machinery, member of the editorial board of IJABE, editorial member of the Transactions of theChinese Society for Agricultural Machinery etc.

He has engaged in teaching and research for the agriculturalengineering as well as for the mechatronics techniqueapplications.

Joseph Mwape Chileshe, Male, born in 1968, Lusaka, ismember of staff, in School of Engineering, University ofZambia. He obtained a bachelors of engineering degree in

Mechanical Engineering, University of Zambia, July 1991;Master's degree of Agricultural Engineering, South China

Agricultural University, June 1996. He then joined thedepartment of Agricultural Engineering, University of Zambiaas a lecturer in mechanization and machinery Design. Currently

he is pursuing postgraduate studies at the college of Engineering,South China Agricultural University.



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