A2T: automatic abstraction from RTL to TLM IPs. 2 Outline HIFSuite overview Motivation for...

A2T: automatic abstraction from RTL to TLM IPs

2

Outline

• HIFSuite overview

• Motivation for abstraction

• Abstraction techniques

• Tool features

• Tested benchmarks

EDALab s.r.l. – Networked Embedded Systems

HIFSuite overview

3EDALab s.r.l. – Networked Embedded Systems

HIFSuite overview

4

A2T: RTL to TLM

abstraction tool


Why automatic abstraction?

5

IP core(RTL)

CPU(Application +

Drivers)

Bus (TLM)

MEM(TLM)

TLMdesignTransactor

RTL IPreuse

IP core(RTL)



6

IP core(RTL)

CPU(Application +

Drivers)

Bus (TLM)

MEM(TLM)

TLMdesignTransactor

RTL IPreuse

IP core(RTL)

• RTL simulation is slow

• is the transactor correct ?



7

IP core(RTL)

CPU(Application +

Drivers)

Bus (TLM)

MEM(TLM)

TLMdesign

IP core(TLM)

RTL /IPabstraction

• Fast simulation• Correct by construction• OSCI TLM 2.0 compliant

Untimed/Loosely Timed -) Quantum Keeper (QK)-) Delay Time (DT)

DT=0 if Untimed

Approximately Timed-) Delay Time (DT)-) 2-4 phases


Abstraction steps

1. RTL HDL (i.e., VHDL, Verilog, SystemC) to RTL hardware intermediate format (HIF)

– Front-end conversion tool

2. RTL HIF to TLM HIF– A2T: merge of states, clock abstraction

3. TLM HIF to SystemC TLM– Back-end conversion tool


• Issues:– Different HDL semantics

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SystemC Verilog

VHDL

TLM

1. Front-end/Back-end conversion tool


– HIF has a proper semantics• HIF RTL (close to VHDL semantics) + HIF TLM

• Front-end tool maps any HDL-related construct into HIF constructs

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SystemC Verilog

VHDL

HIF(TLM) HIF

(RTL)

1. Front-end/Back end conversion tool (contd)


Framework for conversion verification

• HIFSuite Regression Suite (HRS)– HRS consists of two environments:

• From VHDL or Verilog to VHDL or Verilog– Synopsys Formality equivalence checking

• From VHDL or Verilog to SystemC (and viceversa)– Dynamic simulation via Mentor Modelsim + EDALab

ATPG (Ulisse)


Formal Framework: UNIVERCM

• Unique formalism for heterogeneous components– Handle discrete and continuous behaviors– Supports hardware and software descriptions

• Non determinism versus determinism• Allows elaboration of intermediate models for

– Software generation– Efficient system simulation

HIFSuite

UNIVERCM

Software

SystemCSystemC AMSSystemC TLM

Pure SW generation

Efficient simulation

p_count: process (clk)

begin

ContaByte <= '0’;

if Step = ‘1 then

ContaByte <= ‘1’;

end if;

end process;

D

E

C

B

F

AEntry SExit α, T

α

β

Offx>=24dx/dt=

-Kx

Onx<=25dx/dt= K(h-x)

x=24

x=25


HIFSuite conversion tool limitations

• Supported HDL constructs:– Almost all VHDL, Verilog and SystemC synthesizable

constructs supported• Ongoing work for complete support• Documentation available on current supported constructs

– Synthesizable constructs used in a non-synthesizable way supported! (e.g., while (x>0))

– TLM constructs supported only by the back-end conversion tool

• they are generated in HIF during abstraction


2. From RTL HIF to TLM HIF: A2T

• Tool features:– Merge of states and clock abstraction– RTL communication protocol abstraction– Cycle accurate to transaction accurate behavior

abstraction– Data type abstraction– Correct-by-construction TLM IPs

• event-based equivalence– OSCI TLM-2.0 compliant interfaces– 10x to 100x speedup depending on

• RTL IP structure and target TLM protocol


2.1 Merge of states and clk abstraction

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A B

uf0;

clk & ef0

uf1;

clk & ef1

uf2;

clk & ~ef1

A’uf0;while (~ ef1) { uf2

};uf1;

ef0

A B

uf0;

clk & ef0

uf1;

clk

RTL

A’uf0;uf1;

ef0

TLM


16

16

A

B

uf2;

clk & ~ef1 C

uf0;if ( ef1) {

uf1; // recursively, all the code representing

the path of state B }else { uf2;

// recursively, all the code representing

the path of state C };

ef0

A’

uf0;

clk & ef0 uf1;

clk & ef1

RTL

TLM

2.1 Merge of states and clk abstraction


2.2 RTL comm. protocol abstraction

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// write #1port_data data1;port_data_en true;wait();

// write #2port_data data2;port_data_en true;wait();

// write #2result_en port_result_en;while ( !result_en) wait();result port_result;

…

// write transactionpayload.command write;payload.data data1;b_transport(payload, t);

// write transactionpayload.data data2;b_transport(payload, t);

// read transactionpayload.command read;b_transport(payload, t);result payload.result;

…

RTL TLM


2.3 CA to transaction accurate behavior

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write_transaction( read(data1) )

Cycle-accurate (CA):

clk

data_INdata_en_INresult_OUTresult_en_OUT

data1<=data_IN.read()data2<=data_IN.read()

result_OUT.write()<=result

write()

read()

write_transaction( read(data2) )

read_transaction( write(result) )

end transaction

start transactionTransaction-

accurate (TA):


RTL-TLM event-based equivalence:• Bombieri et al. [ACM/IEEE MEMOCODE 2006, 2007];• Bombieri et al. [IEEE Transactions on Computer, 2010]

2.4 Data type abstraction

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IP core(RTL)

RTL /IPabstraction

IP core(TLM)

HIF SuiteAbstracted DataTypes (HADT) Library (C++)

HDL Data TypesLibrary

Data typeabstraction

HIFSuite HADT library:– Faster and more efficiente

implementation

– Logic and bit accurate types abstracted

– Two versions:• Multivalue logic abstracted

into 2-values logic• Multivalue logic mantained


2.5 OSCI TLM-2.0 compliant interfaces

• Different TLM IP interfaces can be generated during abstraction– Functionality code separated from protocol code– TLM 2.0 interfaces currently available:

• Untimed/Loosely Timed

– -) Quantum Keeper (QK)?

– -) Delay Time (DT)

» DT=0 if Untimed

• Approximately Timed

– -) Delay Time (DT)

– -) 2-4 phases

• Easily extendible


2.6 Speedup: tested benchmarks

• Div, Dist, Root VHDL/SystemC-RTL– Face Recognition System by STMicroelectronics

• ECC, CRC VHDL/SystemC-RTL– VERTIGO project Platform by STMicroelectronics

• Bxx VHDL/Verilog– ITC-99 suite

• ADPCM SystemC-RTL– Opencore

• FFT VHDL

– Magali Platform by CEA-Leti• I2C VHDL

– COMPLEX project platform by STMicroelectronics


2.6 Speedup: times


The tool


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Thank you

for further information please contact us:

[email protected]

http://hifsuite.edalab.it


mailto:[email protected]

http://hifsuite.edalab.it/

A2T: automatic abstraction from RTL to TLM IPs. 2 Outline HIFSuite overview Motivation for...

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