IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 66, NO. 7, JULY 2019 5231

A ZVS APWM Half-Bridge Parallel ResonantDC–DC Converter With Capacitive Output

Neilor C. Dal Pont, Delvanei G. Bandeira, Jr. , Member, IEEE,Telles B. Lazzarin , Senior Member, IEEE, and Ivo Barbi , Life Fellow, IEEE

Abstract—In this paper, a modified asymmetric half-bridge (AHB) isolated converter is proposed, which does nothave dc current offset in the transformer. The topology op-erates in the same way as the conventional half-bridge (HB),using asymmetric pulsewidth modulation with constant fre-quency. A voltage doubler rectifier is used in the outputstage, which avoids the flow of the dc component currentin the primary side of the transformer. In order to investi-gate the application of the proposed topology, a parallel-resonant (PR) version of the modified AHB was tested,which uses the parasitic elements of the transformer, suchas the leakage inductance and the winding capacitance, toachieve zero voltage switching in the primary side switchesover a wide load range. Theoretical and commutation analy-sis results are reported and design guidelines are presentedherein. Experimental data were obtained from a parallel res-onant 1-kW prototype, operating with a 50 kHz switchingfrequency, 400 V input voltage, and 400 V output volt-age, to verify the theoretical study, and 97% efficiency wasachieved. The proposed solution was also tested at highvoltage, operating with a rated power of 1.8 kW, switchingfrequency of 50 kHz, input voltage of 400 V and series-connected output voltages, the maximum voltage being8620 V.

Index Terms—Asymmetric pulsewidth modulation(PWM), constant frequency, efficiency, half-bridge parallelresonant, zero voltage switching.

NOMENCLATURE

Vi Converter input voltage.Vo Converter output voltage.V ′

o Primary referred output voltage.Io Load current.I ′o Primary referred load current.I ′o Primary referred normalized load current.Ib Base Current.

Manuscript received March 21, 2018; revised June 29, 2018; acceptedAugust 13, 2018. Date of publication September 10, 2018; date of cur-rent version February 28, 2019. (Corresponding author: Telles BrunelliLazzarin.)

N. C. Dal Pont, D. G. Bandeira Jr., and T. B. Lazzarin are withthe Department of Electrical and Electronic Engineering, Federal Uni-versity of Santa Catarina, Florianopolis, Santa Catarina 88040-900,Brazil (e-mail:, neilorcolombodalpont@gmail.com; delvanei.jr@gmail.com; telles@inep.ufsc.br).

I. Barbi is with the Department of Automation and Systems, FederalUniversity of Santa Catarina, Florianopolis, Santa Catarina 88040-900,Brazil (e-mail:, ivobarbi@gmail.com).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2018.2868270

D Duty cycle.q Static gain.Z Characteristic impedance.fs Switching frequency (Hz).ωr Resonance frequency (rad/s).μ0 Relation between switching frequency and resonance

frequency.n Transformer turns ratio.Lr Resonant inductor.Cr Resonant capacitor.Ts Switching period.tm Dead time.

I. INTRODUCTION

I SOLATED resonant dc–dc converters are widely used inapplications, such as hybrid and electric vehicles [1], re-

newable energy sources [2], [3], solid-state transformers [4],[5], high-voltage converters [6]–[9], power supplies and others[10], [11]. Nowadays, such applications require power convert-ers with high efficiency, low electromagnetic interference pro-file, and the integration of parasitic elements in the transformer.In addition, isolated versions need to be considered. The res-onant power converters can provide all of the aforementionedrequirements, due to the following operational features. First,they can provide zero voltage switching (ZVS) or zero currentswitching (ZCS) (or both) to all power switches, improving theconverter efficiency and extending the operation frequency ofthe switches. This feature is achieved by the integration of theparasitic elements that originate from either the converter com-ponents or from the high frequency transformer, this being thesecond feature.

A generic unit for a resonant dc–dc converter is shown inFig. 1. The key characteristic of this converter is the resonantblock, which comprises the integration of the parasitic elementsof a transformer. The configuration is totally dependent on theapplication and those most commonly employed for the resonantblock are series [12]–[14], parallel [9], [15]–[17], and seriesparallel [1] resonant circuits. In addition, advances in researchhave led to the introduction of the LLC [18]. The inverter blockhas a wide variety of combinations, and the choice is based onthe output power level, cost effectiveness, and voltage stress ofthe switches. In order to fulfill the requirements of the variousapplications, the topologies available are full-bridge [9], half-bridge [11], [12], [19], [20], t-type [15], [21], and push-pull [8],among others.

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5232 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 66, NO. 7, JULY 2019

Fig. 1. Resonant dc–dc converter block diagram.

In terms of the modulation scheme for resonant convertersthere are several techniques available, and frequency modulationand pulsewidth are the most common choices [22], [23]. In fre-quency modulation schemes, the duty cycle of the gating signalsof the switches are kept constant while their frequency variesover a wide range. This modulation scheme is chosen in order toobtain soft switching on switches and good load regulation, fromlight to full load. However, its implementation requires morecomplex hardware and the mathematical models employed forboth static and dynamic analysis are quite complex, since theymust overcome the nonlinear behavior of the converter. Anotherimportant drawback is the fact that the topology magnetics mustbe designed to operate at the lower frequency limit, and thus, theconverter design does not necessary favor miniaturization [24].When the resonant converter operates with pulsewidth modula-tion, soft switching in the switches is achieved with simple andwell established modulator technology, where power process-ing can be controlled by the duty cycle, and magnetics can bedesigned for the converter operation frequency [25], [26].

Regarding the topologies available for the resonant unit, thehalf-bridge topology offers low cost and low to mid power dueto its low active switch count [12], [27]–[31]. Research based onthis topology has been published in recent years considering awide range of applications, most of them using frequency modu-lation and a few with pulsewidth modulation (PWM) [32]–[36].The reason for this choice is related to the dc bias current thatflows through the transformer, the magnitude of which origi-nates from the parasitic elements of the converter, and smalltiming delays in the gate signals of the switches (in symmetricand asymmetric versions) [37]–[39]. Under these conditions,the core saturation of the transformer occurs during the con-verter operation and solutions, such as a core gap or a capacitorplacement, in series with the transformer winding need to beapplied. Due to this major drawback, this topology is limitedto the low to mid power category, where the transformer size isan issue to be addressed. However, studies are currently beingfocused on this challenge in order to improve the pulsewidthmodulated asymmetric half-bridge (AHB) performance, whichwould provide valuable benefits if the dc bias current could beeliminated [32], [40].

In order to improve the AHB resonant topology and addressthe aforementioned issues, the aim of this research was to con-nect a voltage doubler rectifier to the conventional AHB con-verter, which employs the fixed frequency PWM modulation.The voltage doubler rectifier in the output stage provides anequivalent capacitor in series with the transformer, thus avoid-ing the flow of the dc component current in both sides of thetransformer. Furthermore, the diodes of the output rectifier op-erates under ZCS conditions, which eliminates reverse recov-ery issues. These benefits are added to the conventional AHB

Fig. 2. AHB-PR-ZVS circuit.

Fig. 3. AHB-PR-ZVS equivalent circuit.

topology, which operates with ZVS over a wide range of loadsand remains with a low switch count, since no passive or activecomponents are added.

All of the aforementioned benefits of the proposed topol-ogy improve the converter efficiency using simple technologyand well established knowledge regarding the AHB converter.A similar approach can be found in [41]. However, the pro-posed solution introduces the AHB in the mid to high voltagefield, where a capacitive filter is employed. Hence, the proposedconcept is evaluated using a version with a parallel resonant con-verter, that is, a AHB-PR-ZVS converter. This converter usesboth the leakage inductance and winding parasitic capacitanceof the transformer at the resonant stage.

The structure of this paper is organized as follows. InSection II, the operation of the proposed converter is described.Section III details the theoretical analysis. Section IV illustratesa design example. Section V provides the experimental results.Section VI concludes this paper.

II. PROPOSED CONVERTER

The proposed AHB-PR-ZVS dc–dc converter is shown inFig. 2. The input stage is an HB inverter operating with APWM,in which the S1 switch conducts during the DTs period andthe S2 switch conducts in the complementary time period((1 − D)Ts ). The output stage is composed of a voltage doublerrectifier, which multiplies the output voltage as compared to thefull-bridge rectifier and thus it reduces the required turns ratioof the transformer windings. The resonant stage is a parallelresonant converter, where the transformer leakage inductanceand winding capacitance can be used to achieve ZVS in theprimary side switches and ZCS in the secondary side diodes ofthe transformer.

An equivalent circuit (shown in Fig. 3) is used in the theoret-ical analysis, where both the input capacitors (C1 and C2) andthe output capacitors (Co1 and Co2) are considered as voltagesources (VC 1 , VC 2 , VC o1 , VC o2) and the secondary parameters(VC o1 , VC o2 , Vo , io , is) are referred to the primary side (V ′

C o1 ,V ′

C o2 , V ′o , i′o , i′p ) of the transformer. The magnetizing inductance

PONT et al.: ZVS APWM HALF-BRIDGE PARALLEL RESONANT DC–DC CONVERTER WITH CAPACITIVE OUTPUT 5233

Fig. 4. Main converter waveforms.

Fig. 5. Converter state plane.

is neglected if it is much higher than the leakage inductance (witha ratio of around 25:1, the magnetizing peak current being 5%of the resonant inductor peak current), because it will have zeroaverage current due to the presence of the input and output ca-pacitors. However, its presence guarantees zero average voltageat the resonant capacitor.

The main waveforms of the AHB-PR-ZVS are shown inFig. 4. Here, the asymmetrical wave form of iLr can be ob-served, which generates the circulation of a harmonic current inthe converter. The normalized state plane that describes the res-onance trajectory is shown in Fig. 5. These two figures aid

an understanding of the operational stages of the proposedconverter.

The converter operation in the continuous conduction mode(CCM) has six operational stages. Due to the asymmetry, all ofthe operational stages must be considered in the analysis.

A. First Operational Stage (Δt1) [see Fig. 6(a)]

The first operational stage starts when S2 is turned OFF andS1 is turned ON. A resonant circuit composed of Lr , Cr , VC 1and V ′

C o2 is created. The resonant inductor current (iLr ) withinitial conditions (−I1) increases linearly until zero.

B. Second Operational Stage (Δt2) [see Fig. 6(b)]

The second operational stage starts when iLr reaches zero (Lr

is demagnetized). Thus, diode D2 blocks and then a resonantstage involving VC 1 , Lr , and Cr begins. In this stage, energytransfer to the output does not occur as shown in Figs. 4, 5,and 6(b).

C. Third Operational Stage (Δt3) [see Fig. 6(c)]

In this operational stage, the voltage at the resonant capacitor(vCr

) reaches the V ′C o1 value, and thus the diode D1 is forward

biased. The inductor current is positive, with an initial value I2and it increases linearly until this reaches the value I3 .

D. Fourth Operational Stage (Δt4) [see Fig. 6(d)]

The fourth operational stage is similar to the first stage andit starts when S1 is turned OFF and S2 is turned ON. The inputvoltage source provided by C2 (VC 2) is connected as a nega-tive voltage source on the input resonant circuit, as shown inFigs. 6(d), 4, and 5. The output voltage is V ′

C o1 and the inductorcurrent is positive (I3) and decreases linearly.

E. Fifth Operational Stage (Δt5) [see Fig. 6(e)]

Similarly to the second stage, the fifth stage starts with thecomplete inductor demagnetization, blocking the output recti-fier. Thus, diode D1 blocks and then a resonant stage involvingVC 2 , Lr , and Cr begins, which does not involve energy transferto the output [see Figs. 6(e), 4, and 5].

F. Sixth Operational Stage (Δt6) [see Fig. 6(f)]

As in the case of the third operational stage, in the sixth stagethe resonant capacitor voltage (vC r ) reaches the same value asthe voltage of the capacitor Co2 (−V ′

C o2), and thus, the diodeD2 is forward biased and the inductor current decreases linearly(from −I4 to −I1).

III. ANALYSIS

A. Equation

The analysis presented, in this section, is carried out for D >0.5, D being the conduction period of S1 . The analysis for

5234 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 66, NO. 7, JULY 2019

Fig. 6. Equivalent circuits for AHB-PR-ZVS operational stages. (a) First stage. (b) Second stage. (c) Third stage. (d) Fourth stage. (e) Fifth stage.(f) Sixth stage.

D < 0.5 will be complementary. Similar approaches to thatapplied in this study are introduced in [42] and [43].

From the resonant converters, the following relations can bederived:

Z =√

Lr

Cr(1)

q =V ′

o

Vi(2)

fo =1

2π√

LrCr

(3)

ωr =1√

LrCr

(4)

μ0 =fs

fo. (5)

The primary referred output voltage and the primary referredoutput current are given by

V ′o =

Vo

n(6)

I ′o = Ion. (7)

The input and primary referred output voltages are defined asfollows:

Vi = VC 1 + VC 2 . (8)

V ′o = V ′

C o1 + V ′C o2 (9)

On analyzing the circuit shown in Fig. 2, it can be notedthat the input capacitor average voltages are equal to the switchaverage voltages (VC 1 = VS1 and VC 2 = VS2). The voltageacross the switches is proportional to the conduction period andthus the voltages on the input capacitors are given by

VC 1 = VS1 = (1 − D)Vi (10)

VC 2 = VS2 = DVi. (11)

In relation to the output capacitor voltages, a similar relationcan be found regarding the voltage average values across therectifier diodes. The voltage V ′

C o1 is related to the first, second,fifth, and sixth topological stages and V ′

C o2 is related to thesecond, third, fourth, and fifth topological stages (as shownin Fig. 4). This is a nonlinear problem without an analyticalsolution and thus a simplified method to obtain these voltagesis introduced in this paper. The average values for the outputcapacitor voltages are defined by

V ′C o1 = VD1 =

V ′o

Ts

[Δt1 + Δt6 +

12(Δt2 + Δt5)

](12)

V ′C o2 = VD2 =

V ′o

Ts

[Δt3 + Δt4 +

12(Δt2 + Δt5)

]. (13)

On inspecting the waveforms in Fig. 4, the time interval re-lations Δt6 > Δt1 and Δt3 > Δt4 are observed. From theserelations, (12) can be approximated by (1 − D)V ′

o , since Δt6is proportional to (1 − D). Furthermore, for a D value closeto 0.5, (13) can be approximated by DV ′

o , since Δt3 is propor-tional to D. This set of assumptions introduces an error which isproportional to a variation in D. In order to reduce this error, alinear fitting of the capacitor average voltages, related to the Dvalue, is used, which tends to minimize the error. In the fittingprocess a KD parameter is introduced, given by

KD = A · D + B. (14)

Next, the approximated values for the output capacitorsaverage voltages are obtained as

V ′C o1 = V ′

o (1 − D + KD ) (15)

V ′C o2 = V ′

o − V ′C o1 . (16)

The A and B parameters of (14) are evaluated using sim-ulations. First, two limits are defined for the duty cycle (forD > 0.5 in this case), one for the maximum power transfer andone for the minimum load situation, considering the converter inCCM. Simulations are then performed for the two duty cycles,obtaining the voltages for the output capacitors at these points.

PONT et al.: ZVS APWM HALF-BRIDGE PARALLEL RESONANT DC–DC CONVERTER WITH CAPACITIVE OUTPUT 5235

Fig. 7. Simulations used to obtain KD parameters A and B .

In the next step, KD is fitted to each point of the duty cycleand thus the voltages obtained by (15) and (16) are equal to thevalues obtained in the simulation. For example, Fig. 7 shows theresults for the output capacitor voltage with fixed μ0 for D (0.55and 0.85). For D = 0.55, KD is adjusted in (15) for the outputcapacitors voltages equation result match the simulation result,and the same process is carried out for D = 0.85. With the twovalues for the duty cycle and KD , A and B are obtained as aresult of a linear system. It should be noted that the values for Aand B obtained in this example provide good results even whendifferent q and μ0 values are used in the converter analysis.

After the capacitor voltage definitions, the resonant stageequations are obtained through state plane analysis. The radii ofthe circumferences (Rd1 and Rd2) are described by

Rd1 = VC 1 + V ′C o2 (17)

Rd2 = VC 2 + V ′C o1 . (18)

The angles described during the resonant stages (β1 and β2)are defined by

β1 = arccos(

VC 1 − V ′C o1

VC 1 + V ′C o2

)(19)

β2 = arccos(

VC 2 − V ′C o2

VC 2 + V ′C o1

). (20)

The triangle geometric relationships of the state plane analysisare given by

Rd21 = (I2Z)2 + (VC 1 − V ′

C o1)2 (21)

Rd22 = (I4Z)2 + (VC 2 − V ′

C o2)2 . (22)

The angular velocity equation is given by

ω =β

Δt. (23)

Through the manipulation of (1) to (23), I2 and I4 and thenΔt2 and Δt5 are obtained, which are described by

I2 =√

Cr

Lr

√2(1 − D)ViV ′

o + V′2C o2 − V

′2C o1 (24)

I4 =√

Cr

Lr

√2DViV ′

o + V′2C o1 − V

′2C o2 (25)

Δt2 = β1

√LrCr (26)

Δt5 = β2

√LrCr . (27)

The equations of the linear stages, for Δt1 , Δt3 , Δt4 , andΔt6 , are given by

Δt1 = LrI1

(VC 1 + V ′C o2)

(28)

Δt3 = Lr(I3 − I2)

(VC 1 − V ′C o1)

(29)

Δt4 = LrI3

(VC 2 + V ′C o1)

(30)

Δt6 = Lr(I1 − I4)

(VC 2 − V ′C o2)

. (31)

From the time relations, the following are defined:

DTs = Δt1 + Δt2 + Δt3 (32)

(1 − D)Ts = Δt4 + Δt5 + Δt6 . (33)

Finally, based on Fig. 4, the average output current referredto the primary side of the transformer is defined as

I ′o =1

2Ts

(I1Δt1

2+

(I2 + I3)Δt32

+I3Δt4

2+

(I4 + I1)Δt62

). (34)

It is difficult to substitute all of the parameters in (34) and thiswould lead to a very large equation, so (34) is presented in thefinal form of the I ′o equation. The output voltage is generallydefined by the control, and μ0 is defined by the switching fre-quency and the resonance frequency. Thus, the control variableof the circuit is D, which can control the output voltage throughthe output current.

B. Static Analysis

The steady-state characteristics of the converter plottedthrough the output current normalized by a base current (Ib ),are shown

I ′o(q,D, μ0) =I ′oIb

= I ′o

√Lr/Cr

Vi(35)

where the base current (Ib) is defined by

Ib =Vi

Z=

Vi√Lr/Cr

. (36)

The static gain (q) versus the normalized output current, forD = 0.55 and different values of μ0 , is shown in Fig. 8, in

5236 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 66, NO. 7, JULY 2019

Fig. 8. Static gain versus normalized output current for D = 0.55 anddifferent μ0 values.

Fig. 9. Duty cycle versus normalized output current for μ0 = 0.1 anddifferent static gain values.

which a voltage source output characteristic for low values ofμ0 (around 0.1) and a current source output characteristic for ahigher value of μ0 can be noted.

The characteristics of the duty cycle versus the normalizedoutput current for μ0 and different values of static gain areshown in Fig. 9. It should be noted that the output voltage canbe controlled by duty cycle variations. As can be depicted fromFig. 9, the normalized output current reaches at its maximumvalue for duty cycle values near 0.5; with this behavior beingrepeated for different static gain values. Considering differentvalues of μ0 , the output power plot shows the same information.

C. Transformer DC Component Current Elimination

An approach to understanding the elimination of the dc com-ponent current by the voltage doubler is introduced in [44] andthis topology presents a similar scenario. First, the origin of thisdc component will be shown. In Fig. 10, the proposed structurecan be observed, but with a full-bridge output rectifier. The dccomponent of the current ip of Fig. 10 is eliminated through C1and C2 . However, there is no series capacitor with the currentis of Fig. 10, causing a nonzero dc current in the transformerwhen D �= 0.5. However, the dc component of the current ofFig. 2 will not occur, because the output current will always bein series with one of the output capacitors (Co1 and Co2), asseen in the operational stages, as shown in Fig. 6.

Fig. 10. AHB-PR-ZVS equivalent circuit with a full-bridge rectifier.

Fig. 11. AHB-PR-ZVS equivalent circuit with a full-bridge rectifierwaveforms.

Fig. 12. AHB-ZVS-PWM commutation circuit.

Fig. 11 shows the main waveforms of the AHB-PR-ZVS witha full-bridge rectifier. With regard to the output current, thehighlighted areas with lines represent the periods in which D2and D3 are ON and in the highlighted areas without lines D1and D4 are ON. These areas differ, and the difference betweenthe average current in each area represents the average currentof the transformer. On the other hand, in the case of the outputcurrent in Fig. 4, these two areas are equal.

D. Commutation

The proposed topology can achieve ZVS during the switchON-time of the primary-side switches. Due to the commandasymmetry, the resonant inductor current at moment of commu-tation varies for each switch. It can be observed in Fig. 4 thatI1 > I3 , thus the S2 commutation is considered critical.

The equivalent circuit at the moment of commutation is shownin Fig. 12. When one switch is blocked, it starts the charge or

PONT et al.: ZVS APWM HALF-BRIDGE PARALLEL RESONANT DC–DC CONVERTER WITH CAPACITIVE OUTPUT 5237

discharge process of the commutation capacitors (Cc1 and Cc2).The current in each capacitor is half of the commutation current(Ic ). Prior to the commutation, the voltage of the turned ON

switch is zero and of the blocked switch is Vi .Since the voltage variations of the switch capacitors (Cc1

Cc2) are linear, from Vi to 0, the critical commutation can bedefined by evaluating the time variation from the current-voltagecapacitor relationship, which gives

tc2 =2Cc2Vi

I3. (37)

The dead time has to be shorter than Δt4 so that it does notchange the operation stages. This can be achieved with a deadtime shorter than the period after the commutation (in the criticalswitch), because in this stage the inductor current will naturallyflow through the antiparallel diode of the switch. Therefore, thedead time (tm ) is defined by

tc2 < tm < Δt4 . (38)

IV. DESIGN

A design example is detailed in this section, with the follow-ing specifications: Vi = 400 V; Vo = 400; Po = 1 kW; fs =50 kHz. The first step is to define q through an analysis of Fig. 8.For low value of μ0 (around 0.1), is selected a value q, wherethe converter has a linear characteristic, being 0.667 in this case.Thus, the transformer ratio is calculated through (6) (n = 1.5).The next step is to define the duty cycle at the operational point.Based on Fig. 9, D = 0.55 appears to be a good choice because itis close to the maximum power transfer point and has a margin toload transients. Next, Io for 1 kW is calculated using Po = VoIo ,obtaining 2.5 A. Thus, using (5), μ0 is adjusted with q = 0.667and D = 0.55 to obtain Io = 2.5 A, being in this design μ0 =0.043. Then, with fs as a design parameter, a capacitor is chosen,and Lr is calculated through (5). In this case, a 0.5 nF capacitorand a 38 μH inductor are used. With these values defined, thetransformer is build and the values of the leakage inductance andwinding capacitance are measured. If the desired values of Lr

and Cr are equal to the leakage inductance and winding capac-itance values obtained, the design process is completed. If not,an external inductor and/or external capacitor should be added.

For the commutation design, first, the commutation capaci-tance is selected, which will be the sum of the switch outputcapacitance (Coss). In this case, a Cc2 + Coss of 2.5 nF is esti-mated. The value of I3 is then normalized applying the sameprocess presented in (35). Substituting I3 normalized in (30)and (37), and maintaining μ0 and q fixed by the design, it ispossible to trace the curves of Δt4(D) and tc2(D) as a functionof D, as shown in Fig. 13. Two important limits are shown inthis figure: Dtmax represents the intersection between Δt4(D)and tc2(D), this being the maximum duty cycle where the con-verter has ZVS at the inverter switches; and Dmax represents themaximum duty cycle where the converter is in CCM. From thegraph values of Dtmax = 0.79 and Dmax = 0.86 are obtained.Substituting Dtmax = 0.79 in (34), the maximum load where theconverter has a ZVS of 50% is obtained.

Fig. 13. Δt4 and tc2 in function of D.

TABLE ICONVERTER SPECIFICATIONS

TABLE IICOMPONENTS USED IN PROTOTYPE

With all of the parameters defined, the selection of the com-ponents can be carried out using the equations for the nominaloperational points.

V. EXPERIMENTAL RESULTS

A. Low-Voltage Application

In order to verify the theoretical analysis, a prototype withthe specifications in Section IV was designed, built, and tested.Fig. 14(a) shows the prototype scheme and Fig. 14(b) providesa photograph of the prototype. Tables I and II summarize theprototype specifications as well as the passive components andsemiconductors employed.

Once the design parameters had been defined, the transformerwas built, and the leakage inductance and intrinsic capacitancewere measured. For this prototype, the impedance analyzerAgilent 4294A was used for these measurements, providing a

5238 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 66, NO. 7, JULY 2019

Fig. 14. Prototype built for the AHB-PR-ZVS tests. (a) AHB-PR-ZVS cell that when connected to the rectifier comprises the low voltage ratedprototype. (b) Photograph of the prototype built.

Fig. 15. Drain source voltages (vS 1 -vS 2 ) and gate source voltages(vg 1 -vg 2 ) with nominal load for the primary side switches. Scale: vs =200 V; vg = 20 V; t = 5 μs/div.

leakage inductance value of 2.6 μH and a winding capacitanceof 0.01 nF, and a magnetizing inductance of 1 mH. Thus, theexternal inductance of 35 μH was added in series with the pri-mary winding of the transformer and the external capacitancewas added in parallel with the secondary winding, to obtain thedesign values.

The chosen switch (IPW60R041C6) has a Coss of 0.36 nF,so a commutation capacitor of 2.2 nF was added to thecircuit.

Experimental tests were performed for the CCM operation.Fig. 15 shows the drain-source voltages and gate source voltagesfor the primary side switches. The ZVS operation in the switcheswas verified, with no overshoot in the drain-source voltages, andthe switches clearly turn ON with zero voltage.

The voltage across the primary side of the transformer (vab )and the resonant inductor current can be seen in Fig. 16. On

Fig. 16. Primary side transformer input voltage (vab ) and current (iL r )with nominal load. Scale: vab = 200 V; iL r = 10 A; t = 5 μs.

analyzing these waveforms, the converter asymmetry can benoted, due to the different current peaks in the inductor anddifferent voltage levels in the inverter output.

The waveforms of the input and output voltage capacitors areshown in Fig. 17. There is an imbalance between VC 1 and VC 2and between VC o1 and VC o2 owing to the asymmetric command,as predicted in the theoretical analysis.

To verify the output characteristics, tests were carried out withdifferent loads and fixed duty cycle. The results are reported inFig. 18, in which the theoretical curves are plotted together withthe experimental points. A good agreement between the resultswas achieved.

The efficiency of the converter was measured using YokogawaWT500 and the results are shown in Fig. 19. The converteroperates with high efficiency (above 97%) for a wide load range,

PONT et al.: ZVS APWM HALF-BRIDGE PARALLEL RESONANT DC–DC CONVERTER WITH CAPACITIVE OUTPUT 5239

Fig. 17. Input and output capacitor voltages with nominal load. Scale:VC = 100 V; t = 200 μs.

Fig. 18. Theoretical (lines) and experimental (points) output charac-teristics of the proposed converter, for different duty cycle values andμo = 0.041.

due to the ZVS operation and also to the absence of the dc currentoffset in the primary side of the transformer.

B. High-Voltage Application

To demonstrate the potential application of the AHB-PR-ZVS, a high-voltage prototype was designed to feed a travellingwave tube (TWT) amplifier. The specifications used are basedon [9], in which the valve parameters are similar to those givenin Table III.

The primary side of the high-voltage converter is the sameas that of the low voltage prototype, as shown in Fig. 14(a).For this design, the parameters are D = 0.55, q = 0.78 andμ0 = 0.048. The secondary side is composed of a multiplewindings transformer, and each winding is connected to a volt-age doubler rectifier. The rectifiers employ MUR4100E diodes

Fig. 19. Proposed converter efficiency versus output power curve, withthe converter operating at input and output voltage of 400 V.

TABLE IIITWT PARAMETERS

Fig. 20. Voltage at outputs 3, 2, and 1 (Vo3 + Vo2 + Vo1 ) and resonantinductor current (iL r ). Scale: V = 5 kV; iL r = 20 A; t = 5 μs.

and 1 μF/600 V polypropylene capacitors. The output voltagesof the rectifier are series-connected. Hence, the outputs Vo1 ,Vo2 , Vo3 , and Vo4 are built with a group of series-connectedvoltage doubler rectifiers. This prototype also uses the leakageinductance (23 μH) and the winding capacitance (0.8 nF) fromthe transformer in its resonant circuit.

A high-voltage experimental result is reported in Fig. 20. Evenwith multiple secondary windings, the proposed APWM half-bridge parallel resonant maintains its characteristics, as seenby the inductor current (iLr ). The results demonstrate that theconverter is suitable for high-voltage applications.

VI. CONCLUSION

A study on the ZVS APWM half-bridge parallel resonantdc–dc converter with capacitive output, which uses a voltagedoubler rectifier, was carried out in this paper. The equation,static analysis, commutation analysis, experimental results, andapplications were reported herein.

5240 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 66, NO. 7, JULY 2019

The HB-PR-APWM with a voltage doubler rectifier operateswith zero dc-offset current in the primary side of the transformer,owing to the series connection of output capacitors over theoperation stages. Therefore, there was no need for additionalcomponents or a complex modulation scheme. The conventionalproblem in the resonant HB converter with traditional APWMmodulation, related to the core saturation, was eliminated in theproposed converter.

The theoretical analysis showed that the maximum powertransfer of the converter occurs with a 0.5 duty cycle, and itsvariation allows the gain of the converter to be controlled. There-fore, in this resonant topology, it is possible to control the outputvoltage through a variation in the duty cycle. Also, the commu-tation analysis demonstrated that the topology can provide ZVSin HB active switches (primary side) during the switch ON-timeover a wide range of loads, improving the converter efficiency.

All of the aforementioned benefits were verified based on twoprototypes. These prototypes were built to process an amountof power that was not usual for the half-bridge topology. In thelow-voltage rated prototype, a high efficiency (above 97%) andsoft switching for a load range of 60%–100% of the rated power(1 kW) was obtained. These results indicate that the power lev-els generally associated with the half-bridge structure can beincreased; hence, the second prototype was built. This high-voltage rated prototype, targeting TWTA applications, chal-lenges the proposed solution in terms of the dc-offset currentelimination and transformer design. The results obtained withthe high-voltage prototype demonstrate the feasibility of usingthe proposed converter in applications with high-voltage powersupplies. There is also the potential for application in otherpower electronics areas in which the conventional HB is notcurrently used, such in as electrical vehicles, battery chargers,and dc microgrids.

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Neilor C. Dal Pont was born in Criciuma, SantaCatarina, Brazil, in 1989. He received the B.Sc.and M.Sc. degrees in electrical engineeringin 2015 and 2017, respectively from the Fed-eral University of Santa Catarina (UFSC), Flo-rianopolis, Brazil, where he is currently workingtoward the Ph.D. degree in resonant converterswith the Department of Electrical and ElectronicEngineering, Power Electronics Institute.

His research interests include switched-capacitor converters, inverters, high-voltage dc–

dc converters, resonant converters and grid connected systems.

Delvanei G. Bandeira Jr. was born in Pelotas,Rio Grande do Sul, Brazil, in 1986. He re-ceived the B.S. degree in soft switching isolatedconverters for high voltages from the CatholicUniversity of Pelotas-UCPel, Pelotas, Brazil, in2011, the M.S. and the Ph.D. degrees in elec-trical engineering from the Federal Universityof Santa Catarina, Florianopolis, Brazil, in 2014and 2018, respectively.

He is currently a Research Engineer with theBrazilian Power Electronics and Renewable En-

ergy Institute. His research interests include soft switching, switchedcapacitors, resonant converters, solid state transformers, and high volt-age power supplies.

Telles B. Lazzarin (S’09–M’12–SM’18) wasborn in Criciuma, Santa Catarina State, Brazil,in 1979. He received the B.Sc., M.Sc. andPh.D. degrees in electrical enginering fromthe Federal University of Santa Catarina, Flo-rianopolis, Brazil, in 2004, 2006 and 2010, re-spectively.

He is currently an Adjunct Professor with theDepartment of Electronic and Electrical Engi-neering, UFSC. In 2006, he worked with indus-try, including R&D activities at the WEG Mo-

tor drives and controls, Brazil. He was a Postdoctoral Fellow withthe UFSC, in 2011 and a Visiting Researcher with the NortheasternUniversity, Boston, MA, USA, from 20017 to 2018. His research interestsinclude switched-capacitor converters, inverters, rectifiers, high-voltageand high-gain dc-dc converters.

Dr. Lazzarin is a member of the IEEE Industry Applications Society,IEEE Power Electronics Society, and IEEE Industrial Electronics Society.

Ivo Barbi (M’78–SM’90–F’11–LF’17) was bornin Gaspar, Santa Catarina, Brazil, in 1949. Hereceived the B.S. and M.S. degrees in electri-cal engineering from the Federal University ofSanta Catarina, Florianopolis, Brazil, in 1973and 1976, respectively, and the Dr.Ing. degreein electrical drives for induction machines fromthe Institut National Polytechnique de Toulouse,Toulouse, France, in 1979.

He founded the Brazilian Power Electron-ics Society and the Brazilian Power Electronics

Conference in 1990, and the Brazilian Power Electronics and RenewableEnergy Institute (IBEPE) in 2016.

Dr. Barbi is an Associate Editor for the IEEE TRANSACTIONS ON POWERELECTRONICS, the President for IBEPE, a Researcher with the Solar En-ergy Research Center and Professor of Electrical Engineering, FederalUniversity of Santa Catarina, Brazil.