A Zero-IF 60GHz Transceiver in 65nm CMOS with > 3.5Gb/s Links

A Zero-IF 60GHz Transceiver in 65nm A Zero-IF 60GHz Transceiver in 65nm CMOS with > 3.5Gb/s LinksCMOS with > 3.5Gb/s Links

Alexander Tomkins, Ricardo A. Aroca, Takuji Yamamoto*, Sean T. Alexander Tomkins, Ricardo A. Aroca, Takuji Yamamoto*, Sean T. Nicolson, Yoshiyasu Doi* and Sorin P. Voinigescu, University of Nicolson, Yoshiyasu Doi* and Sorin P. Voinigescu, University of

Toronto, Toronto, Canada, *Fujitsu Laboratories, Kawasaki, JapanToronto, Toronto, Canada, *Fujitsu Laboratories, Kawasaki, Japan

1University of Toronto 2008

Alexander Tomkins – University of Toronto 2008 2

System DescriptionSystem Description

Simple architecture appropriate for rapid Simple architecture appropriate for rapid file-transfer -> “Kiosk” applicationsfile-transfer -> “Kiosk” applications

Fundamental frequency, zero-IF Fundamental frequency, zero-IF architecturearchitecture

Direct BPSK modulation/demodulationDirect BPSK modulation/demodulation

Baseband NRZ data recovered with no Baseband NRZ data recovered with no ADCADC

Single-chip with TX and RX integrationSingle-chip with TX and RX integration

Design completed in 3-4 weeks (4 designers), with an immature design-kitDesign completed in 3-4 weeks (4 designers), with an immature design-kit

Performed hand design with only DC sims and no layout parasitic extraction tool.Performed hand design with only DC sims and no layout parasitic extraction tool.

Designed for 60GHz + 10%Designed for 60GHz + 10%

VDDIF+

IF-LNA

DataBuffers

RFin

Datain

LOin

Bias

÷ 2TX-

TX+

Div

Bias

LOTree

BPSK Modulator

Mixer

Divider

12mA

18mA

18mA

18mA

VDD

LO Buffer


Circuit Design Philosophy in CMOSCircuit Design Philosophy in CMOS

Tradition cascode stages:Tradition cascode stages:

Require VRequire VDDDD≥1.0≥1.0

VVDSDS will vary as a result of V will vary as a result of VTT variation variation

Different topologies are required in order to:Different topologies are required in order to:

Work with VWork with VDDDD < 0.9V < 0.9V

VVTT insensitive insensitive

VDD

VVDDDD ≥≥ 1.0V 1.0V

∆∆VVDSDS due to ∆ V due to ∆ VTT

*A 65nm CMOS wafer costs more than a 300GHz SiGe BiCMOS wafer**A 65nm CMOS wafer costs more than a 300GHz SiGe BiCMOS wafer*

CMOS does not make economic sense unless you integrate the DSP CMOS does not make economic sense unless you integrate the DSP

You must ensure that all topologies can scale to 45nm, 32nm ...You must ensure that all topologies can scale to 45nm, 32nm ...

∆ ∆ VVTT


VG

VDD

VDD

LO+LO- LO-

VDD

Ibias

Vout+ Vout

-

VDD

Ibias

VIN+

XFMR

AC-folded AC-folded CascodeCascode

XFMR-folded XFMR-folded CascodeCascode

Folded-cascode topologies with constant current biasingFolded-cascode topologies with constant current biasing

Only one high-speed transistor is placed between VOnly one high-speed transistor is placed between VDDDD and ground, and ground, maximizing the transistor Vmaximizing the transistor VDSDS..

All mm-wave blocks can be implemented with these topologies: All mm-wave blocks can be implemented with these topologies:

But there is a price: 2x the currentBut there is a price: 2x the current

Circuit Design Philosophy in CMOSCircuit Design Philosophy in CMOS

Low-Noise (Power) AmplifierLow-Noise (Power) Amplifier

5Alexander Tomkins – University of Toronto 2008

Input is noise and impedance matched to 50Input is noise and impedance matched to 50ΩΩ, with large output transistors for IIP3 and OP, with large output transistors for IIP3 and OP1dB1dB

80mA (60mA) from 1.2V (1.0V)80mA (60mA) from 1.2V (1.0V)

High gain to reduce receiver NF variation with temperature/processHigh gain to reduce receiver NF variation with temperature/process

M1

120pH

VDD

250pH

250pH

120pH

M2

120pH

VDD

120pH

130fF

VG

M3

100pH

VDD

92fF

VIN

1pF

M1, M2: 30x0.8umx60nmM3: 38x0.8umx60nmM4, M5: 50x0.8umx60nmM6: 62x0.8umx60nm

100pH

130fF

VG

M5

100pH

VDD

92fF

M4

100pH

M6

VDD

+

VOUT

-

VG

VDD

130fF

100pH

90pH

Direct BPSK Modulator and MixerDirect BPSK Modulator and Mixer


Data signal directly drives quad transistors of modulator [in SiGe: C. Lee Data signal directly drives quad transistors of modulator [in SiGe: C. Lee et al, CSICS 2004]et al, CSICS 2004]

Equivalent to a digitally modulated PA; operates in saturationEquivalent to a digitally modulated PA; operates in saturation

Both circuits drive off-chip directly in 50Both circuits drive off-chip directly in 50ΩΩ (mixer has no IF amplifier) (mixer has no IF amplifier)

DATA+

DATA- DATA-

90pH 90pH

VDD=1.2V

18mA

Vout+ Vout

-

40um 40um

VDD=1.2V59.2um 59.2um

20mA

VLO+VLO

-

2-coilXFMR0.77mA

VDD=1.2V

81.6um

800Ω

2.4um

83.2um

LO+LO-LO+

50Ω 50Ω

VDD=1.2V

12mA

Vout+ Vout

-

40um 40um

VDD=1.2V

From LNA

59.2um

VDD=1.2V

R=300Ω

R

R

4kΩ

20mA

VDD=1.2V

2-coilXFMR

41.6um

800Ω

0.77mA

2.4um

VDD=1.2V

81.6um

c

R

59.2um

New Frequency Divider TopologyNew Frequency Divider Topology


Single differential pair drives Single differential pair drives both latches:both latches:

Reduces footprint, Reduces footprint, increases speedincreases speed

saves power and areasaves power and area

50Ω 50Ω

VDD=1.2V

12mA

20um 20um

32um

330pH 330pH

50Ω 50Ω

VDD=1.2V

12mA

20um 20um

330pH 330pH

18mA

2-coilXFMR

2-coilXFMR

VDD=1.2V

32um

800Ω

VDD=1.2V

0.77mA

60.8um 1pF

CLK+

CLK-

Vout+

Vout-

2.4um

51.2um51.2um

Diagonally symmetric transformers

Compact divider core

CML buffer stage Merged latching quads Merged latching quads minimize feed-back pathminimize feed-back path

85um

220um

Transceiver Implementation – Die PhotoTransceiver Implementation – Die Photo


LNA Mixer

Divider

BPSK Modulator

LO TreeDiv Out

IF Out+

IF Out-

LO in

Data in

TX O

ut+

TX O

ut-

RX in

1.28mm

0.81

mm

Transceiver Implementation - TechnologyTransceiver Implementation - Technology


Fujitsu 65nm CMOSFujitsu 65nm CMOS

7-metal back-end, MiM capacitors7-metal back-end, MiM capacitors

Low-Noise (Power) Amplifier Low-Noise (Power) Amplifier MeasurementsMeasurements


-30 -20 -10 0 10-20

-15

-10

-5

0

5

10

58GHz, 25C 58GHz, 85C

Pou

t (dB

m)

Pin (dBm)

0

5

10

15

20

25

30

Gai

n (d

B)

@85oC = -12dBm@25oC = -14dBm

Peak gain of ~19dB, SPeak gain of ~19dB, S1111 better than -10dB up to 65GHz better than -10dB up to 65GHz

40 50 60 70-20

-15

-10

-5

0

5

10

15

20

-20

-15

-10

-5

0

5

10

15

20

S-P

aram

eter

s (d

B)

Frequency (GHz)

S11

S21

2525ooC, 1.2V: IPC, 1.2V: IP1dB1dB = -14dBm, OP = -14dBm, OP1dB1dB = +2.5dBm, P = +2.5dBm, PSATSAT = +7.5dBm = +7.5dBm

Frequency Divider Measurement (from TXRX)Frequency Divider Measurement (from TXRX)


Measured Receiver Gain and NF over Measured Receiver Gain and NF over Process CornersProcess Corners


Measured Receiver Gain and NF Over Measured Receiver Gain and NF Over Temperature and Power SupplyTemperature and Power Supply


Measured Transmitter Output Power vs. Measured Transmitter Output Power vs. Frequency over Temperature and VFrequency over Temperature and VDDDD


61GHz Carrier, 4.0Gbps 261GHz Carrier, 4.0Gbps 277-1 -1 PRBS SignalPRBS Signal


Signal Source 0 - 12 GHz

Power Splitter

Agilent 20 GHz Digital Scope

Centellax PRBS

Generator 0 – 12 . 5 Gbit / sec

Transceiver ( Transmit Mode )

Transceiver ( Receive Mode )

IF Amp 35 dB

4 GHz BW

Agilent Signal Source

0 - 67 GHz HP Signal Source

0 - 50 GHz

60 GHz LO

15 GHz

Millitec 4 x Multiplier 50 – 75 GHz

60 GHz LO

10 MHz Sync Signal

Trigger

Out - Out + Channel 4 Channel 3

~ 2 m

Horn Antenna 25 dBi

Clock

DC Signals

4 DC Signals

5

Data

IF

Horn Antenna

25 dBi

Transmit-Receive Link ExperimentTransmit-Receive Link Experiment

Transmit-Receive Test SetupTransmit-Receive Test Setup


Received EyeReceived Eye

RX Antenna (25dBi)RX Antenna (25dBi)

Receiver Probe-stationReceiver Probe-station

Received SpectrumReceived Spectrum

PRBS GeneratorPRBS Generator

TX Antenna (25dBi)TX Antenna (25dBi)

Transmitter Probe-station (not in shot)Transmitter Probe-station (not in shot)

~2m~2m

External 4GHz IF AmplifierExternal 4GHz IF Amplifier


Transmit-Receive Test Results – 4Gb/s @ 50°CTransmit-Receive Test Results – 4Gb/s @ 50°C

60.8GHz Carrier60.8GHz Carrier

4.0Gbps 24.0Gbps 277-1 PRBS Signal-1 PRBS Signal

Transmitter @ 50Transmitter @ 50°C, receiver @ room temperatureC, receiver @ room temperature

Data Transmission at 4 Gb/s (50°C)

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0 5 10 15 20 25 30 35time (ns)

-0.3

-0.2

-0.1

0

0.1

RX

TX


Transmit-Receive Test Results – 6Gb/sTransmit-Receive Test Results – 6Gb/s



Testing limited by bandwidth of IF amplifier (4GHz)Testing limited by bandwidth of IF amplifier (4GHz)

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0 5 10 15 20 25time (ns)

-0.3

-0.2

-0.1

0

0.1

RX

TX

SummarySummary


1.2V 60GHz zero-IF single-chip transceiver in 65nm CMOS1.2V 60GHz zero-IF single-chip transceiver in 65nm CMOS

Occupies only 1.28x0.81mmOccupies only 1.28x0.81mm22 (1.0mm (1.0mm22), consumes 374mW), consumes 374mW

Simple high-bandwidth, high data-rate architectureSimple high-bandwidth, high data-rate architecture

Proof-of-concept demonstration: wireless link over 2mProof-of-concept demonstration: wireless link over 2m

Data-rates up to 6.0Gb/s demonstrated (IF bandwidth limited above 4GHz)Data-rates up to 6.0Gb/s demonstrated (IF bandwidth limited above 4GHz)

First demonstration of a 60GHz wireless link at 50First demonstration of a 60GHz wireless link at 50ooC C

60GHz transceiver block characterization over process corners, 60GHz transceiver block characterization over process corners, temperature, and power supply.temperature, and power supply.

AcknowledgementsAcknowledgements


This work was funded by Fujitsu Limited. This work was funded by Fujitsu Limited.

Many thanks to Katya Laskin and Ioannis Sarkas for testing, Many thanks to Katya Laskin and Ioannis Sarkas for testing, measurement, and lab support.measurement, and lab support.

The authors would like to thank Jaro Pristupa and CMC for CAD support, The authors would like to thank Jaro Pristupa and CMC for CAD support, CFI, OIT, and ECTI for test equipment. CFI, OIT, and ECTI for test equipment.

We would also like to thank Dr. W. Walker of Fujitsu Laboratories of We would also like to thank Dr. W. Walker of Fujitsu Laboratories of America Inc. for his support.America Inc. for his support.


Backup Backup

60GHz SPST Switch (Stand-alone)60GHz SPST Switch (Stand-alone)


Tuned SPST switch for 60GHz operationTuned SPST switch for 60GHz operation

High-isolation from series-shunt transistor and 250pH inductorHigh-isolation from series-shunt transistor and 250pH inductor

Lower-insertion loss from 45pH shunt inductorLower-insertion loss from 45pH shunt inductor

Transmit-Receive Link ExperimentTransmit-Receive Link Experiment


Goal: Demonstrate successful data transmissionGoal: Demonstrate successful data transmission

““Bits in, bits out”Bits in, bits out”

Single-ended input data stream (PRBS sequence) fed directly on-chipSingle-ended input data stream (PRBS sequence) fed directly on-chip

Data stream reclaimed directly from the receiver IF output with no ADCData stream reclaimed directly from the receiver IF output with no ADC

One probe-station will act as a transmitter, one as receiverOne probe-station will act as a transmitter, one as receiver

Transmit channel formed by: Transmit channel formed by:

2m wireless link with transmitter/receiver 25dBi horn antenna2m wireless link with transmitter/receiver 25dBi horn antenna

Total channel loss (including input/output losses): 35dBTotal channel loss (including input/output losses): 35dB

Lack of on-chip IF-amp requires an additional external amplifier (limited to Lack of on-chip IF-amp requires an additional external amplifier (limited to 4GHz BW)4GHz BW)


Data Transmission at 2 Gb/s (50°C)

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0 10 20 30 40 50 60 70time (ns)

-0.3

-0.2

-0.1

0

0.1

Transmit-Receive Test ResultsTransmit-Receive Test Results



Transmitter @ 50Transmitter @ 50°C, receiver @ room temperatureC, receiver @ room temperature

Comparison TableComparison Table


A Zero-IF 60GHz Transceiver in 65nm CMOS with > 3.5Gb/s Links

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