A WCDMA/HSDPA Baseband ProcessorChien-Jen Huang and Hsi-Pin MaDepartment of Electrical Engineering

National Tsing Hua University, HsinChu, TaiwanEmail: cjhuang @larc.ee.nthu.edu.tw, hp @ee.nthu.edu.tw

TABLE IAbstract- In this paper, a baseband processor including whole DESIGN SPECIFICATION.

transceiver system for WCDMA/HSDPA communications is pre-sented. In order to resist the non-ideal effect of the wirelesschannel, the receiver of the proposed processor consists of a Physical channel CPICH_HS-SCCH1 HSPDSCHchannel estimator for channel estimation and receiver parameterscalculation, a carrier frequency synchronization and timing MCPCHQPSKsynchronization block for carrier frequency offset and clock ModulatidntVpe HS-SCCH QPKoffset compensation, moreover, an adaptive equalizer for IST HS~PDSCH QPSK I 16-QAMsuppression. In receiver architecture design, we adopt applicable CPICH 256 (fxd)algorithms to design each building blocks, so as to minimize SF HSWCCH 128 (fixed)the area complexity and power consumption but still with HS-PDSCH 1 iedgood performance. After system architecture design and systemperformance simulation, we do some rough evaluation from Detection CPICH Cob et Ddctonsystem architecture about the area and power consumption of Chip ratWthe proposed processor. Scrabling code Como1 Gold&& seuence

I. INTRODUCTION Spading codeD s Qn k-1 * +- + +L + ~~~~~~~ufti--cod Up t.1 oiti-cisd transmisionBefore 3G mobile communication systems, the most per-

sonal communication service is voice service limited by trans-mission data rate. However, in order to increase the transmis-sion data rate further, 3GPP/WCDMA introduces High SpeedDownlink Packet Access (HSDPA) in Release 4 and 5 [1]-[5]. III. ARCHITECTURE DESIGN

Since the higher modulation, higher coding rate, and moreadvance transmission techniques have adopted to achieve A Transmitterhigher system transmission rate, it is a tendency towards There are mainly three incoming data in the transmittersystem complexity increasing. before entering the complex scrambling for processing indi-

In this paper, a digital baseband processor for vidual physical channel data symbols simultaneously. The dataWCDMA/HSDPA communications systems with modified modulation for CPICH and HS-SCCH are QPSK. The datamultiple-dwell detection method for multi-path searching, a mapping of the HS-PDSCH has been adopted under QPSK,frequency recovery loop to obtain fast carrier synchronization, 16-QAM or even higher order modulation type in the future.a timing synchronization to provide correct data sampling, There is an AMC functional block to handle the modulationand finally a chip level equalizer to combat inter-symbol type and the number of multi-code transmission channel viainterference is proposed. a serial to parallel device.The rest of the paper is as follows. In section II, the HSDPA B. Receiver

system is briefly. Transmitter, receiving techniques and systemperformance simulation are provided in section III and section The whole architecture of proposed transceiver system isIV respectively. Architecture analysis are presented in section shown in Fig. 1. The receiver can be separated into fourV. Finally, some conclusions are given in section VI. parts: synchronization, equalization, de-spreading and symbol

II. SYSTEM DESCRIPTIONThe system design specifications are listed in Table 1. The C. Synchronization

proposed baseband transceiver is designed to achieve highest The synchronization part consists of a channel estimator,data rate of 10 Mbps information bit rate of HS-PDSCH when carrier synchronization, and a timing synchronization.the system reaches the maximum peak throughput under 16- In HSDPA systems, CPICH is the pilot channel with knownQAM data modulation, 3/4 coding rate, and 15 multi-code pattern for estimating the wireless channel conditions when thetransmitted simultaneously. receiver receives data. The data symbol from transmitter can

This research is supported in part by the National science Council, be represented as:Taiwan, R.O.C. under Grants NSC-94-2220-E-007-018 and National Chip-CS(M±]MQ*(Ci±ICQ)(1Implementation center. t= P(M+ MQ*(CI+JSQ)(1

0-7803-9390-2/06/$20.00 ©2006 IEEE 4519 ISCAS 2006

Synchronization S ht,ming Syn~I c armel C de 2 Ma9rnteQtoh.

Car r tSyn. EH mate G-emdEdE Pr6e4ver gM tEh com.put_tor I

input~ ~ ~ ~ ~ ~ ~ ~~~~~~~~~~~~~~~~~ptb

b~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~S 'sdF Itrl0~1nterpo1tion Equazer etHMSPDSCH

5Nuali@|zation{_ 4t Equa--at~on&} Ke-spreadng Fig. 2. Block diagram of channel estimator.

Fig. 1. Block diagram of the receiver.

peak value(Q, pk) peak value of the significant path providedby channel estimator as shown:

where SMI and SMQ are the I/Q channel symbols consist of F 1pilot and data information, the spreading code is notated as 4=tan' Qspk (4)CsP and CSC = (Csci + jCscQ) is the complex scrambling code. L is-pkThe pilot symbol extraction in receiver can be shown as: The Aco can be known by average phasor difference from

consecutive two peak values. That isSrx&cPICH (n) = Stx(fl)CSpcPIcH (n) * Cc(n)*, (2) /=Ao

where SspCPICH(n) is the corresponding spreading code of kr Qthe CPICH. After removing the spreading code of CPICH and tan Y, (Is pk,i + Qs pk,i) * (Is±pk,(i+1)+ Qs pk,(i+l))*scrambling code, I/Q values of the received pilot symbols can (5be re-written as: (5)

Srx-CPICH (n) In CDMA system, the sampling timing reflects on the

256 alignment of the PN code. For that reason, the delay-lock loop2CspcpicH (n)CspcpicH (n) (Smi ± jSMQ), (DLL) [8]-[10] technique is one of most popular solutions

n=1 (3) for timing synchronization. In this proposed receiver, two2 x 256(SMI + jSMQ). kinds of timing synchronization have been implemented. First

A matched filter is commonly chosen in the channel esti-we adopt 4-time oversampling of the input data for coarse

Amator hedrfasteandparallcom nlyhosn inthoeerchanlesy ltiming synchronization, which can provide the precision of

mator for fast and parallel correlation [6]. However, a symbol 1/8 sampling clock. The other part is the proposed modifiedlength matched filter may cause huge area overhead. Espe- digital DLL for timing tracking. The block diagram of thecially, the spreading factor of the CPICH is 256. Therefore, timing recovery loop is shown as Fig. 3. The proposed timinga pilot symbol length matched filter is unacceptable. In the recovery loop is composed of a interpolator, a loop filter, aproposed receiver, the multiple-dwell searching algorithm [7] NCO, and the early-late correlator included in the channelis adopted which can save large area cost without losing the estimator.system performance seriously. Certainly, it can also reduce the The timing recovery loop starts to work when the channelpower consumption efficiently. Fig. 2 is the block diagram estimator is in tracking mode since the information of the pilotof proposed channel estimator. It consists of a pre-filter, symbol is output form channel estimator at symbol rate. Thea complex-valued matched filter, a magnitude computation input data of the timing recovery loop is from the early-lateunit, an algorithm control unit and an early-late correlator. correlator in the channel estimator.Since the multiple-dwell detection algorithm is adopted with 4detection steps, we just need a 1/4 pilot symbol length matched D. Equalization and De-spreadingfilter (256(taps) = 64(chips) * 4(oversampling)) to collect the The rake receiver is most popular and conventional receiverdata symbols from the pre-filter and calculate the segmental in the DS-CDMA system. Unfortunately, the relative powercorrelations. The path detection and searching unit (PDSU) density of delay spread of the HSDPA is quite large. Thisexecutes the multiple-dwell detection, and make the decision means that the receiver may encounter large ISI. At thiswhether the correlation values of the matched filter outputs scenario, the rake receiver can no longer provide satisfactoryshould be accumulated or be discarded by controlling the performance, so an equalizer should be adopted.scrambling code coefficients. The channel estimator outputs Fig. 4 is the block diagram of proposed adaptive LMSthe delay profile and early-late correlation magnitude for other equalization and de-spreading architecture. This architecturefunctional blocks. consists of a random pattern generator, a 14-tapped length

Besides the channel estimator, it contains a phase detector, weight update filter, a 14-tapped length transversal filter and ainitial phase setting block, initial frequency offset block, loop correlator bank. The entire architecture can be separated intofilter and a numerical control oscillator (NCO). The initial two operation modes: training mode and de-spreading mode.phase offset 4) can be obtained by arctangent operation by I- In general, the training sequence is a random sequencechannel correlation peak value(Ispk) and Q-channel correlation with the properties close to the data symbol. The only one

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Fig 5. Obviously, the maximum data rate of 10.8 Mbps canh inputt X.... be achieved with satisfactory performance.

Channel Loop NCOesimator filer B. Fixed-point Simulation

The main objective of the fixed-point simulation is to figureCode out the minimum word length of the signals in receiver

gen2eratr without critical system performance degradation. The fixed-point simulation performance approximates to floating-point

Fig. 3. Block diagram of timing synchronization. simulation results.

-mm,W&S hua ' d6ii. ..1'..ii..i l... il_ dUn.t- I

Path 9enator RRt; ker C.num. 1I5jI;| Sprediing codes ..- ...=ilght upddate I I

Input _ FTR Fil er Corr-elator 1 zF>! |1.!,1, i_i,

Correlator 2 1 10 t wu f Ivi 9z i&<u M. fiix&i& &v u +S

I~~~9 P/Sjxk8= t w aCorrelator 1 *;-**;*Riidd*...............................

Fig. 4. Block diagram of equalization and de-spreading. 0_-0 5 10 15 20 25

SNR (dB)

downlink physical channel with the known symbol pattern in Fig. 5. BER versus SNR for multi-code simulation.this transceiver system is CPICH. However, the symbol patternof this physical channel can not to be served as the training V. ARCHITECTURE ANALYSISsequence because of its monotonous symbol pattern. In orderto solve the problem of training sequence, we proposed the Awekon, h n fmi atr cuishayaeconcept to generate the random training sequence by receiver complexity and power dissipation in receiver is matched filteritself. Because the training sequence iS generated by receiver as shown in Fig. 6 in channel estimator and equalizationitself, thus it iS necessary to join the channel conditions in circuit. Consider that, there are three main components ofitrainin seuncefosiuayting the channel ronse. the matched filter: a tapped-delay-line, scrambling coders and

In training mode of LMS algorithm, the training sequence Wallace tree adder. The tapped-delay-line is composed of thewI training the weight ute Fra filt After shift registers by D-type flip-flops for holding the incomingfinish training the weighting coefficients of update filter, the data. Since the complex scrambling code is bit operator,system will switch to de-spreading mode. In this mode, all the operation can be accomplished by using two 4 to 1functionail blotck to dentirearchitecture arde. undes wor

amultiplexers to select the product value. Besides, the Wallace

functional blocks of entire architecture are under working.treadrwt h : ar-sv de CA sue o

The filter of the input data symbol is working for eliminating tree adder With the 4:2 carry-save adder (CSA) is used forthe ISI effect with weighting factors from trained coefficients isumminglup the de-scrambi vle. Threfore,nehardwarof the weight update filter. On the other hand, the random issues analysis can be done by these circuit components. Inpattherngeneratorandweight updatefil FRflther k upatng our hareware issues evaluation, several 1-bit operation unitspattern generator and weight update FIR filter keeps updating

fo .8g rcs t18Vspl otg r mlydithe weight coefficients to data symbol filter periodically by for 0.18-gm process at 1.8-V supply voltage are employed inmonitoring the channel conditions to make equalization appli- comcable in variable channel. The estimation results and comparisons of matched filters

are shown in Table 2. Theoretically, by means of (1/4) symbolIV. SYSTEM SIMULATION length matched filter can get 75% area and power reduction.

Practically, there still need an additional logic control circuitblock to execute the multiple-dwell algorithm we call PDSU

The floating point simulation results are used to evaluate previously. From Table 2, it is not hard to observe that the logicsystem performance. The channel model adopted here is PB3 control circuit does not take much area and power. Therefore,propagation condition of multi-path fading environment for by this algorithm, it still can achieve 50% area and powerHSDPA specified in 3GPP standard under 16-QAM. Moreover, reduction as shown in Table2.3-ppm carrier frequency offset and clock offset (6000 Hz Besides matched filter, another component plays an impor-relative to the 2GHz RF frequency and 15.36 MHz sample tant role of this baseband processor is LMS equalization. Forclock) are considered. The multi-code simulation is shown as convenience to analyze the dominant operation complexity of

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TABLE IIIcorrefaion OPERATION BREAKDOWN OF PROPOSED EQUALIZATION.

tLoutput 1

N/Rumber of OperatingATmethnc& Oper6ationi Frequency

Weighft ukpdat Compolex MlUpticahn1coer 1 I oder 2 POeW 4 3 cc &4 HR fliter (144Ws)*(9bNs)

in _ l_i1Tapped-delay line (64M4 tps) t lIt Cp 14

EVALUATION OF THE ARE AN OERCMjPINOMTHD nrainWoft hardwaeitAitcaompeityadpwrcnupini

FILTER. undoubtedly true. The multiple-dwell algorithm is adopted to

Et-mtonleS 1024 taps Thi Wor Reuto R.. sm prlimnr anlyi of mace fil;Ete (Xandlequaliza||t;Ion,

er.4r5 061%red p ation c fulre.Cmsumtm50 2U.52

Fig. 6. Proposed matched filter architecture. higher modulation and some advanced transmission techniquesTABLE II have been adopted to achieve higher transmission data rate, the

EVALUATIONOFTHEAREA AND1OW91 OMSUPTI4 N 51%MATincreasing of hardware complexity and power consumption is

FILTER. undoubtedly true. The multiple-dwell algorithm is adopted todesign the complex matched filter in channel estimator. Via

Estirn6tioh ItlbMns 1024 taps Thit Wblk RledlLittion RAIJ some preliminary analysis of matched filter and equalization,d rmalizd Are ha o1 areacom(0ex)tR anH power savPng areexAecleo 4tea1izdPoe 136 03792 T[line]. lae: t

Ait 1477632 1738816 1 50% proposed matched filter compared to a full-tap matched filter

,~~~~~~~~~~~~~~~set (Rles 5. TS2.85 v00. [nie. Aviale tp

rn)m2 i ~rnblTuRqc:iuEIbd I

AwjkMtMeI 534380 1z262920 51 ff but still with satisfactory performance. Furthermore, advanced

th euaizon,lbdid6labreiakdowof--- 28997t component--- arithmetical algorithm and efficient implementations can beEvidbet l Aly t 3363692m i 1629628d et6% used to replace complex multipliers in equalization block to

PbW@r wol@li I 145 1 a612 | 75% reduce implementation cost further.CcnFrntio k| 1hcombi:dbt | 5-0 1 2525 | 50%

( rR v REFERENCES

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