A Very Low Power CMOS Mixed-Signal IC for … Very Low Power CMOS Mixed-Signal IC for Implantable...
Transcript of A Very Low Power CMOS Mixed-Signal IC for … Very Low Power CMOS Mixed-Signal IC for Implantable...
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A Very Low Power CMOS Mixed-Signal IC for Implantable
Pacemaker Applications
Louis S. Y. WongRaymond Okamoto
Joseph Ahn
St. Jude MedicalCardiac Rhythm Management Division
Sunnyvale, CA
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Questions:(1) What year was the 1st pacemaker
introduced?
(2) How many transistors are there in the 1st pacemaker?
(3) How many transistors are there in today’s (2004) pacemaker?
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Outline• Overview of Cardiac Pacemaker• Overview – Sensing• Overview – Output Therapy System• Overview – Battery Management System• Overview – Low Power Logic Design• Overview – Low Power Memory Design• Overview (MEMS) – Activity Sensor• Overview (MEMS) – Magnet Sensor • Silicon Results
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Overview of Cardiac Pacemaker – What is it?
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Cardiac Pacemaker System
Picture of an actualImplantable Pacemaker
2 inch
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Pacemaker – Simplified Block Diagram
ElectrodeConfig.
Switches
A/D Converters
& Detectors
Programmable Logic
&Timing Control
&Therapy
Algorithms
Memory
Telemetry Circuit
Physiologic Sensor
Battery Power Management
System Voltage &
Current Reference Generators
Monitoring &
Measuring System &
ADC
High Voltage Multiplier
High Voltage OutputPulse
Generator
Sensing&
FilteringAmplifiers
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Die Photograph
7000µm
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Overview of Cardiac Pacemaker – Cardiac Sensing System
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Sensing System Block Diagram
Passive FilterNetwork
Out # 1
Out # N
MU
XM
UXPassive Filter
Network
Passive FilterNetwork
MU
XM
UXPassive Filter
Network
ADC
ADC
Cardiac Inputs
(µV-mV)
Low-Power Switched-Capacitor Filters/Amplifiers
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Low Power SC Circuits - Problem
Chold
Vin
I1
I3
I2
VoutVhold+-
Vdd
Vss
A “Sample-hold Amplifier”used to illustrate the problem
Illustrated by a SC SH amplifier:• Residual leakage current (~pA)
when CMOS switch is off• Cardiac/Neuro-signals have low
frequency content ~0.1Hz• Signal amplitude of interest ~µV-
mV
If leakage=1pA, Chold=1pF, hold time=100mS, thenVout drift = 100mV (Unacceptable)
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Leakage Cancellation Technique -Concept
Chold
Vin
I1
I3
I2
VoutVhold
Icancel=I1+I2+I3
Self-adjusted currentsource
+-
Vdd
Vss
The concept of “Leakage Cancellation Technique”
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Leakage Cancellation Technique -Concept
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.00 0.20 0.40 0.60 0.80 1.00
Time (sec)
Vo
ltag
e (V
)
Vrep
VholdChold
Vin
I1
I3
I2
Vhold
Crep
I1
I3
I2
Vrep
Vdd
Vss
Vdd
Vss
Mp
Mn
Mp
Mn
Introducing the “Replica SH Circuit”, with Crep << Chold
Main SH Circuit
Replica SH Circuit
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Leakage Cancellation Technique - Design
A design example of the “Leakage Cancellation Technique”CrepChold
VA
Aoutf
CrepCholdI
dtdV offset
deltahold
−
+=
−=
)(
Chold
Vin
I1
I3
I2
VoutVhold
Crep
I1
I3
I2
Vdd
Vrep
A1
Vss
M1
Replica SH Circuit
Vdd
Vss
M5
Leakage currentcancallation
feedback
-+
+-
M4
M7M3
M6M2
M8
Vdd
Vss
Vdd
Vss
Mp
Mn
Mp
Mn
Aout
I cancel
I cancel
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Leakage Cancellation Technique -Results
SHA (Original)1Hz sine input, Fs=10HzI leakage ~ 0.1pA total
SHA with Leakage Cancellation1Hz sine input, Fs=10Hz
I leakage < 0.01pA (effective)
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Overview of Cardiac Pacemaker – ADC
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8-bit ADC• ADC is used to digitized the cardiac sensing
outputs• Successive Approximation Architecture • Typical power consumed by:
– S/H – DAC– Comparator
• To minimize power, this ADC:1. Uses capacitor-array for both DAC and SHA2. Use an integrated-opamp for both SHA and
comparator
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8-bit ADC – ArchitectureSuccessive Approximation
Controls and Registers
C 128C2C 4C
Vin VREF_1
VREF_0
SHA & Comparator
Clk_16K8b OutputDone
CompOut
Integrated “S/H-comparator”
SHA Out
C 2C 4C 8C C 2C 4C 8C
Capacitor array for S/H and DAC
Cs
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8-bit ADC – Timing
Clock
Output[7:0]
Analog Input
Data1
Sample1
SHA
SAR
Done
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8-bit ADC – Measured Results8-bit ADC INL
-2
-1
0
1
2
1 52 103 154 205 256
Code
INL
(LSB
)
10Hz input sinewave (-6dB of full scale)
-100
-80
-60
-40
-20
0
0 100 200 300 400 500
Frequency (Hz)
Am
plit
ud
e (d
B)
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8-bit ADC – Measured Results
~ 150nA @ 2VSupply Current (On)
~ 20nASupply Current (Standby)
500mVppInput Voltage Range
< 1.5 LSBDNL
< 3 LSBDC offset error
< ±10% FSGain error
> 48 dBSFDR
< 1.5 LSBINL
1 KS/sSampling Rate8-bitsResolution
ValueParameter
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Complete Sensing System –Measurement Setup
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Complete Sensing System (SC Filters and ADC) – Example ECG Results
An example ADC output of Electrocardiogram (ECG) processed by different SC filters.
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Overview of Cardiac Pacemaker – Output Therapy System
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High Voltage Output System
• To stimulate the heart muscle (e.g. initiate a heart beat), a high-voltage output pulse is delivered to the heart through the pacing leads.
• Multiplying the battery voltage is needed to generate the necessary high voltage. Ø A Voltage Multiplier Circuit is used
• The amplitude and pulse width of the high-voltage output pulse is customized for the patients.Ø A High Voltage DAC is used
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High Voltage Multiplier(Not to scale)
Vreg
2*Vdd
3*VddVoltage on chip
Hi-volt output pulse
On-chip analog &
digital
Battery management & references
Usage
Voltage Multiplier
Voltage regulator
Battery(Vdd ~ 2.8V)
Voltage Multipliers and Regulators for the complete IC
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Capacitive Voltage Multiplier –Design
φ1
φ2
C2
φ1
φ2
φ2
φ2
φ1
φ1
C1
Cres2 = 2*Vdd
Cres3 = 3*Vdd
Vdd
Vss
Capacitive 2X and 3X voltage multiplier
φ1, φ2: Non-overlapping clocks
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High-Voltage DAC – Design
Hi-Voltage Output Pulse Generator:
Switched-Cap DAC
φpre
φout
φpre
φout
C2
φoutC1
φpre
Vref
Vss
Output Pulse
Vout
Hi-Voltage Output Pulse Generator: Equivalent model Hi-Volt
DAC φout
Power Supply = 2* or 3* Vdd
Pulse Amplitude
Hi-Volt OutputPulse
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High-Voltage DAC – Design
Vref
Vss
2-in-1 (HV/LV) CMOS opamp
Vout
VbVb
Vdd
V+ V-
Supply = 2*Vdd or 3*Vdd
Freq CompVpre
Vss
Normal MOSFET
Hi-Volt MOSFET
φpre
φout
C2φoutC1
φpre
Vout
Vpre
2-in-1 opamp
φpre
High-Voltage DAC utilizing 2-in-1 opamp
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High-Voltage DAC – Measured Results
Output Pulse Vs input code
0
1
2
3
4
5
6
7
8
9
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
Digital input code
Ou
tpu
t Pu
lse
(V)
Linearity of Output Pulse Amplitude
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Overview of Cardiac Pacemaker – Battery Management System
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Battery Management System
• A primary battery (~2.8V) is typically used for a 5-10 years of device life time.
• Battery status must be accurately monitored to guarantee reliable operations.
• The status of the battery is determined by measuring its output voltage. However, it may NOT be very accurate due to the flat output voltage characteristics.
• To enhance accuracy:– A Battery Charge monitoring circuit
(Battery Charge Meter) is proposed.
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Battery Management System –Block Diagram
Primary Battery
Voltage Reference Generators
VTrip1
VTrip2
VTrip3
Battery Volt Detectors
+ -
Status_1
Status_2
Status_3
To the rest of the chip
Battery Management System
Battery Charge Meter
VCO
Binary Counter
32-bit Charge Meter
RI(t)
Vin_p Vin_n
Battery Charge Meter:• Low offset, high linearity VCO• Continuously monitors 0.5µA-100µA of current • Very low power consumption
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Battery Management System –Battery Charge Meter
• VCO output frequency:
• The output of the counter:
• Re-arrange to give:
• Knowing “Count, KVCO and R”, the total charge depleted from the battery can be accurately calculated.
RtIKFreq VCOVCO ××= )(
dtRtIKdtFreqCount VCOVCO ∫∫ ⋅××=⋅= )(
RKCount
dttIeChQVCO ×
=⋅== ∫ )(arg
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Battery Charge Meter - Design
Voltage Reference generators
VTrip1
VTrip2
VTrip3
Battery volt Detectors
+ -
Status_1
Status_2
Status_3
To the rest of the chip
Primary Battery
Battery Management System
Battery charge meter
VCO
Binary Counter 32-bit Charge Meter
RI(t)
Comparator VCO output
Integrator(switched-
cap)
Vin_pVin_n
Vref_p
Vref_n
Vref_p
Vref_n
Vramp
Integrator Vramp
Vdd
Vss
VCO Out
Time
K
Battery charge meter – VCO block diagram
Vin_p Vin_n
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Battery Charge Meter – VCO Design
int
__ )()_(
CCVV
stepperV sninpinramp
×−=
φ2
ComparatorLow-Power Auto-Zero
Switched-Cap Integrator
Vref_p
Vref_n
VrampK
K
K
K
K
K
φ1
φ1
K
Cint
CS
K
Vin_pVin_n
φ2
φ1
φ2
φ1
VCO Outputs
φ1, φ2: Non-overlapping clocks
ComparatorVCO
output
Integrator(switched-
cap)
Vin_pVin_n
Vref_pVref_n
Vref_p
Vref_n
Vramp
Integrator Vramp
Vdd
Vss
VCO Out
Time
K
Battery charge meter – VCO block diagram int__
__
)(2)(
CVVCFVV
Freqnrefpref
ssninpinVCO ×−
××−=
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Battery Charge Meter – Measured Results
~ 100nA @ 2.8V
Supply Current (On)
< 10nASupply Current (Standby)
< 150µVInput Offset Error
8 KHzSampling Rate
80 Hz/VVCO Gain
0mV - 50mVInput Range
ValueParameterBattery Charge Meter - VCO Linearity
0
20
40
60
80
100
120
0 0.005 0.01 0.015 0.02 0.025
Differential Input Voltage (V)
Ou
tpu
t F
req
uen
cy (
Co
un
ts p
er 6
0 se
c)
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Battery Charge Meter – Measured Results
Battery Charge Meter - VCO Linearity
0
20
40
60
80
100
120
0 0.005 0.01 0.015 0.02 0.025Differential Input Voltage (V)
Ou
tpu
t F
req
uen
cy (
Co
un
ts p
er 6
0 se
c)
To the rest of the chip
Battery charge meter
VCO
Binary Counter CounterOutput
R
Vin_p Vin_n
Now, we have:• Kvco = 80Hz/V, R = 500Ω and assume a 1A-h battery
• At the end of battery life, the counter output will reach:144,000,000 counts
(It is also independent of the battery output voltage!)
32-bit Binary
Counter
RKCount
dttIeChQVCO ×
=⋅== ∫ )(arg
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Overview of Cardiac Pacemaker – Low Power Logic Design
by:
Raymond OkamotoRaymond Okamoto received his B.S. ECE from U.C. Santa
Barbara. He has 15+ years in both hardware and software designs. He has previous worked for ArgoSystems, Trimble Navigation, Intel and Mentor Graphics. He has designed both GPS and networking ASICs as well as other hardware systems. He joined St Jude Medical in 2003.
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Programmable Logic, Timing Control and Therapy Algorithms
• CPU Configuration Registers• Timing and control for Analog Functions• Finite State Machine under CPU control for Therapy
Algorithms• Hardware Control Finite State Machine in backup (fail
safe) mode to delivery therapy• RTL to GDSII design flow• Low Power Design (nW)
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Digital Core Lower Power Techniques
• Minimize Voltage– Trade off custom low power library vs standard library– Backend Flow with multiple power
• Minimize Clock Frequency– Gated Clock Design– Review of minimum clock frequency required
• Minimize Capacitance (Logic Area)– Design for minimum logic at the RTL level– Reduce clock domains (trade off with min clock frequency)
• Customize Clock Synthesis Tool for low power vs high speed trees
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Clock Tree SynthesisCustom Approach to minimize buffer insertion
5 : 1 Aspect Ratio for Digital Core
Hand Placed Initial Clock Buffer
Minimize Buffer Insertion to balance system clock to 8 Clock Domains
Added hand placed buffers Around clock divider Flip Flops to minimizeClk to Q Delay ( reduce buffers for clock balancing)
Clock Divider
…
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Overview of Cardiac Pacemaker – Low Power Memory Design
by:
Joseph AhnJoe Ahn received his B.S. and M.S. EE from Lehigh
University. He has 11+ years in hardware design. He has previous worked for Virtual Silicon Technology, C-Cube Microsysytems and Aspec Technology. He has designed various components including SRAM’s, ROM’s, datapath blocks, I/O’s and standard cells. He joined St Jude Medical in 2002.
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Ultra-Low Power SRAM for Pacemakers and ICD’s
• The three components of power• Capacitance
– Reduce switching of high capacitive nodes
• Voltage– Reduce the voltage swing
• Frequency– Lower operating frequency
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Reduce switching of high capacitive nodes
• Smaller subsections• Shorter word-lines
and bit-lines• Disable inactive
circuitry• Local decoders vs.
global decoders
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Reduce the voltage swing
• Partial voltage swings• Low power sense amp• Special manufacturing
processes– Lower operating voltage– Leakage current– High Vt devices
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Lower operating frequency
• Lower operating frequency
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Overview of Cardiac Pacemaker – MEMS Activity Sensor
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Patient Activity Sensor
• Patient activity sensor is used to:– Sense patient’s body movements, and to
determine the appropriate pacing rates for correct therapy.
– An “Accelerometer Sensor” is placed inside the device.
– Be able to differentiate between patient movements from surrounding noise (egvehicle vibration, vacuum cleaner)
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Activity Sensor Interface Circuit
Piezo-electric Sensor
• It generates a charge/voltage proportional to the patient’s acceleration.
• The VCO generates an output signal whose frequency is proportional to the voltage sensed at the input. The number of cycles of the VCO output is proportional to the average patient physical accelerations.
• Low power consumption ~ 40nA
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Overview of Cardiac Pacemaker – MEMS Magnet Sensor
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Magnet Detection Sensor
• A magnet detector can be used to:– Open the telemetry channel– Disable the device– Put the device into a special operating
mode, e.g. in emergency
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Magnet Detection Sensor
Two types of magnetic sensors are typically used:
1. Reed Switch2. Giant Magneto Resistive (GMR)
Sensor
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Reed Switch Interface Circuit
• Low pass filter• Debouncing circuit to filter out glitches• Very low power consumption ~ 20nA
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Overview of Cardiac Pacemaker – Silicon Results
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Silicon Results
7mm x 7mmDie Size
~ 8µWPower Consumption
2.0V – 2.8VSupply Voltage
ValueParameter