A Two-channel 10b 160 MS/s 28 nm CMOS Asynchronous ...eeic7.sogang.ac.kr/paper file/international...

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.5, OCTOBER, 2017 ISSN(Print) 1598-1657 https://doi.org/10.5573/JSTS.2017.17.4.636 ISSN(Online) 2233-4866

Manuscript received Dec. 22, 2016; accepted Sep. 8, 2017 Department of Electronic Engineering, Sogang University, Seoul, Korea E-mail : [email protected], [email protected]

A Two-channel 10b 160 MS/s 28 nm CMOS Asynchronous Pipelined-SAR ADC

with Low Channel Mismatch

Tai-ji An, Young-Sea Cho, Jun-Sang Park, Gil-Cho Ahn, and Seung-Hoon Lee

Abstract—This work proposes a two-channel T-I 10b 160 MS/s asynchronous pipelined-SAR ADC minimizing offset and gain mismatches between channels without any calibration. Each channel of the proposed ADC is based on a two-stage pipelined-SAR topology, where the first and second stage determines 4b and 7b, respectively, for high conversion rate and low power. An asynchronous SAR algorithm removes on-chip high-speed clock generators for SAR operation, while a simple detection circuit solves a meta-stability problem of the comparator commonly observed in asynchronous SAR ADCs. Analog circuits such as comparators and residue amplifiers are shared to capacity between two channels to reduce various channel mismatches limiting the linearity of the T-I ADC. Three separate reference voltage drivers for two SAR ADCs and a residue amplifier prevent lots of undesirable disturbance among reference voltages due to each different switching operation. The prototype ADC in a 28 nm CMOS process demonstrates a measured differential and integral non-linearity within 0.71 LSB and 0.70 LSB at 10b, respectively, with a maximum signal-to-noise-and-distortion ratio and a spurious-free dynamic range of 51.43 dB and 62.01 dB at 160 MS/s, respectively. The proposed ADC occupies an active die area of 0.23 mm2 and consumes 3.5 mW at a 1.0 V supply voltage.

Index Terms—Asynchronous successive approximation register (SAR), time-interleaved (T-I), comparator sharing, offset mismatch, separate reference

I. INTRODUCTION

Recently, advanced nanometer CMOS technologies allow very low-power system design with a small chip area. In addition, the system-on-a-chip (SoC) enables the integration of various digital circuits and analog circuits together into a single chip. Most of the SoC applications essentially require some kind of interface circuits such as an analog-to-digital converter (ADC) that can convert analog signals into digital signals accurately and reliably. In particular, the ADC for some high-resolution mobile video systems requires a minimum resolution of 10b and a sampling rate exceeding 150 MS/s with low power and small die area [1-6]. In the conventional high-resolution mobile video applications, the pipelined ADC has been commonly employed to satisfy the requirements of high image quality and wide bandwidth.

Meanwhile, the successive-approximation register (SAR)-based ADC primarily using digital logic circuits is well suited in more advanced nanometer CMOS processes which have remarkably increased the operating speed of digital circuits with very low power and small chip area at a low-supply voltage [7, 8]. However, there is a disadvantage as well in that the on-chip operating clock speed of the SAR ADCs proportionally increases with the required resolution. The time-interleaved (T-I) and pipelined topologies can overcome this speed

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.5, OCTOBER, 2017 637

limitation in the high-resolution and high-speed SAR ADCs, while the T-I SAR ADCs suffer from performance degradation due to offset, gain, and sampling-time mismatches between channels. Some calibration schemes may be essential to minimize those channel mismatches, but the requirements for extra timing and complicated circuits make the desired system integration difficult [9-11].

One of the main reasons of performance degradation in the typical T-I SAR ADCs is an offset mismatch between channels resulting from comparator imperfection, while the offset mismatch in the typical T-I pipelined ADC is caused by residue amplifiers. The offset mismatch can be reduced with a calibration technique using tunable capacitors at the comparator output node [12], but it still needs additional calibration time and digital circuits. Even an inventive background digital calibration scheme has some disadvantage of the increased die area and power consumption due to complex calibration circuits [13].

This work proposes a 10b 160 MS/s pipelined-SAR ADC sharing various analog and digital circuits to reduce the offset mismatch between channels without any calibration as well as extra power consumption and die area. The dynamic performance of the proposed ADC is enhanced by a low-noise comparator in the SAR ADCs. The proposed ADC employs a two-channel T-I topology based on a two-step pipelined architecture of 4b and 7b in the first and second stages, respectively. The asynchronous SAR algorithm eliminates the requirement of internal high-speed clock generators. Furthermore, the first- and second-stage SAR ADCs use a common-mode voltage (VCM) based switching method [14] to remove the most significant bit (MSB) capacitor which occupies the largest area in the digital-to-analog converter (DAC) capacitor array. The second-stage 7b SAR ADCs adopt a hybrid DAC combining C and R-2R arrays to decide the last two least significant bits (LSBs), while minimizing the number of unit capacitors in the DAC for high C matching. With those circuit techniques, power consumption and die area are minimized and the required number of unit capacitors is reduced to 1/8 compared to the DAC for the conventional 7b SAR ADC.

This paper is organized as follows. The proposed ADC architecture and operation are introduced in Section II. In Section III, design issues for reducing the circuit noise

and the offset mismatch between channels are discussed, while Section IV describes the detailed circuit techniques for the proposed ADC implementation. The fabricated and measured results of the prototype ADC are summarized in Section V and the conclusion is given in Section VI.

II. PROPOSED TWO-CHANNEL T-I PIPELINED-SAR ADC

1. Architecture of the Proposed ADC The proposed two-channel T-I 10b 160 MS/s

pipelined-SAR ADC shown in Fig. 1 consists of two 4b SAR ADCs, two 7b SAR ADCs, a shared residue amplifier, a digital correction logic (DCL) block, current and voltage references (IVREFs), and a clock timing circuit.

The proposed ADC adopts an asynchronous pipelined-SAR architecture, which combines asynchronous SAR ADCs with a pipelined topology. Two channels share a single comparator and a single residue amplifier to reduce offset and gain mismatches between channels to the minimum.

The MSB capacitors in the first- and second-stage SAR ADCs are effectively removed by using the VCM-based switching method. The second-stage SAR ADCs employ a C and R-2R hybrid DAC to reduce additionally the required number of unit capacitors while deciding the last two LSBs in the DAC. Moreover, the proposed ADC is based on a range-scaling technique [15], which processes a half of the 1.2 VPP full input signal (=0.6 VPP) in the second-stage SAR ADCs, for increasing a feedback factor of the residue amplifier as much. The

Fig. 1. Proposed two-channel T-I 10b 160 MS/s pipelined-SAR ADC.

638 TAI-JI AN et al : A TWO-CHANNEL 10B 160 MS/s 28 nm CMOS ASYNCHRONOUS PIPELINED-SAR ADC WITH LOW …

IVREFs are implemented on chip for various SoC applications. Three separate reference voltage drivers for 4b and 7b SAR ADCs and a residue amplifier prevent undesirable disturbance among reference voltages due to each different switching operation. Considering a gain mismatch between channels, those reference voltage drivers are carefully implemented. Meanwhile, a timing-insensitive asynchronous SAR algorithm removes high-speed clock generators for SAR operation, and a typical meta-stability problem of comparator is removed with a very simple detection logic circuit.

2. Operation of the Proposed ADC

The timing diagram of the proposed T-I 10b 160 MS/s

pipelined-SAR ADC including sampling, SAR operation, and residue amplifying time intervals is shown in Fig. 2. The entire ADC operates at a sampling rate of 160 MS/s, while each channel operates only at 80 MS/s. The operation of each functional circuit block is briefly discussed below.

Analog input signals sampled alternately in the first-stage two 4b SAR ADCs are converted into digital codes of four MSBs by the asynchronous SAR operation during a half period of the 160 MHz clock, 3.125 ns. A residue voltage after the first-stage coarse decision is amplified only by four times through the shared residue amplifier combined with a range-scaling while the second-stage 7b SAR ADCs sample alternately the amplified residue voltage during a half period of the 80 MHz clock. During the next half period of the 80 MHz clock, the 7b SAR ADCs convert the sampled signals to digital codes of seven LSBs by asynchronous SAR operations. Finally, a 10b digital code corresponding to each sampled analog input signal is obtained at a sampling rate of 160 MS/s. On the other hand, some reference disturbance may arise

due to the SAR operations of the first and second stages during the residue amplifying period, as shown in Fig. 2. The ADC proposed in this work reduces this reference disturbance by employing three separate reference voltage drivers.

III. DESIGN ISSUES TO REDUCE CHANNEL

MISMATCH AND CIRCUIT NOISE

1. Comparator Sharing to Minimize Channel-offset Mismatch

In the conventional T-I SAR ADCs, an offset

mismatch between comparators generates non-linearity errors limiting the overall ADC performance. Many offset calibration schemes have been invented to reduce the comparator offset mismatch, but they need additional timing and digital circuits. This work proposes a comparator sharing technique between two channels to minimize the offset mismatch without any calibration. The shared comparator for the first-stage SAR ADCs and its simulated offset distribution are illustrated in Fig. 3.

The shared comparator in the first pipelined stage, as shown in Fig. 3, consists of only a two-stage latch without a preamplifier consuming a static DC current. If a comparator with a single input pair is shared alternately with switches between two channels, the charge injection from the analog series switches for channel selection and the memory effect can distort severely an amplified residue voltage transferred to the second pipelined stage. Therefore, the comparator of the first stage needs to have two differential input pairs without series switches for channel selection, preventing the distortion of a residue voltage. Such circuit configuration automatically removes the memory effect as commonly observed in the comparator with multiple input pairs.

Fig. 2. Data conversion timing diagram of the proposed ADC.

Fig. 3. Shared Comparator for the first-stage SAR ADCs.


The comparator using two differential input pairs in Fig. 3 can cause an offset mismatch between two channels, which also degrades the performance of the overall ADC. However, as long as the offset of the first-stage SAR ADCs is within a half LSB of the 4b coarse resolution, code errors can be corrected by the DCL. According to the Monte-Carlo simulation resulted from 1000 samples for comparator offset with this process, as shown on the right side of Fig. 3, the standard deviation of the comparator offset is 11.56 mV and the whole offsets are reliably distributed within 1/2 LSB of 4b (=37.5 mV). In this work, the offset mismatch caused by the two differential input pairs in the first stage is corrected by the DCL and does not affect the linearity of the overall 10b ADC.

2. Low Noise Comparator Design

In the SAR ADCs, a comparator can produce code

errors due to the internal circuit noise while determining the logic level of an input signal. The internal noise power of the comparator is represented equivalently as the input-referred noise power and the code errors of the comparator increase in proportion to the input-referred noise power [12]. In the proposed ADC, the code errors of the first-stage 4b SAR ADC caused by the offset and circuit noise are corrected by the DCL while the code errors of the second-stage 7b SAR ADC are not. As a result, the code errors of the second stage directly affect the performance of the overall pipelined-SAR ADC. The estimated signal-to-noise ratio (SNR) including the second-stage comparator noise power is expressed in Eq. (1) below.

2

10log( )

10log( )

4

S

N

S

COMPQ C A

PSNR

PP

PP P P

=

=+ + +

(1)

In Eq. (1), PS and PN are the input signal and total

ADC noise power, while PQ, PC, PA, and PCOMP are the quantization noise power, kT/C noise power, and input-referred noise power from the residue amplifier and the second-stage comparator, respectively. Those equivalent noise powers of the ADC are illustrated in Fig. 4. In the

first-stage SAR ADC, a 320 fF sampling capacitor is employed to meet a 10b requirement of kT/C noise at a 1.2 VPP input signal range, where PC is calculated to be 0.026 μV2. The kT/C noise of the second-stage SAR ADC is negligible in the overall pipelined-SAR ADC since its input-referred value is attenuated by a square of the residue amplifier gain. Based on Eq. (1) and Fig. 4, PCOMP needs to be designed below 1 μV2 to obtain the required dynamic performance of 10b ADC, where the expected SNR becomes about 58.87 dB. The comparator for the second-stage SAR ADCs is shown in Fig. 5, where the size of transistors is optimized considering the required operation speed and input-referred noise. In this design, the noise power of the comparator in the second stage is calculated as approximately 0.56 μV2.

The performance of the proposed comparator is compared with the previously reported comparators in Table 1 [16-18]. The comparator implemented in this ADC shows a relatively low or similar kick-back noise

Fig. 4. Equivalent circuit of the proposed ADC with major noise sources.

Fig. 5. Low-noise comparator for the second-stage SAR ADCs.

Table 1. Performance comparison with the previously reported comparators

[16] [17] [18] proposed Operation Speed (GHz) 3.82 4.16 4.90 5.20 Kickback Noise (mV) 4.50 5.34 3.20 2.91

Input Referred Noise (μV2) 1.00 1.96 0.64 0.56


amplitude and input-referred noise power compared with the previously reported comparators.

3. Shared Amplifier for Low Offset and Gain Mismatches

In the conventional T-I pipelined ADCs, offset and

gain mismatches are major factors degrading the overall ADC performance, mostly caused by the amplifiers in the input sample-and-hold amplifier (SHA) circuit and the first-stage multiplying DAC (MDAC) for each channel. In this work, the offset and gain matching accuracies between the residue amplifiers for two channels need to be better than a 10b resolution. However, it is not easy to design the amplifiers with a matching accuracy of at least 10b between channels without any form of calibration technique. Furthermore, the related power efficiency may be poor if each amplifier is used separately in each channel. In the proposed ADC, a single residue amplifier, as shown in Fig. 6, is shared to reduce not only the offset, gain, and bandwidth mismatches between channels but also the die area and power consumption. The shared residue amplifier has two differential input pairs which remove the memory effect of the typical amplifier-sharing techniques by guaranteeing a long enough reset time and by removing series analog switches for the unused channel.

Two differential input MOSFET pairs are turned on and off alternately by using two small-sized switches, M5 and M6, with two slightly overlapped clock phases [19], Q1MB and Q2MB, to prevent the glitch energy and settling delay occurring when two input pairs are simultaneously turned off. Usually, a high DC gain and a sufficient signal swing range tend to be limited by the

short channel effect and the low-supply voltage in the recent nanometer CMOS processes. In the first-stage amplifier of Fig. 6, a gain-boosting topology is implemented to obtain a high DC gain required for a 10b plus resolution, while the second-stage amplifier using only 5 transistors employs a differential common-source topology to achieve a high enough signal swing range. The designed residue amplifier has a loop gain of 64.6 dB and a bandwidth of 323.5 MHz to meet the required settling time. The power consumption of the residue amplifier is 2.1 mW.

IV. CIRCUIT IMPLEMENTATION

1. SAR ADCs using the Minimal Number of Capacitors

The proposed 10b ADC employs a two-step pipelined

architecture to determine 4b and 7b in each of the first- and second-stage SAR ADCs. The first- and second-stage SAR ADCs employ a VCM-based switching method, in common, which directly compares a sampled input signal with the VCM. It eliminates the largest MSB capacitor in the capacitor array of each DAC for the SAR ADCs, reducing both power consumption and die area. Each of the second-stage 7b SAR ADC needs much more unit capacitors, die area, and power consumption in comparison to the first-stage 4b SAR ADC. A two-step split-capacitor array with a small attenuation capacitor, CA, can be used to reduce the number of unit capacitors in the second-stage 7b ADC. However, a capacitor mismatch between the upper and lower arrays with the attenuation capacitor may deteriorate the performance of the SAR ADC since the CA is not the integer multiple of

Fig. 6. Shared residue amplifier with two separate differential input pairs.

Fig. 7. Hybrid DAC with C and R-2R arrays for the second-stage SAR ADC during input sampling.


unit capacitor. The proposed DAC for the second-stage SAR ADCs, as shown in Fig. 7, employs a hybrid 7b DAC combining C and R-2R arrays to decide the last 2 LSBs to minimize die area and power consumption simultaneously by reducing the number of unit capacitors considerably.

Since the VCM-based switching method directly decides the MSB by comparing a sampled input signal with the VCM, as shown in Fig. 7, the 26CU for the MSB decision in the capacitor array is removed. During the SAR operation, the bottom plates of the capacitors are switched from VCM to either VREF+ or VREF- depending on each bit decision and there is no common-mode signal variation in the comparator input. The VCM-based switching does not lead to performance degradation caused by a VCM fluctuation at the comparator input pair, while reducing the switching power dissipated in the DAC by 90% in comparison to the conventional switching method [14]. On the other hand, the previous work generating six sub-reference voltages from a single resistor string for the lower LSBs consumes some static power unnecessarily [20].

This work proposes a hybrid 7b DAC using C and R-2R arrays in the second-stage SAR ADCs to reduce static power consumption. The proposed C and R-2R based DAC operates as shown in Fig. 8. An analog input is sampled into a CU during the sampling period, Phase 1, while three inputs of the DAC are floating. The sampled input is compared to output voltages of the C and R-2R based DAC during the SAR operation, Phase 2, to decide five MSBs where three inputs of the DAC are connected to the VCM with a zero DC current. During the last two LSB decision, Phase 3, three inputs of the DAC are connected to VCM or VREF+ or VREF- depending each bit decision while a code-dependent small DC current flows. After all of the seven-bit decision, Phase 4, three inputs of the DAC are again connected to the VCM to remove a DC current of the C and R-2R based DAC. As a result, the proposed hybrid DAC minimizes undesired power consumption since it consumes a small DC current only during the last two LSB decision. With the proposed C and R-2R arrangement, the next two largest capacitors, 25CU and 24CU, in the hybrid DAC for the second-stage SAR ADC are additionally removed, as shown in Fig. 7. Employing both of the VCM-based switching scheme and the hybrid DAC, the proposed 7b SAR ADC needs only

16 unit capacitors, in contrast with the conventional full 7b SAR ADC requiring 128 unit capacitors.

Meanwhile, the second-stage SAR ADCs need either extra reference voltages or capacitors to process a half of the 1.2 VPP full input signal for range scaling. The extra reference voltages need the corresponding extra voltage drivers, increasing die area and power. In the proposed hybrid DAC for each of the second-stage SAR ADCs, only 24CU capacitors are added for the range-scaled signal processing without extra reference voltages, as shown in Fig. 7 [15]. Furthermore, the proposed two-channel DACs in each stage are laid out adjacently and symmetrically to minimize gain and sampling-time mismatches without any calibration scheme.

2. SAR ADCs based on Asynchronous Algorithm

The conventional synchronous SAR ADC requires N

times of an equal conversion cycle from the MSB to LSB decision, as shown in Fig. 9(a). A clock period for the synchronous SAR ADC is determined by dividing the overall conversion time into an equal time segment based on the longest conversion cycle among the comparator

Fig. 8. Operation of the proposed hybrid DAC employing C and R-2R arrays.

Fig. 9. Timing based on (a) synchronous, (b) asynchronous SAR algorithm.


operation, SAR digital logic delay, and DAC settling. Since the internal clock of the synchronous SAR ADC

is based on the longest conversion cycle, the idle periods between conversion time steps can appear, limiting high-speed SAR operation. On the other hand, in the asynchronous SAR algorithm, as shown in Fig. 9(b), the next conversion cycle begins at the same time as the completion of current conversion cycle, which effectively eliminates the idle periods between conversion steps and allows high-speed SAR operation. Assuming the synchronous internal clock should be used for the proposed ADC, a 1.6 GHz clock for the first-stage 4b SAR ADCs and a 1.4 GHz clock for the second-stage 7b SAR ADCs are needed. At this level of high-speed clocks, a serious synchronization problem may affect the signal accuracy and integrity of sampling, amplifying, and SAR operation with the considerably increased power consumption and die area. The proposed ADC employs an asynchronous SAR algorithm to generate the required conversion clock without a high-speed synchronous internal clock circuit.

3. Simple Meta-stability Detection Logic

In the typical asynchronous SAR ADC, the meta-

stability caused by a very small signal in the comparator input deteriorates the overall ADC performance since the comparator is unable to decide the output logic level precisely and rapidly. Some previous works employ a ramp signal generator to estimate the comparison time and to generate a flag signal when the meta-stability occurs [21, 22]. However, this scheme requires an extra estimation time and the related analog circuits.

This work proposes a simple meta-stability detection logic based on a variable delay circuit and a three-input NAND gate, as shown in Fig. 10. The variable delay circuit itself is implemented with two current-driven inverters with a control signal of CNTL, while the delay time is adjusted by off-chip control pins to confirm a robust operation.

The simulated waveforms of the proposed meta-stability detection logic are illustrated in Fig. 11. When the READY signal indicating the completion of comparator decision is not generated between the comparison signal of CKL and its delayed clock of CKL_D, the comparator output is set to a high logic level

by the META signal.

4. On-chip Separate Reference-voltage Drivers to Keep High-speed Switching Noise from the SAR ADCs

In the conventional pipelined-SAR ADCs, any form of

reference disturbance is hardly avoidable due to the high-speed switching noise from the SAR logic block during the data conversion and amplifying processes. In this ADC, the reference voltage for residue amplification requires a high accuracy of at least 10b, while that for SAR conversion in the first-stage ADC needs only a 4b accuracy. When a single reference voltage is distributed over the overall ADC, the high-speed transient switching noise coupled from the SAR block seriously affects the accuracy of reference voltages, as shown in Fig. 12(a). As a result, the proposed ADC separates the reference voltage drivers for SAR operation and residue amplification, considerably reducing the reference disturbance without any calibration, as shown in Fig. 12(b).

Fig. 10. Simple meta-stability detection logic for the proposed comparator.

Fig. 11. Simulated meta-stability detection logic.


The power dissipated in the on-chip voltage reference blocks is reduced fairly by separating only the driver circuits for the SAR and residue amplifying operation, respectively, while a gain mismatch between references is minimized by sharing the same reference generator between channels. The proposed ADC implements three reference voltages, which are composed of one reference voltage with a 10b accuracy for a shared residue amplifier and two reference voltages with 4b and 7b accuracies for two SAR sub-ADCs, respectively.

V. PROTOTYPE ADC MEASUREMENTS

The prototype 10b 160 MS/s asynchronous pipelined-SAR ADC based on a two-channel T-I topology is implemented in a 28 nm CMOS process and the prototype ADC occupies an active die area of 0.23 mm2. The layout and die photo of the prototype ADC are shown in Fig. 13, where the first- and second-stage SAR ADCs are located symmetrically around a shared 10b-accurate residue amplifier in the center. The on-chip MOS decoupling capacitance of 890 pF integrated in the clear space considerably reduces signal interference between various functional circuit blocks, electro- magnetic effect, power noise, and transient glitch energy.

An evaluation board to measure the performance of the prototype ADC is shown in Fig. 14. Separate power supplies for analog and digital circuits are used for minimizing the signal interference caused by the digital supply noise. The prototype ADC dissipates 5.6 mW with the on-chip references and 3.5 mW without the references with a sampling rate of 160 MS/s at a 1.0 V supply voltage. The measured maximum differential non-linearity (DNL) and integral non-linearity (INL) are

within 0.71 LSB and 0.70 LSB, respectively, as shown in Fig. 15.

The measured FFT spectrums at 25 MS/s and 160 MS/s with a 4 MHz sinusoidal input are shown in Fig. 16, where there is no harmonic tone at fs/2 of 25 MS/s and 160 MS/s. It means that offset and gain mismatches between two channels are effectively eliminated by various analog circuit sharing techniques.

The signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR), as illustrated in Fig.

(a)

(b)

Fig. 12. On-chip references using (a) a single driver, (b) separate drivers.

Fig. 13. Layout and die photo of the prototype 10b 160 MS/s 28nm CMOS ADC.

Fig. 14. Evaluation board for the prototype ADC.

Fig. 15. Measured DNL and INL of the prototype ADC.


17(a), are measured with the sampling rates ranging from 40 MS/s to 160 MS/s at a differential input frequency of 4 MHz. The SNDR and SFDR are maintained above 51.43 dB and 62.01 dB up to 160 MS/s. The SNDR and SFDR variations of the prototype ADC are measured in Fig. 17(b), where input frequencies are increased from 4 MHz to 100 MHz at a sampling rate of 160 MS/s. The SNDR and SFDR are maintained above 51.07 dB and

60.94 dB up to the Nyquist input frequency, while the -3 dB effective resolution bandwidth (ERBW) is measured to 100 MHz. The performance of the prototype ADC is summarized in Table 2 and the performances of previously reported T-I ADCs are compared in Table 3. The prototype ADC maintains a SNDR of 51.1 dB at the Nyquist rate without any calibration and shows a figure of merit (FoM) comparable to the other T-I ADCs.

VI. CONCLUSION

This work proposes a 10b 160 MS/s pipelined-SAR ADC based on a dual-channel T-I topology, minimizing the circuit noise and the offset mismatch between channels without any calibration. The proposed ADC employs a comparator sharing technique between two channels to reduce the offset mismatch, power consumption, and die area. A single residue amplifier is

(a)

(b)

Fig. 16. Measured FFT spectrum of the prototype ADC at (a) fs=25 MS/s, (b) fs=160 MS/s (1/7 fs down sampled in (b)).

(a)

(b)

Fig. 17. Measured SNDR and SFDR of the ADC with (a) fs, (b) fin.

Table 2. Performance summary of the prototype ADC

Process Samsung 28 nm CMOS Supply 1.0 V

Resolution 10 bits Input Range 1.2 VPP (differential)

DNL -0.71 LSB ≤ DNL ≤ +0.70 LSB INL -0.70 LSB ≤ INL ≤ +0.66 LSB

Speed 160 MS/s 51.43 dB (@fin=4 MHz)

SNDR 51.07 dB (@fin=80 MHz) 62.01 dB (@fin=4 MHz)

SFDR 60.94 dB (@fin=80 MHz)

without IVREFs with IVREFs ADC Core Power

3.5 mW 5.6 mW FoM (fJ/Conv.-Step) 74.4 119.0

Active Die Area 0.23 mm2

Table 3. Performance comparison with the previous reported T-I ADCs

[11] [23] [24] [25] This work

Resolution [bits] 10 10 10 11 10 Speed [MS/s] 170 160 120 150 160 Supply [V] 1.0 1.1 1.1 1.2 1.0

Power [mW] 2.30* 2.72* 8.80* 46.80** 3.5* FoM (fJ/Conv.) 40.9 51.0 286.5 1493.3 74.4

Area [mm2] 0.10 0.21 0.38 2.42 0.23 Calibration O O X X X SNDR [dB] (@ Nyquist) 53.2 52.2 49.9 48.5 51.1

Process [CMOS] 65 nm 65 nm 45 nm 130 nm 28 nm

(*: without IVREFs, **: with IVREFs)


also shared between two channels to solve simultaneously the offset, gain, and bandwidth mismatches. The second-stage 7b SAR ADCs are based on a hybrid DAC using C and R-2R arrays to decide the last two LSBs, minimizing power consumption and die area by reducing the number of unit capacitors. The asynchronous SAR algorithm eliminates the need for a high-speed internal clock generator as observed in the common synchronous SAR type ADCs. Three separate reference voltage drivers for three critical circuit blocks of 4b and 7b SAR ADCs and a single residue amplifier relieve the undesirable disturbance among reference voltages due to different high-speed switching operation. The prototype ADC in a 28 nm CMOS technology occupies an active die area of 0.23 mm2. The ADC demonstrates a measured DNL and INL within 0.70 LSB and 0.71 LSB, with a maximum SNDR and SFDR of 51.43 dB and 62.01 dB at 160 MS/s, respectively. The power consumption of the prototype ADC is 5.6 mW including an on-chip reference generator and voltage drivers, at 160 MS/s with a 1.0 V supply voltage.

ACKNOWLEDGMENTS

This work was supported by Samsung Electronics, the Sogang University Research Grant 201619059, and the IDEC of KAIST.

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Tai-Ji An received the B.S. degree in electronic engineering from Univer- sity of Seoul, Korea, in 2007, and the M.S. degree in electronic engineering from Sogang University, Korea, in 2013. From 2007 to 2011, he was with Luxen Technologies, where he

had developed various power-management and analog integrated circuits. He has been in the Ph.D. program at Sogang University since 2013. He is a full scholarship student supported by Samsung electronics. His current interests are in the design of high-resolution low-power CMOS data converters, PMICs, display driver ICs, and very high-speed mixed-mode integrated systems.

Young-Sea Cho received the B.S. and M.S. degrees in electronic engineering from Sogang University, Korea, in 2014 and 2016, respectively. He is now with Samsung Electronics, Korea. His current interests are in the design of high-

resolution low-power CMOS data converters, PMICs, and very high-speed mixed-mode integrated systems.

Jun-Sang Park received the B.S. and M.S. degrees in electronic engineering from Sogang University, Seoul, Korea, in 2012 and 2014, respectively, where he is currently pursuing the Ph.D. degree. He is a recipient of a five-year full scholar-

ship sponsored by Samsung electronics. His current interests are in the design of high-resolution low-power CMOS data converters, PMICs, and very high-speed mixed-mode integrated systems.


Gil-Cho Ahn received the B.S. and M.S. degrees in electronic engineering from Sogang University, Seoul, Korea, in 1994 and 1996, respectively, and the Ph.D. degree in electrical engineering from Oregon State University, Corvallis, in 2005.

From 1996 to 2001, he was a Design Engineer at Samsung Electronics, Kiheung, Korea, working on mixed analog-digital integrated circuits. From 2005 to 2008, he was with Broadcom Corporation, Irvine, CA, working on AFE for digital TV. Currently, he is an Associate Professor in the Department of Electronic Engineering, Sogang University. His research interests include high-speed, high-resolution data converters and low-voltage, low-power mixed-signal circuits design.

Seung-Hoon Lee received the B.S. and M.S. degrees in electronic engineering from Seoul National University, Korea, in 1984 and 1986, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois,

Urbana-Champaign, in 1991. He was with Analog Devices Semiconductor, Wilmington, MA, from 1990 to 1993, as a Senior Design Engineer. Since 1993, he has been with the Department of Electronic Engineering, Sogang University, Seoul, where he is currently a Professor. His current research interests include design and testing of high-resolution high-speed CMOS data converters, CMOS communication circuits, integrated sensors, and mixed-mode integrated systems. Dr. Lee has been a member of the editorial board and the technical program committee of many international and domestic journals and conferences including the IEEK Journal of Semiconductor Devices, Circuits, and Systems, the IEICE Transactions on Electronics, and the IEEE Symposium on VLSI Circuits. Since 2006, he has been organizing various industry-university mutual cooperative programs with many companies such as Samsung Electronics, SK Hynix, and LG Electronics. In 2010, he founded Analog IP Research Center supported by the Ministry of Science, ICT&Future Planning, Korea.

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