182 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-19, NO. 2, FEBRUARY 1972

A Three Mask. Bipolar Integrated Circui:t Structure

JTNCE bJT J. GLINSKI

Abstract-A new bipolar integrated circuit structure has Imen fabricated that compares favorably to the MOS structure in ternla of fabrication simplicity and performance. The new structure is basi’:a~lly a modified isolated lateral transistor and requires only three photo- lithographic masking operations up to and including first levd of metalization.

The fabrication of the structure is as follows: a shallow :Imn- selective p-type base region is diffused into a lightly doped p-ype substrate; n+ emitter and collector regions are then simultaneo sly and selectively diffused intoand through the p-type base region thus forming a lateral n-p-n transistor. The second and third masks define the contact holes and the metalization pattern, respectively.

Lateral isolation of the structure is obtained by encircling the emitter and base regions with the collector region. Vertical isola: ion is achieved by the large collector-depletion region that extends bse- neath the emitter and base regions. Since the substrate is 1iglu:ly doped a low collector voltage will adequately isolate the emitter itnd base regions from adjacent devices.

The new technology permits the fabrication of transistors, re- sistors, and crossunders. Transistors with 2- to 3 - 0 spacings O C C I L ] ? ~

500 Mm2 of silicon area and have the following charactsrist:ir,s: @=35, peakft=0.1 GHz at 0.5 mA, BV(SUSTAIN)=3 to 5 V, t ,= 20 ns, tf = 120 ns, t , =20 ns. Resistors with values as high as 40 k P htwe been fabricated within 600 m2. Active nonlinear loads with effective resistance up to 200 kQ have been fabricated.

TTL gates have been made with power-delay products of 3.6 ,,J, and propagation delays of 34 ns.

1 I. INTRODUCTION

N recent years, new bipolar integrated circuit strcc- tures have been proposed and fabricated [l]-[.ii 1. These structures offer high packing density, simpli-

fied fabrication, and reasonable power-delay produc~ 5,. The new bipolar structure described in this paper allo7,rs complete integrated circuits to be made up to and i.1- cluding the first layer of metalization with only thr1:e: photolithographic masking operations. Packing densi 117

capabilities similar to those attainable using collecto1.- diffusion isolation [ 2 ] are obtained with the new stru1:- ture. Transistors with ft values between 30-100 MHz are obtainable using this approach and these are qui1 e adequate for the submilliwatt circuits for which the a] I ” .

proach is intended.

11. DESCRIPTIOK OF THE INTEGRATED CIRCUIT TRAKSISTOR

The new structure is basically a modified isolatej, lateral transistor [6]. Fig. 1 shows the cross-section::l view of the tri-mask or TRIM transistor. Lateral isola-

Manuscript received October 30, 1970; revised August 25, 1971,

Hill, N. J . 07974. He is now a t 1028 Martinstein Ave., Bay Short, The author was with Bell Telephone Laboratories, Inc., Murra q

N. U. 11706.

Fig. 1. TRIM transistor.

Fig. 2. TRIM transistor where the emitter region is 4- by 8-Mrn and spacing between emitter and collector is 3 pm.

tion of the transistor is obtained by encircling the emit- ter and base region with the collector region. The sur- face-collector junction is always reverse biased because the surface is grounded and the collector voltage is never below Vsat. Since the substrate is lightly doped, a low collector voltage will provide a relatively large depletion region which in turn adequately isolates the emitter and base regions from the substrate. Experiments show that the reverse biased surface-collector junction has a large enough depletion region to collect minority carriers in the base which try to escape the vicinity of the tran- sistor. Experiments also show that base current to ground (substrate or surface) reduces the extrinsic gain by an acceptably small amount as discussed in Sec- tion IV.

Fig. 2 shows a microphotograph of the TRIM tran- sistor. The circular metalization pattern labeled S con- tacts the surface through the square hole in the oxide. The emitter, base, and collector are designated E , B , and C in Fig. 2. The emitter is of reregistered type, and

GLINSKI: THREE MASK BIPOLAR IC STRUCTURE 183

I I I I I I l l 1 I I I I I l l l l .01 I I

IC ( m A t

Fig. 3 . f l versus IC for various VC.

its contact hole is etched simultaneously with the col- lector and base contact holes. The collector region en- circles the emitter aad base region and is dark gray in color. The transistor occupies less than 500 pm2 of silicon area.

111. FA4BKlCATION OF T H E T R I n l TRANSISTOR The fabrication of the TRIM transistor is as follows:

a shallow (0.5 pm) nonselective p-type base region is diffused into a lightly doped (500-1000 Q.cm) p-type substrate; a 3000-8L steam oxide is grown a t 950°C; the first mask now defines the emitter and collector regions; n+ emitter and collector regions are now simultaneously diffused through the p-type base region t o a depth of 1 pm; all of the silicon oxide is removed and a 3000-.& steam oxide is grown ; the second mask now defines the reregistered emitter, reregistered collector, base, and surface contact holes; metal is now evaporated over the entire slice and the third mask is used to define the met- alization pattern. Fabrication details are in the Ap- pendix.

Various fabrication procedures were tried but the above procedure gave the best results. The nonselective p-type base diffusion used in the above fabrication procedure inhibits surface inversion, suppresses lateral injection (near the surface) from the emitter, and pro- vides a field that inhibits surface recombination. It is also used for resistors,

Iv . ELECTRICAL CHARACTERISTICS O F THE

T R I 14 TKXNSI!jTOH

The gain of a T R I M transistor varies with collector current, collector voltage, and emitter-collector separa- tion. Fig. 3 shows p versus IC a t various Vc for a given 3-pm emitter-collector separation. Notice that /3 in- creases with increasing collector voltages and decreasing collector current. When the collector voltage increases, the depletion region widens, thereby narrowing the base region and increasing the gain [7] . Also, as collector cur- rent increases, conductivity modulation of the lightly doped base causes a reduction in gain [SI.

Fig. 4 shows the dependence of /3 on emitter-collector separation, holding collector voltage and current con- s t an t a t 1 V and 0.5 mA. The data was taken from transistors with 1.1 pm deep emitter-collector diffusions and 0.5 pm deep p-type base diffusion. The substrate resistivities ranged from 500 to 1000 Se.cm. The separa- tion distance quoted in the figure is the separation dis- tance between emitter and collector on the photolitho- graphic masks. This figure indicates that reasonable current gain can be obtained from transistors with 8-pm emitter-collector separations.

Fig. 5 shows the IC versus V , characteristics of a T R I M transistor with a 3-pm emitter-collector separa- tion. Notice that without any base drive (lowest curve) there is space-charge limited current due to punch

184 IEEE TRANSACTIONS ON ELECTRON DEVICES, FEBRUARY 1972

Fig. C

.97

.96

.95 '

a

.94 .

.93 t I I

2 4 6 a

B =12 ,92

p SEPARATION

4. Gain versus emitter-collector separation. 1.l-pm emit1 *ollector diffusion, 500-1000-0/Op diffusion, 500-1000-n ' cm

. -r-

Fig. 6. TRIM transistor geometry.

substrate.

Fig. 7. TRIM transistor switching waveforms. 1.6-V power supply,

horizontal, 2.7-kn load resistor, 2.7-kn series input resistor. 0.4-V/div input waveform, 0.4-Vldiv output waveform, 50-nsjdiv

TABLE I T R I M TRANSISTOR SWITCHING CHARACTERISTICS'

Emitter- Collector 1000 n

Input and Output Resistors

Fig. 5 . TRIM transistor, IC versus Vc, 3-km spacing. O.'l-V/div horizontal, 0.1-mA/div vertical, 0.005-mAjstep.

through between the emitter and collector. This curren : is 0.1 mA a t 2 V and can be reduced by decreasing thi: sheet resistance of p-type base diffusion or by increasing; the emitter-collector spacing. Both approaches give lower but still adequate gain. Fig. 6 shows the TRII\:I transistor geometry in detail.

The switching waveforms of the TRIM transistor ( 3 pm) in a common emitter configuration are shown in Fig. 7. The circuit has a 2.7-kQ load resistor and a 2.7-l<Q series input resistor. The two horizontal lines are voltage reference lines; the lower line is 0 V and the upper line is approximately 1.6 1 7 . Notice that the col., lector voltage does not equal the power supply voltage when the transistor base current is zero. This lower col- lector voltage is due to the space-charge limited current. The transistor also exhibits long rise and fall times as shown in Fig. 7. This is probably due to the stored charge in the very wide base region that must be swept out before the transistor can turn off. Table I shows switching waveform data for TRIhI transistors with

4 6 8

30 44 75

16 10

20

56 66 66

10 000 D 4

Input and Output Resistors

6 86 40 8 140 50

50 20 168 150 200

of 2.6 pF. The turnon delay was less than 10 ns in all of the above a Usinga common emitter configuration and a probe capacitance

measurements.

various emitter-collector separations and various series input and load resistors. Measurements were made with the transistor in the common emitter configuration.

Fig. 8 shows the variation of ft with increasing IE. Peak ft occurs a t approximately 0.5 mA and decreases rapidly with increasing or decreasing I#. The geometry of the two devices measured is shown in Figs. 2 and 6 (present geometry). The TTL gates to be discussed later in this paper used this transistor at an average operating current of less than 0.1 mA.

Table I1 shows the dependence of peakf t (MHz) on emitter to collector separation. This table indicates that the 8-,urn geometry has adequatef, and current handling

GLINSKI: THREE MASK BIPOLAR IC STRUCTURE

l o - ' IO- IE (AMPS)

Fig. 8. !T versus IE a t Vcs=2V.

TABLE I1 TRIhI TRANSISTOR FREQUENCY RESPOUSE

Emitter-

V C

3 100 4 90

2

6 40 0 .1 2 2

8 30 0.05 2

0 .5 0 .2

TABLE I11 INTERACTION OF T W O ADJACENT TRIM TRANSISTORS

Collector- Collector Collector

Current Q 2 Collector

Ratio of

Separation Current Q1 With Vc1 = 0 Collector

(rm) I C 1

b.4) (mA) IC2 Currents

I C J I C ,

6 1.0 0.007 11

143 1 . 2 0,005 240

capabilities to be useful in the static bipolar shift register which is proposed later.

The interaction of two adjacent TRIhl transistors is shown in Table 111. Two TRIM transistors (identical to the one shown in Fig. 2) were fabricated with a collector- collector separation of 6 pm. The first transistor Q1 is operated in the common emitter configuration with a collector current of 1 mA and a collector voltage of 2 V. The collector of Q1 is now grounded and a voltage of 2 V is applied to the collector of Qz. The current collected by the collector of Qz is 0.007 mA, or less than 1 percent

185

of the current collected by the collector of Q1 with a 2-V bias. This experiment shows that TRIM transistors are adequately isolated with a collector-collector separation of 6 pm. Results are also shown for an 11-pm separation.

V. RESISTORS FABRICATED USING THE T R I M TECHNOLOGY

Resistors may be fabricated in a number of ways us- ing the TRIM technology. Low-value self-isolating re- sistors (R<lOO a) may be formed using a diffused emitter region (Rs = 15 a/u). Medium value resistors (100 a < R < 20 kQ) may be formed in the nonselectively diffused region. Resistors made this way must have an encircling collector region to provide lateral isolation for the resistor as shown in Fig. 9. T o provide vertical isola- tion, the collector region must be: positively biased so that the depletion region closes on itself' below the re- sistor. High-value self-isolating, nonlinear resistors (10 ka <R <200 kQ) may be obtained by using the space-charge limited current present in transistors. In fact, if a sufficient negative bias ( - 2 V) is applied to the base of the TRIM transistor, the space-,charge limited current flowing between emitter and collector can be re- duced to under 10 p A . Hence, by fabricating a T R I M transistor with 3- or 4-pm separation distance and applying negative bias to the base, we can obtain an active nonlinear load.

Figs. 9 and 10 show two versions of the space-charge limited resistor. Fig. 9 shows the simple space-charge limited resistor fabricated from two emitter diffusions a certain distance apart (3 or 4 Hm). Fig. 10 shows a con-

186 JEEE TRANSACTIONS ON ELECTRON DEVICES, FEBRUARY 1972

DEPLETION RE610N EPLETIOH REGION

.i P TYPE SUBSTRATE

(a> (b ) Fiq. 9. (a) Resistor, ( I ) Space-charge limited resistor.

OEPLEllOW IIEI:IOW

P- TYPE SUBSTRATE

Fig. 10. Controllahi ? space-charge limited resistor.

Fig. 11. Controllable space-charge limited resistor with 3-pm spacing between electrodes.

trollable space-charge limited resistor with the c o n t : d electrode placed between the two n+ regions. When a negative bias is applied to the control electrode, 1 he space-charge limited current flowing between the ' e -

sistor electrodes decreases substantially. Fig. l l show:; a microphotographof the controllable space-charge 1imii.ed resistor. The resistor electrodes are 50 pm long and 2 /..;n wide and are spaced 3 pm apart. The control electrode is shown in the upper right section of the figure. The three short metalization stripes signify that the spaci r~g of resistor electrodes is 3 pm.

Fig. 12 shows the IC characteristics of the contro1,led space-charge limited resistor (CSCLR) shown in Fig. ' 1. In Fig. 12(a) the negative voltage steps (-0.2 V/stc:p) are applied to the control electrode. The effective -1:-

sistance increases from 7.7 kQ to approximately 70 as the applied negative voltage increases from 0 V 'to -2.8 V. Fig. 12(b) shows the CSCLR operated ir- a

( b ) Fig. 12. Controlled space-charge limited resistor, 3-pm spacing,

SO pm long. 0.1-mA/div vertical, 0.2-V/div horizontal. (a) -0.2-V/step base. (b) O.OS-mA/step base.

normal transistor mode (positive current steps applied to the base).

I t should be noted that the resistance value of the CSCLR with the control electrode a t 0 V will vary sig- nificantly with the radius of curvature of either resistor electrode and the separation distance between the electrodes.

Fig. 13(a) shows the output of a CSCLR operated in a

GLINSKI: THREE MASK BIPOLAR IC STRUCTURE 187

u t v ++

INPUT

DEPLfWW RE6Y)W

P TYPE SUBSTRATE

Fig. 14. Crossunder.

+ SUPPLY VOLTPGF:

P

O U T P U i

(b) Fig. 15. Crossunder with 6-pm isolation spacing. Fig. 13. (a) Controllable space-charge limited resistor switching

waveforms. 1.6-V power supply. 0.4-V/div input waveform, 0.4- V/div output waveform, 2.7-kQ load resistor, jO-ns/div horizontal. (b) CSCLR in a common emitter configuration where the emitter and collector are formed with n+ regions that are 50 pm long and 2 pm wide and are spaced 3 prn apart. The surface contact was used as a base contact in this experiment.

“common emitter configuration” as shown in Fig. 13(b). A standard 2.7-kQ resistor is used as a load. The input waveform varies from 0 V t o -1.2 V, thereby tending to turn off the CSCLR and increasing the “collector” voltage. The resistance of the CSCLR increases from 6 to 14 kQ in this experiment. Greater differences can be obtained by using a larger negative drive voltage. The purpose of this figure is to show that this type of device will operate above 3 MHz; which is a high enough fre- quency, for example, in shift register circuits.

VI. CROSSUNDERS FABRICATED WITH

THE T R I 111 TECHNOLOGY Crossunders may be fabricated by using a diffused

emitter region (Rs = 15 Q/ 0) as shown in Fig. 14. The main disadvantage of using this type of crossunder is the space-charge limited current to any other n+ region in the vicinity of the crossunder. Fig. 15 shows a cross- under and two other n+ regions. The crossunder is the middle dark gray stripe and is 4- by 20-pm. The outer stripes are 4- by 44-pm, and the separation distance between the stripes is 6 pm. The metalization on the extreme right contacts the surface and is used as a con- trol electrode or base contact. The metalization on the extreme left contacts the two long stripes and is used as a collector contact. The crossunder is used as an emitter.

(b) Fig. 16. Crossunder with 20 pm long emitter, 2 4 4 pm long c01-

lectors, O.OOl-rn.A/step base, 0.01-mA/div vertical, 0.2-V/div horizontal. (a) 6-pm spacing. (b) 8-pm spacing.

Fig. 16 shows the transistor characteristics derived from the crossunder in a common emitter configuration with stripe separation distances of 6 and 8 pm. Notice that the gain and the space-charge limited current decreased with increased separation between emitter and collector stripes.

3 88 IEEE TRANSACTIONS ON ELECTRON DEVICES, FEBRUARY 1972

Vcc COLLECTOR BASE EMITTER COLLECTOR “cc

m OEPLETION RE610N

P TYPE SUBSTRATE

Fig. 17. TRIM transistor with a space-charge limited resistor used as a load.

tVR Vcc COLLECTOR BASE EMlTTER COLLECTOR VR Vcc

DEPLETION REGION

P TYPE SUBSTRATE

Fig. 18. TRIM transistor with a controllable space- charge limited resistor used as a load.

Fig. 19, TRIM transistor with controllable space- charge limited resistor used as a load.

VII. FUNCTIONAL INTEGRATION OF SCLR AND CSCLR INTO THE COLLECTOR OF A T R I M

TRANSISTOR Small area space-charge limited resistors and C O I ~

trolled space-charge limited resistors may be functior: I

ally integrated into the collector of a T R I M transistcr as shown in Figs. 17 and 18. Fig. 19 shows a TRlF.1 transistor with an encircling n+ diffusion. The nf di I - fusion is one of the resistor electrodes; the collector c E the transistor is the other resistor electrode. I t shouYll be noted that the resistor electrode does not have t1 encircle the transistor. The emitter-collector separa- tion is 3 pm, and the collector-resistor electrode is 3 p m S The ratio of the resistor width to the emitter-collectcr gap width is approximately 7 : 1. The ratio of space- charge limited current of the resistor to the space-

charge limited current of the transistor was only 1: 2.7 for the same applied voltage. This low current ratio is due to the small radius of curvature of the emitter- collector gap compared to the larger radius of curvature of the resistor electrodes. T h e highest collector voltage obtained was 0.47 V with a 1.6-V power supply and the emitter and base grounded. This low collector voltage is due to the nonlinearity of the SCLR and can be im- proved substantially by changing the geometry of the transistor and resistor.

VIII. T T L GATES FABRICATED WITH THE T R I M TECHNOLOGY

Transistor-transistor logic gates have been fabri- cated using T R I M transistor (3 pm) and the simple resistors shown in Fig. 9(a). Fig. 20 shows the schematic diagram of the resistor modified TTL gate that has been described in the literature [1]-[3]. All resistors in the circuit are identical in value and approximately equal to 15 kL?. A TTL ga te is shown in Fig. 21. There are six external metalization patterns in the figure. Starting from the circular metalization pattern and proceeding clockwise, the purposes of the patterns are as follows: the circular pad contacts the surface which is maintained a t ground potential; the second pad contacts an emitter on the input transistor; the third pad contacts the emitter on the output transistor; the fourth pad contacts the collector of the output tran- sistor; the fifth pad contacts the nf region which de- fines the resistors; and the sixth pad contacts both R1 and R3.

Metalization pads 1 and 3 are grounded externally. Pads 5 and 6 are externally connected to the positive power supply (1.6 V). Fig. 22 shows the switching waveforms for the gate with the input signal applied to pad 2 and the output waveform obtained from pad 4. The gate exhibits a power-delay product of 3.4 pJ with a power consumption of less than 0.12 mW in this experiment.

Fig. 23 shows the output waveform of three T T L gates in ring oscillator configuration. The period of oscillation is 167 ns with a power consumption of 0.134 mW per gate. The power-delay product is 3.7 pJ.

The above measurements were made on TTL gates with 2- to 3-pm mask tolerances. If 4- to 6p-m tolerances are used then the switching data given for individual transistors indicates that the delay would increase to approximately 100 ns a t this power level.

]x. FABRICATION COMPARISON O F VARIOUS IC STRUCTURES

Table IV compares the various IC structures with respect to the number of masks and the number of processing steps required to fabricate the structures. This comparison does not include cleaning steps or raw material handling. The comparison starts with polished substrates and ends with the complete fabrication in- clusive of the first layer of metalization.

GLINSKI: THREE MASK BIPOLAR IC STRUCTUFU2

POSITIVE SUPPLY

VOLTAGE

P

189

LNPUTS

GROUND

Fig. 20. Resistor-modified TTL gate. Fig. 2 1 . Transistor-transistor logic gate where

area is approximately 3000 pm?

TABLE IV FABRICATION COMPARISON OF VARIOUS IC STRUCTURES

Structure Number of

Number of

Masks Processing

SteDs

TRIM

SIGFET IGFET

BDI (4) BDI ( 5 ) CDI SBC

1 1 13 15 15 19 20 21

X. CONCLUSION I t has been shown that the T R I M technology offers

extreme simplicity of fabrication-high densities- together with bipolar advantages of reproducible low threshold and high transconductance. Transistors with ft values between 30-100 MHz are obtainable using this approach and these are quite adequate for the submilli- watt circuits for which the approach is intended.

APPENDIX FABRICATION OF T R I M INTEGRATED CIRCUITS

Fabrication of T R I M integrated circuits starts with

After the wafer is initially cleaned, boron is non- a 1000-Q~cm syton-polished p-type silicon wafer.

selectively diffused for one hour a t 930°C in a Nz-02 ambient flow. This time and temperature results in a boron sheet resistance of approximately 500 Q/O and a boron depth less than 1 pm.

The wafer is then cleaned and a 3000 steam oxide is grown ( 2 5 min a t 950°C). The first mask is now used in a standard photoresist process to simultaneously define the collector and emitter areas. After etching the defined areas, an n+ phosph.orous region is diffused at 950°C. Diffusion times, typically 40 to 80 min, are long enough to insure that the collector and emitter depths are greater than the depth of the boron diffusion previously completed.

All of the silicon dioxide is now removed from the slice. A 3000-w oxide is grown on the wafer in the identi-

190 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-19, NO. 2, FEBRUARY 1972

cal manner that the first oxide was grown. This n e w oxide grows faster over the n+ diffused regions thereby delineating these regions from the boron regions making the next photoresist process possible.

The second mask is used to photolithographica.lly define the collector, emitter, base, and surface cont;.ct areas. After etching these areas, 400 J! of platinum is sputtered on the slice and sintered into the etch-d areas. This is followed by the etching away of the u r \ -

sintered platinum and the evaporation of 300 A of titanium and 2000 A of aluminum over the entire waf[:l-.

The third and final mask is used next in the phol o- resist process to define the desired metalization pattern,. The unwanted aluminum and titanium are now etch1:d away.

ACKNOWLEDGMENT

’The author wishes to express his appreciation for the efforts of J. A. O’Sullivan in the fabrication of tl c:

circuits and to B. T. Murphy and J. E. Iwersen for their many helpful discussions.

REFERENCES [l] B. T. Murphy and V. J. Glinski, “Transistor-transistor logic with

gain,” IEEE J . Solid-State Civczlits, vol. SC-3, pp. 261-267, high packing density and optimum performance a t high inverse

1.21 B. T. Murph V. J . Glinski, P. A. Gary, and R . A. Pedersen, Sept. 1968.

vol. 57, pp. 1523-1527, Sept. 1969. “Co!lector d iks ion isolated integrated circuits, Proc. 1% EE,

131 V. J . Glinski and B. T. Murphy, “Bipolar integrated circuits formed in P-type epitaxial layers,” presented a t the Int. Electron

[4] T. Makimoto, ”I illaki, and K. Sugawara, Self-isolated bipolar Devices Meeting, Washington, D. C., Oct.111968, Paper 3.3.

transistors in integrated circuits, presented at the Int. Electron Devices Meeting, Washington, D. C., Oct. 1968, Papzr 3.2.

[5 ] B. T. Murphy, S. M. Neville, and R. A. Pedersen, Simplified hipolar technology and its application to systems,” IEEE J .

[6] H. C. Lin, T. B. Tan, G. Y . Chang, B. Van der Leest, and Solid-State Circuits, vol. SC-5, pp. 7-14, Feb. 1970.

N. Formigoni, “Lateral complementary transistor structure for

vol. 52, pp. 1491-1495, Dec. 1964. the simultaneous fabrication of functional blocks,” Proc. IEEE,

[7] J. M. Early, “Effects of space-charge layer widening in junction

[8] R. N. Hall, “Power rectifiers and transistors, ’’ Proc. IRE, vol. 40, transistors,” Proc. IRE, vol. 40, pp. 1401-1406, Nov. 1952.

pp. 1512-1518, NOV. 1952.

Yield Degradation of Integrated Circuits Due to Spot Defects

Abstract-Economy of integrated circuit fabrication in the pres:- ence of quasi-randomly distributed spot defects is described. Til? distribution of the defects is represented in terms of density ant1 modeled as follows : 1) they are randomly distributed within a limited area; 2) the density in a wafer changes concentrically; and 3) tho density is normally distributed from wafer to wafer with unifornt deviation throughout a wafer. The yield degradation phenomeno:ri due to such defects has been analyzed using a computer simulatio~:~. technique. The effect of density variations in a wafer and betweel:. wafers has been mainly investigated. An extensive numerical stud:!. leads to the following conclusions.

1) The deviation of the yield versus chip-area relation from thlr simple exponential law is influenced more greatly by the nonuniforn: defect distribution in a wafer than by the density variation betweer wafers.

2) The increase of average yield due to the density variatior: between wafers is sometimes offset by the decrease of the accurac:, in yield prediction. Process stabilization is essential for the ecm nomical production of a few large-scale chips.

I. INTRODUCTION N SEMICONDUCTOR integrated circuits, where defective components can be neither trimmed nor exchanged or a faultless process can never be

expected, yield is one of the most essential design

IC Manuscript received June 2,1971; revised September 2, 1971. The author is with Nippon Electric Company, Ltd., Kawasaki,

Japan.

criteria. There are two approaches to cope with the yield problem: one is to improve fabrication processes themselves and the other is to design devices so that the yield is less affected by the defects. The first step for the latter approach is to establish a method to predict the yield accurately.

Yield degradation phenomena of integrated circuits can be classified broadly into two modes: 1) structure failure due to area, line, or spot defects, and 2) per- formance failure due to spread in process parameters. This paper is concerned with the yield prediction of integrated circuits in the presence of the first failure mode due to spot defects, which usually exceeds the others in number. Spot defects, such as pinholes in photoetching processes and crystal defects, cause local damage to the device structure. This kind of failure is, in most cases, detected by the functional characteristic test.

In the simplified case, the distribution of defects has been assumed to be random and uniform all over the wafer surface [1]-[3]. I t has been pointed out, however, that this assumption is not always realistic [4]-[7]. The discrepancy between the simple theory and observed results has been accounted for as being due to the clustering of defects in a wafer [ 6 ] , [S] and