A TEACHING-FOCUSED RISC-V ESIGN IN CHISEL · DINO CPU A suite of RISC-V CPU designs Single cycle...
Transcript of A TEACHING-FOCUSED RISC-V ESIGN IN CHISEL · DINO CPU A suite of RISC-V CPU designs Single cycle...
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DINO CPUA TEACHING-FOCUSED
RISC-VDESIGN IN CHISEL
Jason Lowe-Power
Christopher Nitta
@JasonLowePower
https://github.com/jlpteaching/dinocpu
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DINO CPU
A suite of RISC-V CPU designsSingle cycleFive stage pipeline
+ Branch predictor
All designs can run rv32i code compiled with mainline GCC
A set of assignmentsOne for each design
Tools for classroom useChisel developmentAuto grading
Open sourcehttps://github.com/jlpteaching/dinocpu
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Open source hardware construction language
Embedded in Scala
Main benefit: Parameterizable
Used in industry: SiFive, Google, IBM, others…
https://chisel.eecs.berkeley.edu/
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Why Chisel?Vs Logisim
From an evaluation:
“I hate Logisim with a passion”
Scaling designs difficult
Grading time consuming
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Why Chisel?Vs Verilog
More modular design
Built-in unit tests + easy to add auto grading
Scala-basedMore familiar (to me)
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DINO CPU Design
Closely follows Patterson and Hennessy’s textbook’s design
Simple and modularNot fast, small, synthesizable
Complete-ishHide complexity when possible
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DINO CPU Assignment 1: R-types
Step 1: Logic for ALU control
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DINO CPU Assignment 1: R-types
Step 1: Logic for ALU control
Step 2: Draw R-type circuitBefore implementation!
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DINO CPU Assignment 1: R-types
Step 1: Logic for ALU control
Step 2: Draw R-type circuitBefore implementation!
Step 3: Write Chisel
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DINO CPU Assignment 2: Single-cycle
Given diagram:
Implement control
Wire control lines
Wire whole datapath
Assignment takes one instruction type at a time
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DINO CPU Assignment 3: Pipelined
Significant increase in complexity
Define all pipeline registers
Implement hazard and forwarding logic
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DINO CPU Assignment 4: Branch prediction
Extensions!We chose branchprediction
We updated pipeline
Students implemented two predictors
Ran benchmarks and compared results
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Tools included
Singularity containerMany dependenciesSafe and secure
Gradescope scriptsAutograder
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Open source
Everything on GitHubhttps://github.com/jlpteaching/dinocpu
Assignments
Documentation
Source code
Tools
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Future Improvements
Main feedback: Need better debugging
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< 5 5 - 10 10 - 20 > 20
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Hours
"How much time did this assignment take?"
WQ L2 SQ L2
WQ L3 SQ L3
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Future Improvements
Main feedback: Need better debugging
More RISC-V supportPrivileged ISA for machine-mode rv32i (e.g., for embedded)
More assignmentsNon combinational memory + cacheMulti-issue?
Open source community!
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Questions/Comments?
Thanks to:
Students of ECS154B WQ19
Jared Barocsi, Filipe Eduardo Borges, Nima Ganjehloo,
Daniel Grau, Markus Hankins, and Justin
Perona