A Systematic Study of Rare-Earth Oxide for Charged Defect ...
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Doctor thesis 2011 A Systematic Study of Rare-Earth Oxide for Charged Defect Reduction and EOT Scaling in Gate Dielectrics Supervisor Professor Hiroshi Iwai Department of Electronics and Applied Physics Interdisciplinary Graduate School of Science and Engineering Tokyo Institute of Technology 09D36020 Miyuki Kouda
Transcript of A Systematic Study of Rare-Earth Oxide for Charged Defect ...
Doctor thesis
2011
A Systematic Study of Rare-Earth Oxide for Charged Defect Reduction and EOT Scaling
in Gate Dielectrics
Supervisor
Professor Hiroshi Iwai
Department of Electronics and Applied Physics
Interdisciplinary Graduate School of Science and Engineering
Tokyo Institute of Technology
09D36020
Miyuki Kouda
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Abstract
Rare Earth (RE)-oxides are attractive candidates as the next generation materials
for the MOSFET gate dielectics. In this thesis work, the electrical properties of MOS
devices using RE-oxides such as La, Ce, Pr, Nd, Eu, Gd, and Tm oxide as the gate
dielectrics were investigated. It was found that La2O3 is the most promising among
these RE-oxides, because La-rich La-silicate layer with high dielectric constant can be
formed at the Si interface without forming any SiO2 interfacial layers. However, it was
found that some large amount of fixed charges is formed in the silicate layer, depending
on the condition. These fixed charges were found to be reduced by stacking a Ce-oxide
(CeOX) layer on the La2O3 film. In addition, the formation of low dielectric constant
Si-rich La-silicate was found to be suppressed by covering La2O3 with a Nd- or
Tm-oxide layer, resulting in the reduction of EOT (Equivalent Oxide Thickness) of the
gate insulator. In order to decrease both EOT and the charged defect densities, a
sandwich film structure CeOX/NdOY/La2O3 was found to be effective. It was found that
thinning the gate-metal electrode and high-temperature annealing is useful for
decreasing EOT without increase in charged defect densities.
The research described in the above was accomplished with the gate dielectrics
deposited by E-beam evaporation methods. For the mass production LSI devices, ALD
(Atomic Layer Deposition) or CVD (Chemical Vapor Deposition) methods are believed
to be necessary for the gate dielectrics deposition. ALD (Atomic Layer Deposition) of
La2O3 and CVD (Chemical Vapor Deposition) of CeOX were developed for use for the
Re-gate oxide MOSFETs. It was found that the electric characteristics of MOSFETs
using the EB evaporation methods can be almost reproduced by the ALD/CVD methods,
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although some more improvement is necessary to reach the same level.
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Table of Contents Capter 1 Introduction .................................................................................................1
1.1 Background of This Work..........................................................................................2
1.2 Scaling Technique......................................................................................................3
1.3 Scaling Limits of Traditional SiO2 Gate Dielectric ...................................................4
1.4 Requirements for High-k Dielectric Gate Insulator ..................................................7
1.5 Direct Contact..........................................................................................................13
1.6 Rare-Earth Oxide Materials.....................................................................................19
1.7 Purpose of This Work..............................................................................................24
Capter 2 Fabrication and Characterization Methods ...................................29
2.1 Experimental Procedure ..........................................................................................30
2.1.1 Fabrication Procedure for nMOS Capacitors ...................................................30
2.1.2 Fabrication Procedure for nMOSFETs .............................................................31
2.1.3 Silicon Surface Cleaning Process .....................................................................32
2.1.4 Formation of Gate Insulators............................................................................33
2.1.4.1Electron-Beam Evaporation Method..........................................................33
2.1.5 Post Metallization Annealing (PMA) Method..................................................34
2.2 Measurement Methods ............................................................................................35
2.2.1 C-V (Capacitance-Voltage) Measurement ........................................................35
2.2.2 Gate Leakage Current – Voltage (J-V) Characteristics.....................................39
2.2.2.1 Schottky Effect ..........................................................................................39
2.2.2.2 Poole-Frenkel Effect..................................................................................41
2.2.2.3 Fowler-Nordheim Tunneling Effect ..........................................................44
2.2.2.4 Image-Force Effect ....................................................................................45
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2.2.3 Threshold Voltage.............................................................................................45
2.2.4 Subthreshold Slope ...........................................................................................46
2.2.5 Mobility Extraction Technique ~Split C-V Measurement~ .............................47
2.2.6 Charge Pumping Methods ................................................................................51
2.2.7 XPS Measurement ............................................................................................54
2.2.8 Atomic Force Microscopy................................................................................56
Capter 3 Electrical Properties of Rare-Earth Oxides ...................................59
3.1 Introduction .............................................................................................................60
3.2 Interfacial Reaction..................................................................................................61
3.2.1 Formation of SiO2 interfacial layer ..................................................................65
3.2.2 Formation of the Silicate Layer ........................................................................66
3.2.2.1 Electrical Properties of La2O3 Layered Device .........................................67
3.2.2.2 Electrical Properties of Tm-oxide Layered Device. ..................................68
3.3 Generation of Charged Defects ...............................................................................76
3.4 Summary of RE-oxides Properties ..........................................................................84
3.5 Summary and Conclusion........................................................................................85
Capter 4 Consideration of Reduction in Charged Defects
~ Theoretical Calculation and Analysis of Experiment~ ................89
4.1 Introduction .............................................................................................................90
4.2 A Novel Capping Technique....................................................................................91
4.3 Theoretical Study.....................................................................................................92
4.3.1 First-Principles Calculation ..............................................................................93
4.3.2 Density-Functional Theory (DFT)....................................................................93
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4.3.3 Local Density Approximations (LDA) .............................................................94
4.3.4 Calculation of Charge Defects..........................................................................95
4.3.4.1 Formation Energy ......................................................................................96
4.3.4.2 Concentration of Charge Defects in La2O3................................................99
4.4 Experimental Results.............................................................................................104
4.5 Consideration of Defect-Reduction for Other Material.........................................109
4.6 Summary and Conclusion......................................................................................110
Capter 5 Suppression of Interfacial Reaction for EOT Scaling...............112
5.1 Introduction ...........................................................................................................113
5.2 Suppression of Silicate Formation by Using Capping ..........................................114
5.3 High-Temperature Annealing and Spike Annealing..............................................123
5.4 Effect of Thin Metal Thickness .............................................................................124
5.5 Confirmation of Effects of PMA and Thin Metal on Device Performance...........126
5.6 Summary and Conclusions ....................................................................................128
Capter 6 Charged Defects Reduction and EOT Scaling Combining
Several RE-oxides.....................................................................................................131
6.1 Introduction ...........................................................................................................132
6.2 Charged Defect and EOT Scaling Reduction Techniques .....................................132
6.3 Proposed Structure for Gate Insulator with RE-oxides .........................................133
6.4 Combination of Several Processing Conditions ....................................................136
6.5 Summary and Conclusion......................................................................................142
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Capter 7 Evaluation of High-k Film Formed by Atomic Layer
Deposition and Chemical Vapor Deposition Processes ...............................145
7.1 Introduction ...........................................................................................................146
7.2 Chemical Vapor Deposition...................................................................................148
7.3 Atomic Layer Deposition ......................................................................................151
7.4 Process Condition and Film Properties .................................................................154
7.4.1 La2O3 Film......................................................................................................154
7.4.1.1 La(iPrCp)3 ................................................................................................154
7.4.1.2 La(iPrFAMD)3 .........................................................................................158
7.4.2 Ce-oxide Film.................................................................................................161
7.4.2.1 Ce(Mp)4 ...................................................................................................161
7.4.2.2 Ce(EtCp)3 and Ce(iPrCp)3 .......................................................................167
7.5 Electrical Properties of MOS Devices...................................................................172
7.5.1 La2O3 Film Devices ........................................................................................172
7.5.2 CeO2 Single Layer ..........................................................................................177
7.5.3 La2O3 and CeO2 Stacked Film........................................................................181
7.6 Summary and Conclusions ....................................................................................186
Capter 8 Summary and Conclusions .................................................................191
Publications and Presentations............................................................................195
Acknowledgments.....................................................................................................199
1
Chapter 1 Introduction
1.1 Background of This Work 1.2 Scaling Technique 1.3 Scaling Limits of Traditional SiO2 Gate Dielectric 1.4 Requirements for High-k Dielectric Gate Insulator 1.5 Direct contact 1.6 Rare-Earth Oxide materials 1.7 Purpose of this work
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1.1 Background of This Work
Today, modern human society is affluent in high technology electronic products
such as personal computers, mobile phones, video game machines, digital cameras, and
human-like robots. These products contain numbers of Very-Large-Scale integrated
(VLSI) circuits. Because Metal-Oxide-Semiconductor Field Effect Transistors
(MOSFETs) are the major component of the VLSI, the performance and power
consumption of VLSI depend on those of MOSFETs, which have strong relation with
the physical dimensions of the MOSFETs.
Gordon Moore, who is one of the founders of Intel Corporation, predicted an
exponential growth in the number of transistors per integrated circuit. In concrete, he
expected that this trend would continue for another decade, in a popular article written
in 1965 [1.1, 1.2]. Figure1.1 shows Moore’s original prediction. His prediction is
popularly known as “Moore’s Law”. Moore’s Law states that the number of transistors
on integrated circuits doubles approximately every 24 months. Moore’s law has been
the driving force of the progress of semiconductor and electronics industries in which
number of the transistors and their performance increase exponentially year to year,
resulting in the emergence of more powerful and intelligent application devices every
year. In fact, the historical trend shows that the total number of transistors in
microprocessor has increased double every 2-3 years in the past 40 years, from the first
microprocessor, 4004, to the most recent Core i7 [1.3]. This is in good agreement with
the Moore’s Law.
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Figure 1.1 Moore's Original Law: Logarithm of the Number of Components on a Memory Chip Over
Time.
1.2 Scaling Technique
In order to keep the Moore’s Law, the downsizing of MOSFETs, the downsizing of
MOSFETs is necessary. The downsizing of MOSFETs has been accomplished by the
scaling method, propose by R. Dennard in 1973 [1.4]. In this method, both horizontal
and vertical dimensions such as the gate length and the gate insulator thickness are
decreased by factor S. At the same time, the supply voltage is decreased by the same
factor S. On the other hand, Si-substrate impurity doping density is increased by the
factor S (Fig. 1.2 and Table 1.1).
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Figure 1.2 Schematic description of scaling
Table 1.1 Scaling of MOSFET by a factor of S Quantity Before scaling After scaling
Channel length L L’ = L/S Channel width W W’ = W/S
Device area A A’ = A/S2 Gate oxide thickness tox tox’ = tox/S Gate capacitance per
unit area Cox Cox’ = S*Cox
Junction depth xj xj’ = xj/S Power supply voltage VDD VDD’ = VDD/S
Threshold voltage VT0 VT0’ = VT0/S NA NA’ = S*NA
Doping densities ND ND’ = S*ND
1.3 Scaling Limits of Traditional SiO2 Gate Dielectric
As mentioned in the previous section, the dimensions of the MOSFETs, which are
the major component of VLSIs have to be decreased every few years in order to realize
their better performance and lower price. In the course of the down-scaling of
MOSFETs, the gate insulator thickness should be reduced at every generation of the
scaling.
Silicon dioxide (SiO2) has been used for the gate insulator for 40 years, because its
L
tox
W
ND ND
NA
L/S
tox/S
W/S
NA*SND*S
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extraordinarily good electrical characteristics at the interface with Si substrate. For the
past 4 decades, the thickness of the SiO2 gate dielectrics has successfully scaled-down
from 100 to 1.2 nm. However, 1.2 nm is already the thickness of a few atomic layers as
shown Fig. 1.3 (a) [1.5]. Thus, the gate insulator thinning is now approaching to its limit,
because no one can make the film less than a mono-atomic layer. Also, the
direct-tunneling leakage current and the resulting increase in stand-by power dissipation
became the major issues to be solved in order to realize the further down-scaling of the
MOSFETs.
The direct-tunneling current leakage is proportional to the equation as follows,
I ∝ exp-(mφ)‧D (1.1)
where, m is electron effective mass,φis barrier height, and D is physical thickness of
gate oxide.
Obviously, the gate direct-tunneling leakage current increases when the thickness
of gate dielectric film becomes smaller. Figure 1.3 (b) shows the relationships between
gate leakage current density and EOT (Equivalent Oxide Thickness). The gate leakage
current density reaches 600 A/cm2 as the thickness of SiO2 decreases down to 1nm.
Furthermore, the gate leakage current becomes 1 kA/cm2 in the case of 0.8 nm. As
shown in Table 1.2, EOT value in high performance logic MOSFETs is predicted to be
continuously decreased every 2 years. Already, the SiO2 gate oxide film reaches its limit
at the thickness of 1 nm in consideration of the direct-tunneling leakage current, and
thus new dielectrics with high-dielectric constant (or high-k dielectrics) were introduced
in order to continue the down-scaling of MOSFETs [1.6].
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Figure 1.3 Relationship between gate leakage current density and EOT. Gate leakage current continues to
increase as far as SiO2 is used for gate dielectric [1.5].
(a)
(b)
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Table 1.2 ITRS 2010 update [1.6]
1.4 Requirements for High-k Dielectric Gate Insulator
Replacement of the SiO2 film by high dielectric (or high-k) material is a good
solution to decrease the direct-tunnel leakage current. Figure 1.4 shows the mechanism
for the difference of the direct-tunneling current between SiO2 and high-k gate
insulators. In the case of high-k, the physical thickness of the gate insulator becomes
large enough to suppress the direct-tunneling effect.
The direct-tunneling leakage current (JDT) flowing through a gate insulator film is
determined by the tunneling probability of the carrier. The tunneling probability of the
carrier (DDT) is shown in the equation below, where d is the physical thickness of
insulator, m* is electron effective mass in the gate insulator film, and φb is barrier height
of insulator.
)*2(4exp21
hmdDJ b
DTDTφπ
−∝∝ (1.2)
Relationship between the physical thickness of SiO2 (dEOT) and the physical
thickness of high-k gate insulator (d) to realize the same gate capacitance value (C) is
shown in the equation below, where the dielectric constant of SiO2 is εSiO2 and the
1.31.21.110.90.830.65Gate leakage
current(kA/cm2)
0.530.550.650.750.880.951EOT(nm)
2015201420132012201120102009
1.31.21.110.90.830.65Gate leakage
current(kA/cm2)
0.530.550.650.750.880.951EOT(nm)
2015201420132012201120102009
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high-k gate insulator is εhigh-k.
EOTkhigh
SiO
EOT
SiOkhigh
dd
ddC
−
−
=
==
εε
εε
2
2
(1.3)
Therefore, the physical thickness for the same C is larger for the high-k film case.
(Note that εhigh-k is larger than εSiO2 ). This means that the gate leakage current is
suppressed by using high-k materials.
Figure 1.4 Schematic descriptions of differences of the gate leakage between two cases using, (a) SiO2
and (b) high-k material, as gate insulator
e-
e-
e-
e-
EOT=1nm
SiO2(ε=3.9)
Physical thickness=1nm
EOT=1nm
Physical thickness=10nm
High-k(ε=39)
e-
(a) Direct tunneling current flows (b) Direct tunneling current is suppressed
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Table 1.3 shows the periodic Table, in which elements (or metals) in red frames are
assumed to be applicable for gate insulators as oxides. Table 1.4 shows the properties of
major high-k materials. Four main requirements for gate insulators are listed below.
(1) A large negative energy of formation of the metal oxide, so it does not react
significantly with Si to form SiO2 or silicates during high-temperature process of
MOSFET fabrication.
(2) Low diffusion coefficients of oxygen in the metal oxide film during high
temperature process to avoid the growth of silicate or SiO2 interfacial layers.
(3) High quality interfaces between the metal oxides and Si, so as not to degrade the
carrier mobility of MOSFETs.
(4) High potential barriers (or band offset) from the Si conduction/valence band to that
of metal oxide, so as to suppress the tunneling leakage current both for electrons and
holes.
(5) High dielectric constant for the metal oxides.
There are many reports about HfO2, ZrO2 and Al2O3 [1.7-1.9]. It was reported that
Al2O3 has low interface state density [1.10] but its dielectric constant value is about
only 9. This value is not sufficiently high for the high-k application. HfO2 and ZrO2
have sufficiently high dielectric constant such as 25 and 17 [1.11, 1.12]. Because HfO2
has slightly higher dielectric constant than that of ZrO2, HfO2 was chosen as the better
candidate between them. The problem of HfO2 and ZrO2 is that those oxides easily react
with Si to form SiO2 at the Si interface [1.13, 1.14].
There are some RE (rare earth) oxides such as La2O3 and CeO2 which have large
dielectric constant (27 or 26) [1.15, 1.16] and relatively good electrical properties at the
Si interface. These materials are expected to be suitable for gate insulators of MOSFETs.
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Furthermore, especially, La2O3 has significantly higher band offset than that of HfO2
and ZrO2 Thus, La2O3 could be regarded as the best material for the high-k gate
insulator, However, there is a big concern for the RE oxides. Usually RE-oxides have
high hygroscopicity and the film easily become thick in the air by absorbing the
moisture.
Table 1.3 Periodic table
103Lr
102No
101Md
100Fm
99Es
98Cf
97Bk
96Cm
95Am
94Pu
93Np
92U
91Pa
90Th
89Ac*2 Actinide：
71Lu
70Yb
69Tm
68Er
67Ho
66Dy
65Tb
64Gd
63Eu
62Sm
61Pm
60Nd
59Pr
58Ce
57La*1 Lanthanide：
118Uuo
117Uus
116Uuh
115Uup
114Uuq
113Uut
112Cn
111Rg
110Ds
109Mt
108Hs
107Bh
106Sg
105Db
104Rf*288
Ra87Fr
86Rn
85At
84Po
83Bi
82Pb
81Tl
80Hg
79Au
78Pt
77Ir
76Os
75Re
74W
73Ta
72Hf*156
Ba55Cs
54Xe
53I
52Te
51Sb
50Sn
49In
48Cd
47Ag
46Pd
45Rh
44Ru
43Tc
42Mo
41Nb
40Zr
39Y
38Sr
37Rb
36Kr
35Br
34Se
33As
32Ge
31Ga
30Zn
29Cu
28Ni
27Co
26Fe
25Mn
24Cr
23V
22Ti
21Sc
20Ca
19K
18Ar
17Cl
16S
15P
14Si
13Al1211109876543
12Mg
11Na
10Ne
9F
8O
7N
6C
5B
4Be
3Li
2He17161514132
1H
181
Metal
Semimetal
Nonmetal
Artificial element
1
1
1
Solid
Liquid
Gas
11
Table 1.4 High-k material properties
Thus, among the candidates for high-k materials, Hf-based materials were thought
to be the most promising candidate by the late 1990’s. As shown in Fig. 1.5, papers on
many different high-k materials were published in the major semiconductor conferences
up to 2002. However, from 2003, the main candidate for high-k materials has narrowed
down to Hf-based materials. Therefore, Hf oxides (HfO2), Hf-based silicates (HfSiXOY)
and nitrides (HfSiXOYNZ), with dielectric constants of 25, 10, and 15, respectively, were
considered to be the promising candidate for the 65 and 45-nm-technology nodes.
Materials SiO2 Al2O3 La2O3 Pr2O3 Gd2O3 HfO2 ZrO2
EOT (nm) 0.8 1.5 0.48 1.4 1.5 0.8 0.8
Contact stability with Si (kJ/mol)
Si+MOx→M+SiO2 Stable +63.4 +98.5 +105.8 +101.5 +47.6 +42.3
Lattice energy (kJ/mol) 13125 15916 12687 12938 13330 11188
Bandgap (eV) 9 6 – 8 5.4 3.9 5.4 5.7 5.2 – 7.8
Structure Amorphous Amorphous Amorphous Crystal T>700ºC
Crystal T>400ºC
Crystal T>700ºC
Crystal T>400 - 800ºC
κ 3.9 8.5 – 10 27 13 17 24 11 – 18.5
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Figure 1.5 High-k materials reported in VLSI and IEDM
Usually, the effective mobility of the high-k gate MOSFETs tends to decrease due
to the carrier scattering at the high–k/Si interface. It was been reported that the mobility
degradation of Hf-based gate oxide MOSFETS was suppressed by the insertion of
intentionally-grown thin SiO2-based interfacial layer (0.5 to 0.7) nm at the interface as
shown in Fig.1.6 (a) [1.6]. In fact, Intel succeeded to introduce Hf-based high-k gate
insulator into its 45 nm products using this method. However, this method increases the
EOT. Figure 1.6 (b) shows required EOT values described in ITRS roadmap. To
achieve the EOT less than 0.7 nm, high-k/Si direct contact without the SiO2 interfacial
layer is necessary.
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Figure 1.6 (a) Limit of EOT scaling and (b) EOT required from ITRS 2010.
1.5 Direct Contact
In general, without the insertion of the intentionally inserted SiO2 layer, a thin
SiO2-based interfacial layer is automatically formed between HfO2 and the Si substrate
during the high temperature thermal treatment. This is due to the thermodynamics in the
Si
High-k High-k High-k
SiOx interfacial layer (typ.0.5~0.7nm)
Scaling in EOTlimit
excess gate leakageHf based oxide
0
0.2
0.4
0.6
0.8
1
1.2
2009 2014 2019 2024
ITRS 2009
Year
EOT(
nm)
EOT=0.5 nm
bulk
MG
UTB FD
(a)
(b)
14
non-stoichiometry of the high-k films [1.17]. Numerous studies have tried to optimize
the process conditions, including the control of oxygen partial pressure during HfO2
deposition and the incorporation of metal atoms in the gate electrode, which reduce the
formation of an interfacial layer and thereby achieve a direct contact of high-k with the
Si substrate [1.18]. One of the reports is shown in [1.19]. Figure 1.7 shows TEM image
of TiN/Ti/HfO2/Si gate stacks. In those structures, Ti was deposited on HfO2 as
oxygen-controlling metal (OCM). When the OCM thickness was over than 7 nm, SiO2
interfacial layer was not formed. The mechanism is expounded in Fig. 1.8.
Figure 1.7 X-TEM images of the TiN/Ti/HfO2/Si gate stack structures after cap-PDA at 983oC. The HfO2
thickness was 4.7 nm, and the Ti thicknesses were (a) 5.0 and (b) 7.0 nm, respectively [1.19].
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Figure 1.8 Schematic illustration of SiO2 IL growth in 780oC cap-PDA for three different Ti OCM layer
thicknesses [1.19].
For the 7.0-nm-thick Ti layer, all of the released oxygen from HfO2 at 780oC
annealing could be absorbed by the Ti OCM layer, and the SiO2 Interfacial layer (IL)
did not form. The oxygen absorbability was proportional to the thickness of the Ti layer.
Thinning of the Ti OCM layer led to a decrease in oxygen absorbability. With this
method, achieving HfO2/Si direct contact is possible. However, the electrical properties
were degraded in this layered device. Figure 1.9 shows the mobility characteristics in
HfO2/Si and HfO2/SiO2/Si layered MOSFETs [1.20]. The mobility was degraded by
achieving direct contact. This could be due to increase in interfacial state density. From
Fig. 1.7, it is known that HfO2 layer is crystallized in HfO2/Si layered structure.
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Figure 1.9 Effective mobility characteristics with thickness of HfO2 layer a parameter and influence of
SiO2 IL on election mobility characteristics [1.20].
In contrast to this, La2O3 material is known to react with the Si substrate to form
silicate at the interface. The La2O3 silicate itself is also a high-k material when the
composition is La rich, so that a direct contact of high-k with Si substrate can be
achieved as shown in Fig. 1.10. It should be noted that a smooth interface was achieved
presumably due to high viscosity of the La-silicate at high temperature annealing [1.15].
0 0.2 0.4 0.6 0.8 1.0Eeff (MV/cm)
17
Figure 1.10 TEM image of W/ La2O3 /Si structure after annealing [1.15].
Good electrical properties can be achieved based on this interface. Figure 1.11 shows
the mobility characteristics in La2O3/Si direct contact construction MOSFETs [1.21].
Figure 1.11 Effective mobility characteristics in La2O3/Si direct contact construction devices [1.21].
Comparing the mobility of the same physical thickness devices shown in Figs. 1.10 and
La-silicate
La2O3
W
2.0nm
4.0nm3.0nm
2.5nm
La2O3/Si
0 0.2 0.4 0.6 0.8 1.0Eeff (MV/cm)
µ eff
(cm
2 /Vs)
350
300
250
200
150
100
50
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1.11, the mobility of La2O3 MOSFETs was higher than that of HfO2. In the bench mark
of the recent publications for the mobility of Hf-based and La-based gate oxide
MOFFETs, La-silicate MOSFETs shows top value, although the difference between the
Hf-base top results was not so significant as shown in Fig. 1.12 and Table 1.5 [1.22].
Therefore, rare-earth oxides such as La2O3, which forms high-k silicate at the interface
with good interfacial electrical property is a strong candidate, for future gate insulator
with EOT less than 0.7 nm.
Figure 1.12 Bench mark of the effective electrical mobility at 1 MV/cm [1.22]
La-based oxide
19
Table 1.5 Si benchmark (nMOSFET) [1.22]
1.6 Rare-Earth Oxide Materials
RE-oxide materials are known to react with Si substrates forming silicates and/or
SiO2 at the interface. The amount of formed silicates and SiO2 are dependent on the
elements. Figure 1.13 shows the peak heights of Si–O–Ln phonon absorption in infrared
spectra with various RE elements, where Ln represents lanthanide elements (La, Pr, Nd,
Sm, Eu, Gd, Tb, Dy, Er, Tm, and Yb) as well as Y [1.23]. The peak height corresponds
to the reactivity of RE-oxides and Si substrate to form silicates, thus the higher peak in
the spectra, the more silicate layer grows at the interface of RE-oxides and the substrate.
One can see a decreasing trend in reactivity to form silicates with larger atomic number,
irrespective on the annealing ambient. As the ion radii decreases along with larger
atomic number, which is the typical characteristics of RE elements known as lanthanide
contraction, it is speculated that the Si atoms can easily diffuse from the substrate to the
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films with longer bonding distance owing to larger spaces inside them. Nevertheless,
RE-silicates possess high k-values, ranging from 8 to 20 in some cases, so that these
silicates can be considered as high-k materials. Therefore, once the formation of SiO2
layer is suppressed, RE-oxides have a large potential as gate insulators for future
MOSFETs.
Figure 1.13 Absorption peak height of Si–O–Ln (Ln: Lanthanide elements plus Y) bonds obtained by
transmission measurements of infrared absorption spectra for thin Ln2O3 films as-grown and annealed at
900 °C for 30 min in O2 and N2 ambient [1.23].
Additionally, RE-oxides have a large band gap (Fig. 1.14) which is generally
favorable for the large band offset against the conduction and valence bands of Si [1.24,
1.25]. In fact, the band offset of La2O3 is much larger than that of HfO2, as shown in Fig.
1.15 [1.26]. The large band offset is desirable to suppress the gate leakage current.
21
Figure 1.14 Band gap in each rare-earth oxide materials [1.24, 1.25].
Figure 1.15 Predicted barrier heights of high-k oxide materials [1.26].
Larger growth of silicate during high temperature anneal significantly increases
the EOT value, and will be a problem as shown in Fig. 1.16 [1.27]. The oxygen control
method had been reported as one of the solution [1.22]. However, this method
sometimes requires complicated fabrication processes.
22
Figure 1.16 Thickness increase after 15 s anneal in an oxygen containing ambient as function of anneal
temperature [1.27]
Moreover, the formation of the charged defects in the high-k film is significantly
changed by the ambient oxygen pressure. Figure 1.17 shows the formation and change
of the charged defects in a RE-oxide film with oxygen partial pressure.
Figure 1.17 Influence of oxygen partial pressure on formation of charged defects
RE-oxide
Positive charges =oxygen vacancy (Vo
2+)Negative charges =interstitial oxygen (Io2-)
HighLowOxygen partial pressure
Oxygen vacancy
rich
Interstitial oxygen
rich
Io2-
Vo2+
RE-oxide RE-oxideVo
2+
Vo2+ Vo
2+
Vo2+
Vo2+
Vo2+
Io2-
Io2-
Io2-
Io2-
Io2-Io2-
Io2-
Vo2+
23
The positive or negative charges are formed under oxidation or reduction ambient,
respectively. Those charges cause various issues on electrical properties, such as
flat-band voltage (Vfb) shift, mobility degradation, leakage current increase, and
reliability degradation, etc. These issues must be solved in order for RE-oxides to be
used as the gate insulator of MOSFETs. Figure 1.18 shows the results of Vfb shift
obtained by experiments. In Fig.1.18(a), Vfb shift was induced in oxidizing ambient
[1.28]. In Fig.1.18(b), Vfb change was induced due to the change of the annealing
ambient [1.29].
Figure 1.18 Flat-band voltage (Vfb) shift. Vfb shift caused by (a) oxidising ambient [1.28], (b) changing the
external oxygen atmosphere [1.29]
Those results indicate that the degradation of the film property depends on the
oxygen partial pressure of the ambient. Controlling the ambient oxygen partial pressure
will be effective for decreasing the charged defects concentration. However, it is not
easy to adjust the ambient oxygen pressure in the entire process of the device fabrication.
Thus, an alternative solution is desired.
0.8
0.7
0.6
0.5
0.4
0.3
0.2
Nor
mal
ized
cap
acita
nce
(C/C
max
)
-2 -1 0 1 2Gate voltage (V)
FGA FGA + OGA FGA + OGA + FGA
24
1.7 Purpose of This Work
The RE-oxide materials have a potential for achieving a good direct contact to Si
substrate in order to realize a small EOT. As described in the previous section, there are
cases that the RE-oxides usually form RE-silicate layers at the Si interface, and that the
RE-silicates have a high dielectric constant values ranging from 8 to 20, while HfO2
usually forms a SiO2 layer at the interface. However, there have been not so many
reports on the systematic studies on the RE-oxide application on MOSFET gate stack,
compared with those of Hf-oxide. Thus, there are many concerns on the introduction of
RE-oxides; such as the excessive growth of the interfacial silicate and degradation of
the electrical property at the interface by the formation of charged defects.
The purpose of this thesis work is to investigate the optimum construction of gate
insulator of MOSFETs in case of using RE-oxides for EOT scaling towards 0.5 nm. By
the experiment of various RE (La, Ce, Pr, Nd, Eu, Gd, Tm)-oxides, the best RE-oxides
for MOSFETs with small EOT aiming to 0.5 nm is determined. Furthermore, the effect
of the combinations of RE-oxide films for the gate insulator is investigated.
Fig.1.19 shows the contents of this thesis. This thesis is consisted of 8 parts. In
chapter 1, background and purpose of these researches are described. In chapter 2, the
fabrication conditions of MOS device and measurement method of electrical properties
are explained. In chapter 3, the results of the evaluation of the properties of RE-oxides,
La, Ce, Pr, Nd, Eu, Gd, and Tm-oxide are described. In chapter 4, a novel capping
technique for the reduction of charged defects in gate insulator is shown. In chapter 5,
EOT scaling techniques by using Nd and Tm-oxide are described. Furthermore, the
effects of high-temperature spike annealing and thinning the gate electrode metal layer
on the EOT scaling is described. In chapter 6, the reduction of charged defect density
25
and EOT scaling by the combination of various RE-oxide films are described. In chapter
7, the results of the development of high-film deposition for CVD-CeO2 and
ALD-La2O3 are described. The electrical properties of MOS device using those layers
are shown. Additionally, the comparison of electrical characteristics of the MOSFETs
with high-k gate insulators deposited by Electron beam evaporation and CVD/ALD is
described. In chapter 8, the results of the thesis study are summarized and concluded.
Figure 1.19 Contents of this thesis
Chapter 1 Introduction
Chapter 2 Fabrication and Characterization Method
Chapter 4 Consideration of Reduction in
Charged Defects
Chapter 6 Charged Defects Reduction and EOT Scaling Combining
Several RE-oxides
Chapter 5 Suppression of Interfacial Reaction for EOT Scaling
Chapter 8 Summary and Conclusions
Chapter 7Evaluation of High-k Film Formed
by CVD and ALD Processes
Chapter 3 Electrical Properties of Rare-Earth Oxides
26
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[1.2] Gordon E. Moore, No Exponential is Forever: But “Forever” Can Be Delayed,
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IEEE JSSC, 9(5) (1974) 256.
[1.5] R. Chau, S. Datta, M. Doczy, J. Kavalieros, and M. Metz, “Gate Dielectric Scaling for High-Performance CMOS: from SiO2 to High-k, Ext. Abst. of International Workshop on Gate Insulator (IWGI)., pp. 124-126, 2003
[1.6] International Technology Roadmap for Semiconductors, http://www.itrs.net/.
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S. T. Pantelides, and S. J. Pennycook, Appl. Phys. Lett. 85, 672 (2004)
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Appl. Phys. 92, 1232 (2002).
[1.15] K. Kakushima, K. Tachi, M. Adachi, K. Okamoto, S. Sato, T. Kawanago,
P.Ahmet, K.Tsutsui, N. Sugii, T. Hattori, H. Iwai, Advantage of La2O3 Gate Dielectric
over HfO2 for Direct Contact and Mobility Improvment” ESSDERC 2008, pp. 126-129,
October 15-19 ,2008, Scotland, UK.
[1.16] R. Barners, D. Starodub, T. Gustafsson, and E. Garfunkel, J. Appl. Phys. 100,
044103(2006).
[1.17] S. Stemmer, J. Vac. Sci. Technol. B 22, 791 (2004).
[1.18] J. Huang et al., Dig. Tech. Pap. - Symp. VLSI Technol. 34 (2009).
[1.19] Y. Morita et al., Jpn. J. Appl. Phys. 50 (2011) 10PG01.
[1.20] N. Miyataet al., Appl. Phys. Exp. 4 (2011) 101101.
28
[1.21] K. Kakushima, K. Tachi, M. Adachi, K. Okamoto, S. Sato, J. Song, T. Kawanago,
P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori and H. Iwai, Solid State Electron. 54, 715
(2010).
[1.22] T. Kawanago, Y. Lee, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N.
Sugii, K. Natori, T. Hattori, and H. Iwai, IEEE Trans. Electron Devices 59(2), (2012)
269.
[1.23] J. R. Hauser, “Extraction of Experimental Mobility Data for MOS Devices,”
IEEE Trans. Electron Devices, Vol. 43, no. 11, pp. 1981-1988, 1996.
[1.24] G. Adachi, Science of rare earths, Kagakudojin Co., 1999, p.291.
[1.25] A. Prokofiev, A. Sheykh, and B. Melekh, “Periodicity in the band gap variation of
Ln2X3 (X=O,S,Se) in the lanthanide series,” J. Alloys and Compounds, 242, pp.41-44
(1996).
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29
Chapter 2
Fabrication and Characterization Methods
2.1 Experimental Procedure 2.1.1 Fabrication Procedure for nMOS Capacitors 2.1.2 Fabrication Procedure for nMOSFETs 2.1.3 Silicon Surface Cleaning Process 2.1.4 Formation of Gate Insulators
2.1.4.1Electron-Beam Evaporation Method 2.1.5 Post Metallization Annealing (PMA) Method
2.2 Measurement Methods 2.2.1 C-V (Capacitance-Voltage) Measurement 2.2.2 Gate Leakage Current – Voltage (J-V) Characteristics
2.2.2.1 Schottky Effect 2.2.2.2 Poole-Frenkel Effect 2.2.2.3 Fowler-Nordheim Tunneling Effect 2.2.2.4 Image-Force Effect
2.2.3 Threshold Voltage 2.2.4 Subthreshold Slope 2.2.5 Mobility Extraction Technique ~Split C-V Measurement~ 2.2.6 Charge Pumping Methods 2.2.7 XPS Measurement 2.2.8 Atomic Force Microscopy
30
2.1 Experimental Procedure
2.1.1 Fabrication Procedure for nMOS Capacitors
Figure 2.1 summarizes device fabrication flow of RE-oxides MOS-capacitors. The
MOS capacitors were fabricated on n-type (100)-oriented 2-5 Ω-cm Si substrate. To
determine the capacitor area and to avoid unexpected peripheral effect, 400 nm-thick
thermal oxide was formed and patterned photolithography. The wafers were then
cleaned by a mixture of H2SO4/H2O2 at 85 oC for 5 min to remove all of the organic
contamination, followed by diluted HF cleaning. Thin films of high-k were deposited
using e-beam evaporation from pressed materials target in an ultra-high vacuum
chamber of 10-7 Pa. The tungsten (W) gate electrode of 50 nm was coated by RF
sputtering with power of 150 W. Electrode was finally lithographically patterned to
form MOS capacitors. Post-deposition annealing (PDA) in forming gas
(3 %-H2+97 %-N2) was carried out. Finally, aluminum (Al) was thermally evaporated
on backside of the wafers for bottom electrode.
Figure 2.1 Fabrication procedures for MOS-capacitor
MetalHigh-k
Al
n-type Si substrate
SPM, HF last treatment
High-k materials deposition
Tungsten (W) metal gate electrode deposition by RF sputtering
PMA (Post Metallization Annealing) 500 30min (FG:3%H2)
Bottom electrode Al deposition
In situ
31
2.1.2 Fabrication Procedure for nMOSFETs
The fabrication procedure for nMOSFET is shown in Figure 2.2. nMOSFET
fabrication was started from a Si(100) substrate with isolation and S/D regions. High-k
thin film was deposited by Electron-Beam Evaporation followed by substrate cleaning.
After metal gate formation, the gate area was defined with photolithography followed
by metal gate etching. Annealing in forming gas was performed at 500 oC for 30 min.
The Al-Pad area was formed with lift-off process under acetone solution and Al back
side electrode were formed afterwards.
Figure 2.2 Fabrication procedures for nMOSFET
The detailed explanation of each process and experimental equipment will be
described in next section.
AlSource Drain
p-type Si substrate (Source/Drain pre-formed)
SPM, HF last treatment
High-k materials deposition
Tungsten (W) metal gate electrode deposition by RF sputtering
PMA (Post Metallization Annealing) 500 30min (FG:3%H2)
Source, Drain Al interconnection
Bottom electrode Al deposition
In situ
32
2.1.3 Silicon Surface Cleaning Process
Prior to the deposition of high-k gate thin films for LSI fabrication process, the
ultra-pure surface of a bare Si-substrate should be chemically cleaned to remove
particles contamination, such as metal contamination, organic contamination, ionic
contamination, water absorption, native oxide and atomic scale roughness. It is
considered that this substrate cleaning process is very important to realize desirable
device operation and its reproducibility.
In full fabrication processes as well as substrate cleaning, DI (de-ionized) water is one
of the most important factors because DI water is highly purified and filtered to remove
all traces of ionic, particulate, and bacterial contamination. Theoretical resistively of
pure water at 25oC is 18.3 MΩ·cm. The resistively value of ultra-pure water (UPW)
used in this study achieved more than 18.2 MΩ·cm and have fewer than 1.2 colony of
bacteria per milliliter and no particle larger than 0.25 um.
In this study, a typical surface cleaning process by hydrofluoric acid, which is
usually called RCA cleaning method, was used [2.1]. But some steps were reduced.
First, silicon substrates were dipped in SPM solution (mixed 4 parts H2SO4 (96%) with
1 part H2O2 (30%)) at 85oC. And then, dipped in diluted hydrofluoric acid (1%) to
remove chemical or natural oxide layers and obtain hydrogen-terminated surface.
Hydrogen-terminated surface is stable against oxidation. The cleaning process flow is
shown in Fig. 2.3.
33
Figure 2.3 Si substrate cleaning
2.1.4 Formation of Gate Insulators
In this work, the gate insulator was formed by using electron-beam (EB)
evaporation, chemical vapor deposition (CVD), and atomic layer deposition (ALD).
CVD and ALD processes are described in more detail in chapter 7. In this section, those
processes were provided a simple explanation.
2.1.4.1Electron-Beam Evaporation Method
RE-oxide dielectrics were deposited in ultra high vacuum by electron-beam
evaporation method. Figure 2.4 shows the schematic drawings and a photograph of the
equipment. The background pressure in growth chamber reached as high as 10－8 Pa and
was approximately 10－7 Pa during deposition. In the growth chamber, a sintered
RE-oxide target, which is evaporation source, is irradiated with electron beam
accelerated by 5 kV. The target is heated up and RE-oxide molecules are evaporated.
Then ultra thin RE-oxide film is deposited on the Si-substrate. Physical thickness of the
UPW for 5min
H2SO4/H2O2 (SPM) for 5min
UPW for 5min
UPW for 5min
HF-H2O (DHF) for 5min
UPW for 5min
Remove organic and metal contamination
Remove native or chemical oxide
34
film is monitored with a film thickness counter using crystal oscillator. The temperature
of the substrate is controlled by a substrate heater and is measured by a thermocouple.
Figure 2.4 Schematic views of e-beam evaporation and RF sputtering system
2.1.5 Post Metallization Annealing (PMA) Method
PMA method was employed for the heat treatments after depositing metal
electrode. The annealing process is indispensable to decrease defects in dielectric film
and at the interface. The schematic PMA system and process flowchart are shown in Fig.
2.5. The samples with gate dielectric were put on silicon suspected and inserted into
heat-treating furnace. The furnace was vacuumed adequately by rotary pump for
highly-pure nitrogen or forming gas substitution. And then, nitrogen or forming gas (in
accordance with the purpose) was provided with a flow rate of 1.0 l/min and the
samples were annealed at atmospheric pressure. In order to evaluate the electrical and
chemical properties, the annealing temperatures were changed from 500oC and 700oC.
RP
TMP
RP
TMP
CeO2
La2O3
RE-oxideW
TaSi
Mg
Deposition Ch.Sputter Ch.
10-7Pa 10-7Pa
35
TMP
N2 or F.G
Exhaust
Sample Inserting sample
Vacuuming
Gas supply (N2 of F.G)
Start heating
Figure 2.5 Schematic illustrations of RTA system and annealing process flowchart
2.2 Measurement Methods
2.2.1 C-V (Capacitance-Voltage) Measurement
C-V characteristic measurements were performed with various frequencies (1
kHz~1 MHz) by precision LCR Meter (HP 4284A, Agilent). The energy band diagram
of an MOS capacitor on a p-type substrate is shown in Fig. 2.6 [2.2]. The intrinsic
energy level Ei or potential φ in the neutral part of device is taken as the zero reference
potential. The surface potential φS is measured from this reference level. The
capacitance is defined as
dVdQC = (2.1)
It is the change of charge due to a change of voltage and is most commonly given in
units of farad/units area. During capacitance measurements, a small-signal ac voltage is
applied to the device. The resulting charge variation gives rise to the capacitance.
Looking at an MOS capacitor from the gate, C = dQG / dVG, where QG and VG are the
gate charge and the gate voltage. Since the total charge in the device must be zero,
36
assuming no oxide charge, QG = (QS + Qit), where QS is the semiconductor charge, Qit
the interface charge. The gate voltage is partially dropped across the oxide and partially
dropped across the semiconductor. This gives VG = VFB + Vox + φS , where VFB is the
flatband voltage, Vox the oxide voltage, and φS the surface potential, allowing Eq. (2.1)
to be rewritten as
sox
its
ddVdQdQC
φ++
= (2.2)
The semiconductor charge density QS, consists of hole charge density Qp,
space-charge region bulk charge density Qb, and electron charge density Qn. With QS
=Qp + Qb + Qn, Eq. (2.2) becomes
itnbp
s
its
ox
dQdQdQdQd
dQdQdVC
++++
+
−=φ
1 (2.3)
Utilizing the general capacitance definition of Eq. (2.1), Eq. (2.3) becomes
itbpox
itnbpox
itnbpox
CCCCCCCCC
CCCCC
C+++
+++=
++++
−=)(
111 (2.4)
The positive accumulation Qp dominates for negative gate voltages for p-substrate
devices. For positive VG, the semiconductor charges are negative. The minus sign in Eq.
(2.3) cancels in either case.
Eq. (2.4) is represented by the equivalent circuit in Fig. 2.7 (a). For negative gate
voltages, the surface is heavily accumulated and Qp dominates. Cp is very high
approaching a short circuit. Hence, the four capacitances are shorted as shown by the
heavy line in Fig. 2.7 (b) and the overall capacitance is Cox. For small positive gate
voltages, the surface is depleted and the space-charge region charge density, Qb =
qNAW, dominates. Trapped interface charge capacitance also contributes to the
37
capacitance. The total capacitance is the combination of Cox in series with Cb in parallel
with Cit as shown in Fig. 2.7(c). In weak inversion Cn begins to appear. For strong
inversion, Cn dominates because Qn is very high. If Qn is able to follow the applied ac
voltage, the low-frequency equivalent circuit (Fig. 2.5(d)) becomes the oxide
capacitance again. When the inversion charge is unable to follow the ac voltage, the
circuit in Fig. 2.7 (e) applies in inversion, with Cb = Ks εO / Winv with Winv the inversion
space-charge region width. The flatband voltage VFB is determined by the
metal-semiconductor work function difference φMS and the various oxide charges
through the relation
dxxtx
Cdxx
CCQ
CQ
V ot
tox
ox
tox
oxm
oxox
sit
ox
fMSFB )(1)(1)(
00ρρφφ ∫∫ −−−−= (2.5)
where ρ(x) is oxide charge per unit volume. The fixed charge Qf is located very near the
Si-SiO2 interface and is considered to be at that interface. Qit is designated as Qit (φS ),
because the occupancy of the interface trapped charge depends on the surface potential.
Mobile and oxide trapped charges may be distributed throughout the oxide layer. The
x-axis is defined in Fig. 2.6. The effect on flatband voltage is the greatest when the
charge is located at the oxide-semiconductor substrate interface, because then it images
all of its charge in the semiconductor. When the charge is located at the gate-insulator
interface, it images all of its charge in the gate and has no effect on the flatband voltage.
In the study, principally, EOT values and flatband voltage were extracted from C-V
characteristics by using the NCSU CVC modeling program [2.3]. EOT values were
calculated with taking quantum effect into account.
38
Figure 2.6 Energy band diagram of a MOS capacitor formed on a p-type substrate
Figure 2.7 Capacitances of a MOS capacitor for various biases
39
2.2.2 Gate Leakage Current – Voltage (J-V) Characteristics
One of the main concepts of replacing the high-k gate dielectrics with SiO2 is to
suppress the gate leakage current. Thus, it is enormously important to measure the gate
leakage current-voltage (J-V) characteristics. In addition, the properties of high-k films,
such as the barrier height, effective mass, are obtained by analyzing the carrier transport
mechanisms from the leakage current. To investigate the voltage and temperature
dependences of gate leakage current, it is able to identify the carrier conduction
mechanisms experimentally [2.4]. J-V characteristics are measured using
semiconductor-parameter analyzer (HP4156A, Hewlett-Packard Co. Ltd.).
Additionally, Schottky, Poole-Frenkel and F-N leakage emission, which are known
as major leakage mechanism, were evaluated.
2.2.2.1 Schottky Effect
The Schottky effect is the image-force-induced barrier for charge carrier emission
with an applied field [2.5]. Figure 2.8 shows potential barrier at the metal-vacuum
interface. Maximum barrier height is reduced to image-force effect when an electric
field is applied. This can help the emission of thermally activated carriers from the
metal electrode, which is called Schottky emission. This type of carrier emission is
completely analogous to thermionic emission expect that the applied field lowers the
barrier height. Metal-vacuum system seen in Fig. 2.8 is also equivalent to
metal-insulator system as well as semiconductor-insulator system, expect for the
dielectric constant of vacuum part [2.6].
40
Figure 2.8 Energy band diagram near a metal surface in vacuum. Schottky emission is caused by Schottky
barrier lowering (or image-force lowering) [2.6]
πεφ
4qEqB =∆ (2.6)
Permittivity ε should be replaced by an appropriate permittivity characterizing the
medium. Since carrier emission occurs at much higher energy levels than Fermi level of
the injecting electrode, tunneling probability can be regarded as 1. So Tunneling current
is
⎥⎦
⎤⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛−−⎟⎟
⎠
⎞⎜⎜⎝
⎛ −−=
TkV
TkEE
Tkh
qmJBB
FmB exp1exp4 22
3
*π (2.7)
2/1
00 4 ⎟⎟
⎠
⎞⎜⎜⎝
⎛−=−
iFm
qEEEεπε
φ (2.8)
Here, h is Plank constant, kB is Boltzmann constant, Em is barrier height (f0=fm-c),
0 x
EF
image potentialenergy
Conduction Band Edge (E=0)
Conduction BandEdge (E>0)
φm-χ
∆φB
φB
xm
Metal
0 x
EF
image potentialenergy
Conduction Band Edge (E=0)
Conduction BandEdge (E>0)
φm-χ
∆φB
φB
xm
Metal
41
and V is applied voltage. In the condition of V>>kBT, Eq. (2.7) becomes
⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛−= 2/1022
3
*
expexp4 ETkTk
Tkh
qmJB
s
BB
βφπ (2.9)
2/1
04 ⎟⎟⎠
⎞⎜⎜⎝
⎛=
is
qεπε
β (2.10)
Equation (2.9) is also called Richardson-Schottky equation.
As expected, the Schottky current is caused by thermally activated process and the
activation energy is characterized by Eq. (2.9). The activation energy is modulated by
applied bias with Schottky barrier height lowering effect. One notice that the barrier
deformation decrease as the dielectric constant increase, indicating that, Schottky
emission in high-k oxide films seems to be less probable than that in conventional SiO2
film.
2.2.2.2 Poole-Frenkel Effect
In the MIS (Metal-Insulator-Semiconductor) structure, the P-F and Schottky
emission results from the lowering of a Coulomb potential barrier by an applied field.
The Schottky is associated with the insulator barrier near to the injecting electrode,
whereas the P-F effect is associated with the barrier at the trap well in the bulk of
insulator film. Thus, a neutral donor trap that is neutral when filled and positive when
empty do not experience the P-F effect owing to the absence of the Coulomb potential
[2.7].
Fig. 2.9 shows thermionic emission of trapped carrier in the bulk of the film, which
occurs at the trap site [2.8]. Internal thermionic emission is called as the P-F emission,
while external one is Schottky emission. Another way for emission of electron is
42
hopping process, which is a kind of tunneling process in a short range.
It should be noted here that the P-F conduction by the P-F emission is closely
related to the oxide film thickness while the Schottky conduction by the Schottky
emission isn’t related to that, as far as the equal oxide field is concerned.
Figure 2.9 Thermionic Conditions (Poole-Frenkel Condition) [2.8]
Figure 2.10 Restoring force on escaping electron [2.9] (a) Schottky effect. (b) Poole-Frenkel effect.
Trap 1
Trap 2
Energy
x
∆ΦPF = βPFEOX1/2
ΦS = Φm + ∆ΦPF
Thermionic Conduction (P-F)
Φm Φm(x)
x0
Trap 1
Trap 2
Energy
x
∆ΦPF = βPFEOX1/2
ΦS = Φm + ∆ΦPF
Thermionic Conduction (P-F)
Φm Φm(x)
x0
TrapCharge
ZZZ
ImageCharge
Metal Surface
(a) (b)
TrapCharge
ZZZ
ImageCharge
Metal Surface
(a) (b)
43
Fig. 2.10 shows the restoring force in both Schottky and P-F effect, which comes
from Coulomb interaction between escaping electron and a positive charge [2.9]. The
restoring force is due to electrostatic potential that makes electrons move back to its
equilibrium position. Although the restoring force is the same, they differ in the positive
image charge is fixed for the P-F barriers but mobile with Schottky emission. This
results in a barrier lowering twice as great for the P-F effect.
2/12/1
0
3
EEqPF
iPF β
επεφ =⎟⎟
⎠
⎞⎜⎜⎝
⎛=∆ (2.11)
2/12/1
0
3
4EEq
SKi
SK βεπε
φ =⎟⎟⎠
⎞⎜⎜⎝
⎛=∆ (2.12)
In that the electrons have enough energy to go over the energy barrier and travel in
the conduction band with a mobility m which is dependent on the scattering with the
lattice, the general expression of the bulk current is expressed by
ExqnJ µ)(= (2.13)
The concentration of free carrier in the insulator is following.
( )⎟⎠⎞
⎜⎝⎛ −−=
kTEEq
Nn Fcc exp (2.14)
Since Ec-EF is equal to effective trap barrier height including barrier lowering
effect described by Eq. (2.11), the effective barrier height and governed by the P-F
emission is written by following.
2/1EEE PFSKPFSKFc βφφφ −=∆−=− (2.15)
EEkTq
kTqNJ PF
SKc µβ
φ⎟⎠⎞
⎜⎝⎛⎟
⎠⎞
⎜⎝⎛−= 2/1expexp (2.16)
44
2.2.2.3 Fowler-Nordheim Tunneling Effect
F-N tunneling occurs when electrons tunnel into the conduction band of the oxide
layer. Fig. 2.11 (a) shows F-N tunneling of electrons from the silicon surface inversion
layer. The complete theory of F-N tunneling is rather than completed. For the simple
case where the effects of finite temperature and image-force barrier lowering are
ignored the tunneling current density is given by [2.10]
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛−=
qEm
hEqJ OX
OX h324
exp8
2/3*3 φφπ
(2.17)
Here, h is Plank constant, q is electric charge, E is electric field in the oxide, fOX is
barrier height of the oxide.
(a) (b)
Figure 2.11 (a) F-N tunneling and (b) direct tunneling
Ec
Ec
Ev
Ev
electron
Ec
Ec
Ev
Ev
electron
Ec
Ec
Ev
Ev
electron
Ec
Ec
Ev
Ev
electron
45
2.2.2.4 Image-Force Effect
The abrupt changes in potential at the metal-insulator or insulator-semiconductor
interface are physically unrealistic, since abrupt changes in potential imply infinite
electric field. The potential changes gradually as a result of the image-force. When
electron is at a distance x from the metal, a positive charge will be induced on the metal
surface, which is called image charge. The force of emission between the electron and
the image charge is equivalent to the force that would exist between the electron and an
equal positive charge located at –x. This attractive force is called the image-force given
by [2.11].
2
2
16 xqF
πε−
= (2.18)
Here, q is electron charge and ε is the permittivity of the insulator. From the (Eq.
2.18), one can realize that attractive force is inversely proportional to the dielectric
constant of the film, so that in the high-k film, the effect of image-force will be small. It
is worth commenting that the dielectric constant in the image-force equation is the high
frequency constant for the electrode-limited conduction case, since electron spend only
an extremely short time in the immediate vicinity of the surface in the course of carrier
emission [2.12].
2.2.3 Threshold Voltage
As the MOSFET is the fundamental switching devices in the LSI circuits, the
threshold voltage Vth is an important parameter of the MOSFET. The threshold voltage
can be determined by plotting Ids versus Vg at low drain voltage, typically 50-100mV, as
shown in Fig. 2.12 The extrapolated intercept of the linear portion of the Ids versus Vg
curve with the Vg –axis gives the Vg value. It needs to regard the point of slope because
46
the threshold voltage varies the point of Ids - Vg slope. It is commonly used the point of
slope on the Ids - Vg curve by a maximum in the transconductance, fit a straight line to
the Ids - Vg curve at that point and extrapolate to Ids = 0, as shown in Fig. 2.12 [2.13,
2.14].
-1 -0.5 0.50
140
120
100
80
60
40
20
0
Dra
in C
urre
nt [µ
A]
Gate Voltage [V]
L/W=2.5µm/50µm
Vd=50mV
Vth ID,max
gm,max Transconductance[µS]
250
200
150
100
50
0
Figure 2.12 Threshold voltage determined by linear extrapolation [2.13, 2.14]
2.2.4 Subthreshold Slope
As shown in Fig. 2.12, the drain current rapidly approach to zero below the
threshold voltage on a linear scale. On a logarithmic scale, however, the drain current
remains non negligible level even below the Vth. This is because the inversion charge
abruptly does not to drop zero. The slope is usually expressed as the subthreshold slope
(S.S) in Fig. 2.13. This value is that gate voltage necessary to change the drain current
by one decade, and given by
47
( )⎟⎟⎠
⎞⎜⎜⎝
⎛+=⎟
⎟⎠
⎞⎜⎜⎝
⎛=
−
ox
dm
g
ds
CC
qkT
dVIdS 13.2log
1
10 (2.19)
where k is a Boltzmann’s constant, T is temperature, q is a electronic charge, Cdm is a
depletion-layer capacitance. If the interface trap density is high, the subthreshold slope
may be graded. Because the capacitance attributed to the interface trap is in parallel
with the depletion-layer capacitance.
Figure 2.13 Definition of subthreshold slope (SS)
2.2.5 Mobility Extraction Technique ~Split C-V Measurement~
The effective inversion layer mobility in MOSFET is a very important parameter
for device analysis, design and characteristics. As the effective inversion mobility shows
sensitivity to device properties or interface properties, it can be also used to probe the
high-k gate dielectrics properties.
The effective mobility, µeff, is defined in terms of the measurement of drain current,
10-4
10-5
10-6
10-7
10-8
10-9
10-10-0.5 0 0.5 1.0 1.5
Gate voltage (V)
Dra
in c
urre
nt (A
)
S.S
Vd = 50mV
48
Id, of a MOSFET at low drain voltage, Vd, in the linear region as [2.15]
invd
invd
deff Q
gWL
QVI
WL 11
⋅⋅=⋅⋅=µ (2.20)
where gd = Id/Vd is the channel conductance, Qinv is the inversion layer charge. The
channel conductance is calculated from differential Id-Vg measurements at 50 mV and 1
V as shown in Fig. 2.14. For accurate extraction of effective mobility, accurate value of
Qinv must be used in Eq. (2.20). A Split C-V measurement is one of the extraction
techniques for inversion layer charge accurately. Fig. 2.15 represents the Split C-V
measurement arrangement. The inversion layer charge is obtained from the voltage
integral of a gate-channel capacitance as shown in Fig. 2.16. The inversion layer charge
Qinv can be written as [2.14]
( )∫ ∞−= gV
gggcinv dVVCQ (2.21)
where Cgc is the gate-to-channel capacitance [2.16]. Similarly, the depletion layer charge
Qb is also obtained due to integrate the gate-body capacitance, Cgb , from flatband
voltage toward the inversion as shown in Fig. 2.17.
( )∫= g
FB
V
V gggbb dVVCQ (2.22)
The effective electric field Eeff can be expressed as [2.4]
( )binvSi
eff QQE += ηε1 (2.23)
where η are 1/2 for electrons and 1/3 for holes.
49
Figure 2.14 Id-Vg measurements at Vd of 50mV and 1V
p-SiDS
G
B
S/D
(a)
p-SiDS
G
B
S/D
(b)
Figure 2.15 Configuration used for the measurement of (a) gate-to-channel, (b) gate-to-body capacitance
200
100
150
0-0.5 0 0.5 1.0 1.5
Gate voltage (V)
Dra
in c
urre
nt (µ
A)
Vd = 1 V
Vd = 50 mV
L/W = 2.5/50µm
50
Figure 2.16 Gate-to-channel capacitance of nMOSFET [2.14]
Figure 2.17 Gate-to-body capacitance of nMOSFET [2.14]
0Gate Voltage [V]
1 2-2 -1
400
350
300
250
200
150
100
50
0
Cap
acita
nce
[fF]
L/W=2.5µm/50µm
Qinv
Inversion C-V
0Gate Voltage [V]
-2 -1
400
350
300
250
200
150
100
50
0
Cap
acita
nce
[fF]
L/W=2.5µm/50µm
-3
Accumulation C-V
VFB
Qb
51
2.2.6 Charge Pumping Methods
Inversion layer is formed in the surface region under the gate oxide between the
source and drain and is crucial for current conduction in a MOSFET. Hence, the carriers
in the inversion layer are strongly affected by the gate oxide-Si substrate interface
properties. In addition, as the high-k gate dielectrics is not a thermally-oxidized film but
a deposited film, the evaluation of interface properties between the high-k gate
dielectrics and Si substrate is crucially importance.
The charge pumping method is one of the sensitive methods for the characteristics
of the interface trap density which is located at the high-k gate dielectrics-Si substrate
interface [2.17]. Figure 2.18 shows the circuit diagram of the charge pumping
measurement. The MOSFET gate is connected to a pulse generator. The MOSFET
source and drain are tied together and slightly reverse biased. The time varying gate
voltage is sufficiently amplitude for the surface under the gate to be driven into
inversion and accumulation as shown in Fig. 2.19. The rise and fall times tr and tf are
fixed value, 100nsec. The charge pumping current which due to recombination
processes at the interface defects is measured at the substrate. The interface trap density,
Nit, is written as
qfAI
N cpit = (2.24)
where q is the elementary charge, f is the frequency, A is the channel area. The
waveforms can be constant vamp and pulsing with varying the base voltage from
inversion to accumulation as in Fig. 2.20 (a) and Fig. 2.20 (b) represents the charge
pumping current with varying the base voltage from inversion to accumulation. The Icp
in the Eq. (2.24) is used for the maximum Icp value as show in Fig. 2.20 (b).
52
p-SiDS
G
Icp
Vr
Vtop
Vbase
Pulse generator
Figure 2.18 Measurement circuit diagram of charge pumping method [2.17]
A
Vth
VFB
B
trtL tH tf
accumulation
A
B
inversion
Figure 2.19 Sweeping between inversion and accumulation
53
VFB
VTh
VAmp
a
b
c
d
e
(a)
Icp
Vbase
a
b
c
d
e
Strong accum.
Strong inversion
Week inversion
Week accum.
Depletion
(b)
Figure 2.20 (a) Base voltage for charge pumping and (b) charge pumping current versus base voltage
Fig. 2.21 shows the band diagrams for changing the interface from accumulation
to inversion under the action of periodic gate pulses. The interface traps are filled with
electrons from source/drain during tr and the electrons in traps empty into substrate
during tf.
54
1
accumulation
A
B
4
e- in traps to substrate
3
inversion
ramp down
2
ramp up
e- from source/drain to traps
Isub = q*A*Nit*f
Figure 2.21 Band diagrams applied periodic gate pulses
2.2.7 XPS Measurement
XPS (X-ray Photoelectron Spectroscopy), also known as the Electron
Spectroscopy for Chemical Analysis (ESCA), is one of the useful methods to evaluate
chemical binding state in the bulk, at the surface, or at the interface. Figure 2.22
explains the principle of XPS. Samples were irradiated with X-ray and the emitted
photoelectrons with kinetic energy KE were detected. Measured KE was given by
KE = hν － BE － φs (2.25)
where hν is the photon energy, BE is the binding energy of the atomic orbital from
which the electron generates and φs is the spectrometer work function. The binding
energy is the minimum energy needs for breaking the chemical bond of molecule and is
55
inherent in each bond of molecule. Thus, the binding states can be identified by the
positions of the binding energy which the peak appears. In the case that the peak
position was different from the expected position, the chemical bond states were
discussed considering the amount of shift to higher or lower energy side.
Figure 2.22 Principle of XPS measurement.
Conventional XPS techniques with low excitation energies are surface-sensitive
due to short inelastic mean-free-paths (IMFPs), and it is difficult to obtain information
on the bulk electronic structures which are closely correlated with the characteristics of
the intrinsic materials. In this study, Hard X-ray Photoemission Spectroscopy (HX-PES)
is performed at Super Photon ring- 8 GeV (SPring-8). SPring-8 is the one of the world’s
largest radiation facilities. The advantages of SPring-8 over average XPS equipments
are the high-brightness of radiation which is about a hundred thousand times as high as
normal X-ray and the high radiation energy of 8 keV.
56
2.2.8 Atomic Force Microscopy
Atomic Force Microscopy (AFM) enables to measure surface morphology by
utilizing force between atoms and approached tip. The roughness of sample surface is
observed precisely by measurement of x-y plane and z. Fig. 2.23 shows the principle of
AFM. Tip is vibrated during measurement, and displacement of z direction is detected.
This method is called tapping mode AFM (TM-AFM). Resolution limit for normal
AFM is 5~10nm depending on distance between surface and tip. On the other hand,
resolution limit for TM-AFM is depended on size of tip edge.
Figure 2.23 Schematic diagram of AFM Principle
X and Y axis
Monitor
ComputeZ axis
Scanning system
Servo system
Z axis control
Sample
Cantilever
Photo sensor
Laser
Piezoscanner
X and Y axis
57
Reference
[2.1] W. Kern and D. A. Puotinen, RCA Review, 31 (1970) 187.
[2.2] Dieter K. Schroder, Semiconductor Material and Device Characterization 3rd
Edition, John Wiley & Sons, Inc., 2005.
[2.3] J. R. Hauser, and K. Ahmed, “Characterization of Ultra-Thin Oxides Using
Electrical C-V and I-V Measurements,” Proc. AIP Conf., pp.235-239, 1998.
[2.4] S. M. Sze, and K. K. Ng, Physics of Semiconductor Devices 3rd Edition, John
Wiley & Sons, Inc., 2007.
[2.5] S. M. Sze, Physics of Semiconductor Devices 2nd Edition, John Wiley & Sons Inc.,
1981.
[2.6] H. Watanabe, N. Ikarashi, and R. Ito, Appl. Phys. Lett., 83 (2003) 3546.
[2.7] J. G. Simmons, Phy. Rev. 155(3) (1967) 657.
[2.8] K. Yongshik, Doctor thesis ‘Analysis of Electrical Conduction in Rare Earth Gate
Dielectrics’ (2005).
[2.9] J. R. Yeargan and H. L. Taylor, “The Poole-Frenkel Effect with Compensation
Present”, J Applied Physics, 39[12] (1968) 5600.
[2.10] Y. Hagimoto, H. Fujioka, M. Oshima, and K. Hirose, Appl.Phys Lett., 77 (2000)
4175
58
[2.11] S. M. Sze, Physics of semiconductor devices, John Wiley & Sons Inc., 2ed, 1986
[2.12] G. Shang, P. Peacock, and J. Robertson, “Stability and band offsets of
nitrogentated high-dielectric-constant gate oxides,” Appl. Phys. Lett., 84(1), pp.206-08
(2004).
[2.13] Dieter K. Schroder, Semiconductor Material and Device Characterization 3rd
Edition, John Wiley & Sons, Inc., 2005.
[2.14] T. Kawanago, Doctor thesis ‘A Study on High-k / Metal Gate Stack MOSFETs
with Rare Earth Oxides’ (2010)
[2.15] J. R. Hauser, “Extraction of Experimental Mobility Data for MOS Devices,”
IEEE , Trans. Electron Devices, 43[11] (1996) 1981.
[2.16] S. Takagi, and M. Takayanagi, Jpn. J. Appl. Phys., 41[4B], (2002) 2348.
[2.17] G.. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, “A
Reliable Approach to Charge-Pumping Measurements in MOS Transistors,” IEEE Trans.
Electron Devices, 31[1], (1984) 42.
59
Chapter 3 Electrical Properties of
Rare-Earth Oxides 3.1 Introduction 3.2 Interfacial Reaction
3.2.1 Formation of SiO2 interfacial layer 3.2.2 Formation of the Silicate Layer
3.2.2.1 Electrical Properties of La2O3 Layered Device 3.2.2.2 Electrical Properties of Tm-oxide Layered Device.
3.3 Generation of Charged Defects 3.4 Summary of RE-oxides Properties 3.5 Summary and Conclusion
60
3.1 Introduction
Rare earth (RE) oxides are regarded as potential candidates for high-k gate
dielectric in the future high-k gate stack technology because of their ability to form
‘direct contact’ with Si substrate. Although basic electrical properties (dielectric
constant, band gap, Si–O–RE bond property and so on) of RE-oxides have been
reported in various studies [3.1-3.6], reports about their application on MOSFETs gate
insulator aiming for the ‘direct contact’ were limited [3.7]. Therefore, we carried out
experiments for various RE oxides to obtain the ‘direct contact’ concept in MOSFETs.
In this chapter, the results of these experiments are described. At first, the status of
silicate growth at the Si interface is described for various RE-oxides; La-, Ce-, Pr-, Nd-,
Eu-, Gd-, Tm. Then, the interfacial electric properties such as fixed charge and interface
state densities are examined in MOS structures. Finally we have chosen the optimum
RE-oxide based on experimental results.
Table 3.1 shows dielectric constant and bandgap values for various RE-oxides
obtained from the literatures [3.1-3.6]. The dielectric constant values are those obtained
by the evaluation of the capacitance of MOSFETs using RE-gate oxides. On the other
hand, the bandgap values are those for the bulk and not for the thin gate film, since there
are not so many publications for the bandgap measurement of various RE oxide thin
gate film. In terms of the dielectric constant and bandgap values, La2O3 seems to be an
optimum material for achieving ‘direct contact’ high-k gate insulator.
61
Table 3.1 Properties of RE-oxides [3.1-3.6]
3.2 Interfacial Reaction
Figure 3.1 shows Si 1s spectra of XPS measurements for W(8nm)/RE-oxide(~4
nm)/Si stacked film samples (RE: La, Ce, Pr, Nd, Eu, Gd, Tm). The thickness of the W
gate film was made thin in this case in order for the X-ray easily penetrate trough the W
film. The annealing condition of the samples was at 500 oC for 30min (F.G ambient). In
the measurements, the peak spectrums appeared in 1841-1844 eV regions. The peak in
this reason are designated to be those of RE silicates, and separated from the SiO2 peak
which is located around 1844 eV. The Si-rich silicate phase appears around 1843 eV and
the RE-rich silicate phase appears around 1841.5 eV [3.7-3.9]. The peak intensity
corresponds to the amount of silicate formation.
In Fig. 3.1, slicate formation is significantly larger for Gd2O3 and EuOX cases,
judging by the peak intensity which is estimated from the infrared absorption peak
height of Si–O–Ln bond. Those materials that result in excess silicate formation will be
not suitable for EOT scaling purposes. La2O3 and Ce2O3 were the following material in
5.4-Tm2O3
5.410Gd2O3
4.422EuOX
4.812-14NdOX
4.014PrOX
2.3~30CeOX
5.527La2O3
Bandgap(eV)
Dielectric constantMaterial
5.4-Tm2O3
5.410Gd2O3
4.422EuOX
4.812-14NdOX
4.014PrOX
2.3~30CeOX
5.527La2O3
Bandgap(eV)
Dielectric constantMaterial
62
terms of large silicate formation. La silicate composition can range from a La-rich
silicate phase to a Si-rich silicate phases [3.8]. The dielectric constant of La-rich silicate
is higher than that of Si-rich silicate [3.7]. Therefore, it is necessary to suppress the
formation of Si-rich silicate in order to prevent an increase in EOT.
Large amount of Si-rich silicate seems to be formed in the CeOX case. However,
the peak is close to that of SiO2 and thus, there is a need to confirm the whether SiO2 or
silicate is formed. In fact, the formation of SiO2 interfacial layer at CeO2/Si-substrate
was also reported [3.10].
Figure 3.2 shows the C-V characteristics of MOS capacitors with physical
thickness of RE-gate oxide around 4 nm. The gate electrode is a 50 nm thick W film.
EOT values were obtained from the C-V curve using CVC fitting method [3.11] as
shown in Table 3.2. The amount of silicate formation estimated by the XPS, almost
exactly corresponds to the EOT values calculated by the C-V curve. In terms of
obtaining small EOT on Si, TmOX, NdOX, PrOX are found to be the best, and Gd2OX
and EuOX are the worst.
63
Figure 3.1 Si 1s photoelectron spectra measured for seven kinds of RE oxides formed on the Si substrate.
Figure 3.2 C-V characteristics for all kind of MOS capacitors and estimated EOT values
1845 1844 1843 1842 1841 1840Binding energy (eV)
1839
La2O3
TmOX
PrOX
CeOX
NdOX
Gd2O3
EuOX
Si1s
Inte
nsity
(a.u
.)
3.0
2.0
1.0
0-2.5 -1.5 0.5 1.0 1.5
Gate voltage (V)
Cap
acita
nce
(µF/
cm2 )
La2O3
TmOX
PrOX
CeOX
NdOX
Gd2O3
EuOX
2.07Gd2O3
0.86TmOX
2.05EuOX
0.95NdOX
1.05PrOX
1.32CeOX
1.32La2O3
EOT (nm)insulator
2.07Gd2O3
0.86TmOX
2.05EuOX
0.95NdOX
1.05PrOX
1.32CeOX
1.32La2O3
EOT (nm)insulator
Table 3.2 EOT values of all kind of MOS capacitors
64
As shown Fig. 3.2, sample with EuOX gate oxide insulator showed a large hump on
the C-V curve near the Vfb and also a small hysteresis. In addition, PrOX and NdOX
showed a small hump. This hump is one of the interfacial state indexes. Larger hump in
C-V curve indicates a large interface state density and thus degradation of the interfacial
property. Except the case of EuOX, the hysteresis in C-V curve was small to be
recognized in the plot of Fig. 3.2.
TEM analysis was used to clarify the reaction of RE-oxide with Si-substrate after
annealing. Figure 3.3 shows the TEM image of the capacitors with La2O3, TmOX CeOX.
The silicate layer was formed in all there samples, however, the thickness of the silicate
layers was not the same. The La-silicate thickness was larger than that of Tm-silicate, as
expected from the XPS and C-V measurements. Resultant Tm-silicate thickness is much
smaller compared to overall oxide thickness. In the case of CeOX, SiO2 layer was
formed at CeOX/Si interface in addition to a silicate layer above as shown Fig. 3.3 (c).
Figure 3.3TEM image
W/Ce-oxide/Si
500oC_30min (F.G)
W/Tm-oxide/Si
500oC_30min (F.G)
TmOx
Tm-silicate
W/La-oxide/Si
500oC_30min (F.G)
W/La-oxide/Si
500oC_30min (F.G)
CeOx
SiO2
Ce-slilicate
65
3.2.1 Formation of SiO2 interfacial layer
SiO2 layer seems to be formed at the CeOX/Si substrate interface from the TEM
image. It is reported that when the Ce3+ and Ce4+ exist in CeOX film, SiO2 and
Ce-silicate can be formed [3.12]. The formative mechanism of SiO2 and Ce-silicate
were shown as equation (3.1) and (3.2). Figure 3.4 (a) shows Ce 3d5/2 XPS spectra on
the CeOX samples made with the same condition as those used for Si 1s spectra
measurements described in the previous section. It was found that the film involves both
Ce3+ and Ce4+ states. Therefore, according to the chemical reaction shown in equations
(3.1, 3.2), both SiO2 and Ce-silicate layers were formed as shown in Fig. 3.4 (b). The
SiO2 layer is formed through reaction with oxygen atoms. Therefore, rigorous control of
oxygen concentration in film is required to suppress the formation of SiO2 layer [3.12].
In this fabrication device, oxygen concentration is not controlled. CeOX film is not an
appropriate oxide to deposit on Si substrate because direct contact with Si cannot be
achieved.
4CeO2 + Si +O2 → 2Ce2O3 + SiO2 (3.1)
2Ce2O3 + Si +nO2 → 2CeO2 + Ce2SiO5 (3.2)
66
Figure 3.4 Ce 3d 5/2 core level spectra and formation of SiO2
3.2.2 Formation of the Silicate Layer
La-silicate film is about 2 nm in the La2O3 case. Thickness of the silicate depends
on the generation of radical oxygen atoms in film [3.13]. Figure 3.5 shows the
schematic illustration of oxygen atom concentration in La2O3/silicate gate oxide. The
oxygen atoms show exponential decay with a characteristic length of λm within the
La2O3 layer, creating radical oxygen atoms by catalytic effect. Therefore, the
concentration of radical oxygen atoms at La2O3 /silicate interface, C1, is dependent on
the oxygen atoms, C0, at W/ La2O3 interface. As W gate in this experiment still contains
enough oxygen atoms after annealing, C0 can be treated as a constant. On the other hand,
radical oxygen atoms generated in the La2O3 layer diffuses into silicate layer with a
deactivation process, showing an exponential decay in the silicate layer. Therefore, the
concentration of radical oxygen atoms, C(z), in the silicate layer, at thermal equilibrium,
can be expressed.
If the generation of radical oxygen atom is large, the silicate thickness becomes
thicker and low-dielectric constant layer is also formed. Therefore, generation of radical
894 892 890 888 886 884 882 880
Binding energy [eV]
Ce4+
Ce3+Ce 3d5/2
datafitting
4CeO2+Si+O2 → 2Ce2O3+SiO2
2Ce2O3+Si+nO2→ 2CeO2+Ce2SiO5
SiSiO2
Ce3+Ce4+
Ce-oxide
Ce2SiO5
(a) Ce 3d 5/2(b)
Inte
nsity
(a.u
.)
67
oxygen atoms should be supressed.
Figure 3.5 Schematic illustration of concentration profile of oxygen atoms and oxygen radicals in La2O3
and silicate layers [3.13].
3.2.2.1 Electrical Properties of La2O3 Layered Device
In NdOX, PrOX and TmOX devices, amounts of silicate layer may be smaller than
that of La2O3. However, the bandgap of NdOX and PrOX is smaller than that of La2O3
(Table 3.1). Small bandgap usually results in leakage current increase for the gate
insulator film. Also, the dielectric constant of NdOX and PrOX are lower than that of the
La2O3. Hence, the electrical properties of MOS device using La2O3 insulator have been
investigated in our laboratory.
The dielectric constants of La2O3 and the formed La-silicate, La-rich and Si-rich,
are experimentally measured to be 24 and 14, 8, respectively [3.14]. Figure 3.6 shows
good device characteristics for a MOSFET with La2O3 gate oxide. Therefore, this
material is useful for direct contact on Si substrate.
0 TLa O
La2O3 silicateW
O*O
Si
λm λa
C1
C0
2 3TLa O + Tsilicate2 3
zOxy
gen
conc
entr
atio
n
68
Figure 3.6 Electrical properties of La2O3 based layered devices
On the other hand, the electrical properties of TmOX material are still not known
compared to other materials. To estimate the best RE-oxide for direct contact with Si,
evaluation of the properties in TmOX material is needed.
3.2.2.2 Electrical Properties of Tm-oxide Layered Device
TmOX can form very thin interfacial layer. This means that the generation of
radical oxygen atoms is so small. Hence, this material might be very useful for EOT
scaling. The electrical properties of this material are still not known compared to other
materials. Therefore, we investigated the TmOX insulator. Figure 3.7(a) shows the Si 1s
photoelectron spectra arising from the samples at as-deposited state and those measured
after annealing. The data (marked in circles) can be well fitted using two spectra: one
spectrum with small intensity at peak-bonding energy (BE) of 1842.5 eV, the other
69
spectrum at BE of 1838.9 eV. As the electronegativity of Tm atoms (χTm=1.25) is
smaller than that of Si atoms (χSi=1.90) [3.15], the BE of photoelectrons arising from
Tm–O–Si bond arrangement should be lower than the BE from Si–O–Si bonding. This
can be explained by the second nearest-neighbor effect [3.16]. Indeed, the BE of
photoelectrons arising from SiO2 is reported to be approximately 4.8 eV higher than the
substrate peak, [3.17, 3.18] which is larger than the peak shift of 3.6 eV that we
observed in our experiment. Therefore, the detected photoelectrons are probably present
due to the formation of Tm–O–Si bonding. The number of photoelectrons arising from
the silicate layer increased by 28% after annealing, which indicates a growth of the
Tm-silicate due to PMA. We assume that the composition of the silicate is Tm2SiO5,
which is a typical composition of rare earth silicates. We also assume that the density is
5.78 g/cm3 and that the inelastic mean free paths in the Tm-silicate and the Si substrate
are 8.7 and 10.5 nm, respectively [3.19]. Then, we can estimate that the thicknesses of
the silicate layers as 0.69 and 0.88 nm, respectively, for as-deposited and annealed
samples, where the values are consistent with the thickness obtained from TEM
observations [3.20]. The growth of the Tm-silicate layer is not desirable; in contrast to
the growth of an approximately 1.5 nm thick silicate formed with La2O3 for the same
annealing condition [3.13]. Figure 3.7(b) shows the Tm 3d5/2 spectra at the as-deposited
and annealed samples. The complicated shape of the spectra is due to the multiplet
splitting observed for rare earth elements [3.21]. The fact that we observe only minor
change in the spectra also supports the low reactivity of Tm2O3 and Si substrate.
Therefore, we may speculate that Tm2O3 is appropriate for the gate dielectric in terms of
EOT scaling.
70
Figure 3.7 (a) Si 1s photoelectron spectra for Tm2O3 based layered device with and without annealing.
The amount of Tm–O–Si bonds increases by 28% after annealing. (b) Tm 3d 5/2 photoelectron spectra
exhibited little difference after annealing.
The capacitance-voltage (C-V) characteristics of the 2 nm thick Tm2O3 capacitor
measured before and after PMA are shown in Fig. 3.8(a). Although we observed a
1844 1842 1840 1839Binding energy (eV)
1843 1841
Inte
nsity
(a.u
.)
Sisub.
Sisub.
hν=7940 eV, Si 1sas deposited
500 oC annealed
Tm-O-Si
Tm-O-Si
1844 1842 1840 1839Binding energy (eV)
1843 1841
Inte
nsity
(a.u
.)
Sisub.
Sisub.
hν=7940 eV, Si 1sas deposited
500 oC annealed
Tm-O-Si
Tm-O-Si
data
data
1485 1480 1475 1470 1465 1460
500oC annealed
Binding energy (eV)
hν=7940 eV, Tm 3d5/2
before annealing
Inte
nsity
(a.u
.)
(a)
(b)
71
decrease in the capacitances at high gate voltage because of the excess leakage current,
[3.22] we can estimate the EOT values as 0.45 and 0.55 nm using the North Carolina
State University CVC program [3.11]. The cross-sectional TEM images of the measured
capacitors also showed that there are no distinct changes in the thickness or in the
contrast of the interface layer [Fig. 3.8(b)]. The thin bright contrast that we see next to
the substrate surface is due to the Tm-silicate layer. For the silicate layer thickness of
0.88 nm, the dielectric constants of the Tm-silicate and the Tm2O3 layer can be roughly
calculated to be 12 and 18, respectively.
-1.0 -0.5 0.5 1.00
5.0
0
Gate voltage (V)
Cap
acita
nce
dens
ity (µ
F/cm
2 )
as deposited(EOT=0.45 nm)
500oC annealed(EOT=0.55 nm)
100kHz
4.0
3.0
2.0
1.0
CVC fitting
∆VFB ~ 0.05 V
∆VFB ~ 0.01 V
(a)
72
Figure 3.8 (a) C–V characteristics for MOS capacitors with 2 nm-thick-Tm2O3 before and after annealing.
Both samples exhibit small hysteresis (∆Vfb). (b) TEM images of the capacitors before and after
annealing.
The leakage current density (Jg) as a function of the gate voltage is shown in Fig.
3.9(a) for the Tm2O3/Si capacitors with Tm2O3 thicknesses as a parameter. Two leakage
current mechanisms governed by Schottky and Poole–Frenkel (PF) conductions are
observed when the EOT is over 1.29 nm. Energy of 0.92 eV can be extracted from
Schottky conductions for Tm2O3 conduction band offset with respect to the Si
conduction band. At an EOT below 1 nm, the tunneling current becomes the major
component in the leakage current.
1nm
500oCannealed
Tm2O3
Tm-silicate
asdeposited
EOT = 0.55 nmEOT = 0.45 nm
Si substrate
W
(b)
73
Figure 3.9 (a) Jg–Vg characteristics of MOS capacitors with various Tm2O3 thicknesses. Two conduction
mechanism, Schottky and PF conduction were observed. (b) Jg vs EOT relation at a gate voltage of 1 V.
102
101
100
10-1
10-2
10-3
10-4
10-5
10-6
10-7
Leak
age
curr
ent d
ensi
ty (A
/cm
2 ) 103
104
0.5 0.9 1.1 1.3EOT (nm)
0.7 1.5 1.7 1.9
ITRS roadmap
Vg = 1V
La2O3
Tm2O3
0 0.5 1.0 1.5 2.0 2.5 3.0
103
101
10-1
10-3
10-5
10-7
EOT=0.53nm
0.68nm
0.74nm
1.29nm
1.56nm1.85nm
Gate voltage (V)
Leak
age
curr
ent d
ensi
ty(A
/cm
2 )
Schottkyconduction
P-F conduction
(a)
(b)
74
Jg at a gate voltage of 1V is plotted as a function of EOT in Fig. 3.9(b). The
existence of two slopes in Fig. 3.9 can be understood to reflect the addition of the
tunneling component to the Schottky conduction below an EOT of 0.74 nm. Here, Jg of
capacitors with La2O3 gate dielectrics are also plotted as references. We see that the Jg of
the Tm2O3 gate dielectric is advantageous for the Jg reduction, compared to La2O3.
Moreover, the dependence of Jg on EOT obtained for Vg of 1V is rather promising when
compared with the ITRS roadmap requirements, and this may also be advantageous for
further EOT scaling [3.23].
The transfer characteristics of a 2 nm thick Tm2O3 gated nFET with gate length of
2.5 µm and width of 50 µm at a drain voltage of 50mV are shown in Fig. 3.10(a). The
EOT of the FET was estimated as 0.55nm by gate to channel split C–V measurement. A
subthreshold slope of 84 mV/decade indicates an interface state density (Dit) of 1.6×
1013 cm-2/eV. The dependence of the effective electron mobility (µeff) of the FET on the
effective electric field (Eeff) is shown in Fig. 3.10(b). The peak value of µeff and the
value of µeff at an Eeff of 1 MV/cm were as low as 106 and 90 cm2/Vs, respectively,
indicating the existence of carrier scatterings in the gate stack [3.24]. On the hand, the
degradation in the µeff at low Eeff might be due to the presence of high Dit and the
positive and negative fixed charges in the oxide estimated from the EOT dependent Vfb.
On the other hand, the degradation in the µeff at high Eeff might be due to the
non-uniformity in thickness of the thin silicate layer [3.25, 3.26]. Nevertheless, it would
be interesting to investigate the recent charged defect compensation processes to
scrutinize the intrinsic performance of Tm2O3 for gate dielectric applications [3.27].
75
Figure 3.10 (a) Id–Vg and (b)µeff characteristics of a nFET with an EOT of 0.55nm.
Tm-oxide is a useful material for EOT scaling. However, interfacial state is worse
than La2O3 material. Figure 3.11 shows mobility and Dit values in La2O3 and Tm2O3
devices at the same process condition. The mobility and interfacial state is very
important factor in direct contact with Si. Therefore, we can conclude that La2O3 is an
optimal material to be deposited on Si substrate than Tm2O3.
0.0E+00
4.0E-05
8.0E-05
1.2E-04
1.6E-04
-0.8 -0.6 -0.4 -0.2 0 0.2 0.41.0E-08
1.0E-06
1.0E-04
1.0E-02
1.0E+00
0.6
Vg (V)
I d(A
)SS = 84 mV/decVth = -0.35 V
W/L = 50/2.5 µmVd = 50 mV
1
1×10-2
1×10-4
1×10-6
1×10-8
1.6×10-4
1.2×10-4
8×10-5
4×10-5
0
Id(A
)
120
100
80
60
40
20
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Effective field (MV/cm)
Effe
ctiv
e m
obili
ty (c
m2 /V
s)
EOT=0.55nm
(a)
(b)
76
Figure 3.11 (a) mobility-EOT and (b) Dit surface potential characteristics
3.3 Generation of Charged Defects
Due to formations of interfacial layer, either silicate or SiO2, fixed charged defects
are generated in the film. These defects cause degradation in electrical properties.
Therefore, charged defects reduction is an important issue which needs to be solved. In
5×1012
-0.3 -0.2 -0.1 0
4×1012
3×1012
2×1012
1×1012
Surface potential (V)
Dit
(eV/
cm2 )
0
50
100
150
200
250
300
350
400
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2
La2O3:peak µeff
La2O3:µ[email protected]/cmTm-oxide:peak µeff
Tm-oxide:µ[email protected]/cm
EOT (nm)
µeff
(cm
2 /Vs)
(a)
(b)
77
this section, we suggest a fixed charged model to estimate the charged density in films.
Figure 3.12 shows the schematic illustrations of the fixed charge generation. In this
model, it is supposed that charges are localized especially at the interfaces when the
thickness of the gate dielectric is as thin as 4 nm [3.28]. We introduce two fixed charges
per unit area of Q0 and Q1, which are located at silicate/substrate and RE-oxide/silicate
interface, respectively. Charges might be due to the difference in the bonding nature of
oxygen atoms in the RE-oxide and those in the silicate layer; the former as charged
oxygen atoms (O2-) and the later as neutral states of oxygen atom (O0), leaving electrons
trapped at the RE-oxide/silicate interface during the reaction [3.29]. Moreover another
fixed charge, induced metal diffusion charge (Qadd), is considered as a function of
RE-oxide thickness.
Figure 3.12 Generation of fixed charges in film. The two different kind of fixed charges are generated,
which are caused by silicate formation and metal diffusion.
The flatband voltage (Vfb) of the capacitors on the EOT showed roll-off and roll-up
depending on EOT value. The shift in the Vfb is mainly caused by the fixed charges in
the gate oxide. Based on the relation of Vfb with fixed charges, the dependence of Vfb on
EOT can be expressed as
Oxide
Si
W
Oxide
silicate
Si
W
Q1
Q0 Q0
QaddOxide
Si
W
silicate
78
( ) msoxideREox
fb qEOTQEOTQV ϕε
+⋅+⋅−= −101
（3.3）
where εox is the dielectric constant of silicon dioxide, q is the elementary charge,
EOTRE-oxide is the EOT of the RE-oxide layer on top of the silicate layer, and φms is the
work function difference of the metal and Si substrate [3.28]. Here, metal induced fixed
charge density (Qadd) is introduced in addition to Q1. Figure 3.13 shows the model of all
kind of fixed charges.
Figure 3.13 Schematic illustration of position of fixed charges.
The fixed chare densities of all layered samples can be estimated by using the
proposed fixed charged model. In this work the gate insulator thickness for various
RE-oxides was changed from 2 to 18 nm and EOT and Vfb are evaluated. Fig. 3.14
(a)~(f) shows the EOT-Vfb data (plots) and fitting curve (solid line) using equation
(3.3) of La2O3, CeOX, PrOX, NdOX, GdOX, and TmOX, respectively. The estimation of
charged defect density in film (Q1) values are shown in Fig. 3.14 (g)
RE-oxide
silicate
Si
W
+
-
+ +
- - +Q1
Q0Qadd=f(z)
z
⎟⎠⎞
⎜⎝⎛=
DtzerfcCQadd 20
79
Figure 3.14 (a),(b) EOT-Vfb characteristics and estimation of fixed charged density (Q1) in La2O3 and
CeOX layered MOS capacitors
-0.1
V fb
(V)
0
0.1
-0.2
-0.3
-0.4
-0.5
-0.60 0.5 1.0 1.5 2.0 2.5 3.0
EOT (nm)
fitting
La2O3
Si
La2O3La2O3
La2O3La2O3W
WW
W
Q1= 1.3×1013 /cm2
(a) W (50 nm) / La2O3 (2~10 nm) / Si
2 ~ 10 nm
0.15
V fb
(V)
0.2
0.1
0.05
01.0 1.2 1.4 1.6 1.8
EOT (nm)
fitting
Ce-oxideQ1= -4.6×1012 /cm2
(b) W (50 nm) / CeOX (2~18nm) / Si
2 ~ 18 nm
Si
Ce-oxideCe-oxide
Ce-oxideCe-oxideW
WW
W
80
Figure 3.14 (c),(d) EOT-Vfb characteristics and estimation of fixed charged density (Q1) in PrOX and
NdOX layered MOS capacitors
Si
Pr-oxidePr-oxide
Pr-oxidePr-oxideW
WW
W
-0.1V fb
(V) 0
0.3
-0.2
-0.3
-0.4
-0.50 0.5 1.0 1.5 2.0 2.5 3.0
EOT (nm)
fitting
0.2
0.1
Pr-oxide
Q1= 1.6×1013 /cm2
(c) W (50 nm) / PrOX (2~14 nm) / Si
2 ~ 14 nm
Si
Nd-oxideNd-oxide
Nd-oxideNd-oxideW
WW
W
-0.1
V fb
(V)
0
-0.2
-0.3
-0.4
-0.70 0.5 1.0 1.5 2.0 2.5 3.0
EOT (nm)
fitting
Nd-oxide
-0.5
-0.6
Q1= 3.0×1011 /cm2
(d) W (50 nm) / NdOX (1.5~14 nm) / Si
1.5 ~ 14 nm
81
Figure 3.14 (e),(f) EOT-Vfb characteristics and estimation of fixed charged density (Q1) in GdOX and
PrOX layered MOS capacitors
Si
Gd-oxideGd-oxide
Gd-oxideGd-oxideW
WW
W
V fb
(V)
0
-0.20.5 1.0 1.5 2.0 2.5 3.0
EOT (nm)
fitting
Gd-oxide-0.1
0.1
0.2
0.3
0.4
Q1= 1.2×1013 /cm2
(e) W (50 nm) / GdOX (3~12 nm) / Si
3 ~ 12 nm
Si
Tm-oxideTm-oxide
Tm-oxideTm-oxideW
WW
W
V fb
(V) 0
-0.60.5 1.0 1.5 2.0 2.5 3.0
EOT (nm)
fitting
Tm-oxide
-0.2
0.2
0.4
0
-0.4
Q1= 1.2×1013 /cm2
(f) W (50 nm) / TmOX (1.5~14 nm) / Si
1.5 ~ 14 nm
82
Figure 3.14 (g) Estimated of fixed charged density in each films are compound
It was confirmed that the SiO2 interfacial layer is formed at CeOX/Si interface.
Therefore, negative charge might be generated at CeOX/SiO2 interface and positive
charge might be generated at RE-oxide/silicate.
On the other hand, no conclusive data for EuOX could be obtained. Figure 3.15
shows the C-V characteristics in EuOX layered devices with physical thickness as the
parameter.
1012
Fixe
d ch
arge
den
sity
(/cm
2 )
1011
1013
La2O3 CeOX PrOX TmOX NdOX GdOX
Positive charge Negative charge1014
(g)
83
Figure 3.15 CV characteristics in EuOX devices
The shape of C-V curve is largely different from ideal curve. In this section, EOT
and Vfb were estimated using CVC program by fitting the experimental curve to the
ideal curve. The correct fitting is inapplicable to those C-V characteristics. Therefore,
charged defect density in Eu-oxide layer could not be estimated. Additionally, large
hysteresis was observed for thickness EuOX film samples. EuOX single layer is not
optimal as the gate insulator for MOS device.
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0-3 -2 -1 0 1 2
Gate voltage (V)
Cap
acita
nce
(µF/
cm2 )
-2 -1 0 1 2Gate voltage (V)
-2 -1 0 1 2Gate voltage (V)
-2 -1 0 1 2Gate voltage (V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0-3 -2 -1 0 1 2
Gate voltage (V)
Cap
acita
nce
(µF/
cm2 )
-2 -1 0 1 2Gate voltage (V)
-2 -1 0 1 2Gate voltage (V)
-2 -1 0 1 2Gate voltage (V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0-3 -2 -1 0 1 2
Gate voltage (V)
Cap
acita
nce
(µF/
cm2 )
-2 -1 0 1 2Gate voltage (V)
Si
Eu-oxideEu-oxide
Eu-oxideEu-oxideW
WW
W
4nm ~
~ 18 nm 4 ~ 18 nm
84
3.4 Summary of RE-oxides Properties
The electrical properties of each rare-earth oxides were compared. Table 3.2 shows
the electrical properties of all investigate materials. The parenthetic number in dielectric
constant is an estimated value obtained by thin experiment.
Table 3.3 Electrical properties of RE-oxides
In the EuOX and Gd2O3, large interfacial layer were formed due to high reactivity
with Si. Especially, C-V characteristic of EuOX were extremely poor. In the CeOX, the
direct contact with Si substrate could not be achieved due to formation of SiO2
interfacial layer. Therefore, this oxide is also not optimal. The interfacial reaction in
PrOX, NdOX, Tm2O3/Si substrate is small. However, interfacial state density was
degraded in Tm2O3 layered devices. Although PrOX and NdOX are better for deposition
on Si, the dielectric constant and bandgap values are smaller than La2O3 material.
Additionally, interfacial state was also degraded because humps in C-V characteristics
of both PrOX and NdOX were observed. To achieve EOT scaling, both factors and their
Very small
Very small
small
Very small
Very small
Very small
Very small
Hysteresis in CV curve
-0.44
0.3
-0.22
-0.54
-0.12
0.05
-0.43
Vfb (V)
0.86
2.07
2.05
0.95
1.05
1.32
1.32
EOT (nm)
5.4
5.4
4.4
4.8
4.0
2.3
5.5
Bandgap(eV)
4.0×1011
1.2×1013
-
3.0×1011
1.6×1013
4.6×1012
1.3×1013
Charge defect(/cm2)
silicate
Large reaction
Large reaction
silicate
silicate
SiO2
silicate
Interfacial reaction
(12-18)
10
22
12-14
14
~30 (26)
27 (24)
Dielectric constant
Very small
Very small
Large
Small
Small
Very small
Very small
Hump in CV curve
Tm2O3
Gd2O3
EuOX
NdOX
PrOX
CeOX
La2O3
material
Very small
Very small
small
Very small
Very small
Very small
Very small
Hysteresis in CV curve
-0.44
0.3
-0.22
-0.54
-0.12
0.05
-0.43
Vfb (V)
0.86
2.07
2.05
0.95
1.05
1.32
1.32
EOT (nm)
5.4
5.4
4.4
4.8
4.0
2.3
5.5
Bandgap(eV)
4.0×1011
1.2×1013
-
3.0×1011
1.6×1013
4.6×1012
1.3×1013
Charge defect(/cm2)
silicate
Large reaction
Large reaction
silicate
silicate
SiO2
silicate
Interfacial reaction
(12-18)
10
22
12-14
14
~30 (26)
27 (24)
Dielectric constant
Very small
Very small
Large
Small
Small
Very small
Very small
Hump in CV curve
Tm2O3
Gd2O3
EuOX
NdOX
PrOX
CeOX
La2O3
material
85
trade-off should be taken into consideration. Therefore, La2O3 material is optimum for
direct deposition on the Si substrate.
3.5 Summary and Conclusion
In this chapter, we investigated several RE-oxides (RE elements: La, Ce, Pr, Nd,
Eu, Gd, Tm) for gate dielectric material. High reactivity with Si has been observed with
EuOX and Gd2O3 films, and SiO2-based interfacial layer has been formed for CeOX film.
Therefore, these three oxides are not suitable to achieving direct contact with Si
substrate. In PrOX and NdOX films, reaction with Si is smaller than that of La2O3.
However, band gap and dielectric constants are also smaller than that of La2O3.
Therefore, La2O3 film is better than PrOX and NdOX films as gate insulator for
achieving lower leakage current. On the other hand, TmOX shows the smallest reaction
with Si, so that formation of silicate is small thus, an EOT of 0.5 nm can be easily
achieved. However, degraded mobility and Dit characteristics have been observed
compared to La2O3 single layer device. The main reason is due to the generation of
fixed charges at RE-oxide/silicate interface. As fixed charges are located near interface,
electrical properties are degraded.
We suggested a model for estimating fixed charges in gate oxide insulator film and
evaluated the fixed charged density for each film. Fixed charge values for various
oxides are about 1011~1013 /cm2 and only CeOX material showed negative charges. By
comparing the results of all samples, we selected La2O3 as the optimal material for
direct deposition on Si.
86
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[3.18] K. Kakushima et al., Appl. Surf. Sci. 254, 6106 (2008).
[3.19] S. Tanuma, C. J. Powell, and D. R. Penn, Surf. Interface Anal. 35, 268 (2003).
[3.20] Z. H. Lu, J. P. McCaffrey, B. Brar, G. D. Wilk, R. M. Wallace, L. C. Feldman, and
S. P. Tay, Appl. Phys. Lett. 71, 2764 (1997).
[3.21] Y. A. Teterin, A. Yu Teterin, Russ. Chem. Rev. 71, 347 (2002).
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[3.22] A. Nara, N. Yasuda, H. Satake, A. Toriumi, IEEE T Semiconduct M. 15, 209
(2002).
[3.23] International Technology Roadmap for Semiconductors, http://www.itrs.net/
[3.24] S. Takagi, A. Toriumi, M. Iwase and H. Tango, IEEE T. Electron Dev. 41, 2357
(1994).
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Hiratani and S. Kimura, J. Appl. Phys. 98, 113706 (2005).
[3.26] S. Saito, K. Torii, Y. Shimamoto, S. Tsujikawa, H. Hamamura, O. Tonomura, T.
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89
Chapter 4 Consideration of Reduction
in Charged Defects ~ Theoretical Calculation and
Analysis of Experiment~ 4.1 Introduction 4.2 A Novel Capping Technique 4.3 Theoretical Study
4.3.1 First-Principles Calculation 4.3.2 Density-Functional Theory (DFT) 4.3.3 Local Density Approximations (LDA) 4.3.4 Calculation of Charge Defects
4.3.4.1 Formation Energy 4.3.4.2 Concentration of Charge Defects in La2O3
4.4 Experimental Results 4.5 Consideration of Defect-Reduction for Other Material 4.6 Summary and Conclusion
90
4.1 Introduction
We selected La2O3 material as base gate insulator in Chapter 3. One of the major
problems of the application of a La2O3 is its high concentration of charged defects,
which causes threshold voltage (Vth) shift [4.1, 4.2]. These charged defects usually
originate from the native defects such as oxygen vacancies (VO+) and interstitials (IO
-),
whose concentration strongly depends on the oxygen concentration in the insulator. The
oxygen concentration was defined the oxygen chemical potential (µO). Figure 4.1 shows
the mechanism of changing chemical potential dependence on the ambient. When a
process with reducing ambient is performed, oxygen atoms were taken out to produce
oxygen vacancies, so that oxygen chemical potential changed. On the other hand, when
oxidizing process is performed, oxygen atoms will compensate the oxygen vacancies.
As the result, oxygen vacancies are reduced. However, interstitial oxygen atoms will be
generated in the film, if excess oxidation is performed. Therefore, the oxygen chemical
potential fluctuates according to device process ambient. So, a way to fix the chemical
potential against process ambient is essential.
91
Figure 4.1 Mechanism of fixed oxygen chemical potential in La2O3 single layer
4.2 A Novel Capping Technique
For reduction of charged defects, we suggested the using CeOX material. This
material has different valence states, in which are Ce2O3 and CeO2, and called
multivalent material. The CeOX acts as an oxygen reservoir thanks to its multivalent
nature where Ce change from tetravalent to trivalent as absorbing oxygen under an
oxidation ambient, and from trivalent to tetravalent as expelling oxygen under a
reduction ambient. This contributes to having the La2O3 layer robust against the defect
formation. This scenario is schematically depicted in Fig. 4.2. Therefore, oxygen defects
in La2O3 film might be compensated by deposited CeOX on La2O3.
Oxygen chemical potential
Vo2+
Vo2+
Vo2+
Vo2+
Io2-Vo2+
Vo2+
Vo2+
Vo2+
Io2-
Vo2+
Io2-Io2-
Io2-
Io2-
Vo2+
Io2-Io2-
Io2-
Io2-
reducing process oxidizing process
negative shiftin flatband voltage
positive shiftin flatband voltage
La2O3→ La2O3 + VO2+ La2O3 + O→
La2O3 +IO2-
La2O3
La2O3
92
Figure 4.2 Mechanism of defects compensation by using CeOX
In this study, a novel capping technique for reducing charged defects in La2O3
gate dielectric is proposed. With the use of CeOX as capping material, charged defects
in La2O3 can be controlled. For comparison of capping material effects, EuOX and
PrOX are also investigated as other multivalent materials.
4.3 Theoretical Study
To this date, many theoretical calculation methods have been studied and this
accuracy has been improved. Therefore, theoretical calculation is quite useful in the
design of gate insulator with MOSFET. Consequently, in this study, the calculation was
also used for investigated high-k film structure.
In this chapter, the quantity of the fixed charge in La2O3 is investigated the
theoretical calculation. The calculation is done by using the first-principle method. Our
first-principles calculations were based on the density-functional theory (DFT) within
the local-density approximation (LDA), using the projector augmented wave
CeO2→ Ce2O3 + O
VO2- + O
Ce2O3 + O→ CeO2IO2--2e-→ O
(a) Reducing ambient (b) Oxidizing ambient
Ce2O3CeO2
Ce2O3CeO2
Vo2+Vo2+
Io2-Io2-OOrelease
La2O3
Ce2O3CeO2
Ce2O3CeO2
Vo2+Vo2+
Io2-Io2-OOabsorb
La2O3
93
pseudopotentials as implemented in the VASP code [4.3, 4.4].
4.3.1 First-Principles Calculation
Quantum mechanics provides a reliable way to calculate what electrons and atomic
nuclei do in any situation. The behavior of electrons in particular governs most of the
properties of materials. This is true for a single atom or for assemblies of atoms in
condensed matter, because quantum mechanics describes and explains chemical bonds.
Therefore we can understand the properties of any material from first-principles, that is,
based on fundamental physical laws and without using free parameters, by solving the
Schrödinger equation for the electrons in that material. This, however, is a tall order.
We rapidly run into difficulty because electrons interact strongly with each other. The
alarming consequence is that exact pencil-and-paper solutions exist only for a single
electron in simple potentials: solving the Schrödinger equation for the hydrogen atom is
a classic undergraduate task, but solving it for helium requires a computational
approach. The problem of interacting electrons in condensed matter physics, one
manifestation of the many-body problem, is the defining challenge of the subject.
Despite this difficulty, one can acquire dozens of published papers describing the
application of first-principles calculations to systems containing hundreds or thousands
of atoms and electrons, yielding accurate, quantitative information. This is a great
triumph of condensed matter science, and it has fundamentally changed the way we
approach the subject [4.5].
4.3.2 Density-Functional Theory (DFT)
Quantum physics of electrons in materials is governed by the Schrödinger equation.
94
Density-functional theory (DFT) provides a parameter-free frame-work for casting the
formidable many-electron problem to a numerically tractable form involving only the
three spatial coordinates of the N interacting electrons (as opposed to 3N in the full
solution of the Schrodinger equation).
A useful primer for designing DFT calculations had reported [4.6]. The design of
any calculation, whether using periodic boundary conditions, finite clusters or
embedding techniques, involves the choice of the exchange-correlation functional. The
choice, whether a particular flavor of local-density (LDA) or local spin-density (LSDA)
approximation, an generalized-gradient approximation (GGA), full Hartre-Fock-type
exchange, screened exchange, or a “hybrid” between a nonlocal orbital-based functional
and a density-dependent functional, defines the physical accuracy of the calculation.
The numerical accuracy of the calculation depends on such technical things as basis-set
completeness, accuracy of integration in both real and reciprocal space, convergence
criteria, etc. the model accuracy depends naturally on how faithfully the chosen
super-cell, cluster or embedding methods describe the desired situation [4.5].
4.3.3 Local Density Approximations (LDA)
Local-density approximations (LDA) are a class of approximations to the
exchange-correlation (XC) energy functional in DFT that depend solely upon the value
of the electronic density at each point in space (and not, for example, derivatives of the
density or the Kohn-Sham orbital [4.7]). Many approaches can yield local
approximations to the XC energy. Overwhelming, however, successful local
approximations are those that have been derived from the homogeneous electron gas
(HEG) model. In this regard, LDA is generally synonymous with functional based on
95
the HEG approximation, which then applied to realistic systems (molecules and solids).
In general, for a spin-unpolarized system, a local-density approximation for the
exchange-correlation energy is written as
Exc[ρ] = ∫ρ(r)εxc(ρ(r)) dr (4.1)
where ρ is the electronic density. εxc is the exchange-correlation energy per electron in a
uniform gas of density ρ. The uniform electron gas remains the only system for which
Exc can be calculated, and hence from which εxc[ρ] can be constructed [4.8].
Local-density approximations are important in the construction of more
sophisticated approximations to the exchange-correlation energy, such as generalized
gradient approximations or hybrid functionals, as a desirable property of any
approximate exchange-correlation functional is that it reproduces the exact results of the
HEG for non-varying densities. As such, LDA's are often an explicit component of such
functional [4.5].
4.3.4 Calculation of Charge Defects
The ease of formed defects in La2O3 was estimated by first-principle calculation.
A La2O3 hexagonal crystal with 50 atoms was used for calculation. Two intrinsic
defects with charge of +2 (++) or -2 (--) were considered; a single oxygen vacancy at
4-fold oxygen site (VO++) and an interstitial oxygen (IO
--) in the crystal. The crystal
structures are shown in Fig.4.3
96
Figure 4.3 La2O3 crystal structures (a) is perfect crystal, (b) is included an interstitial oxygen (IO--) in
crystal, (c) is formed oxygen vacancy (VO++) in crystal
The valence configurations of the pseudopotentials are 5s25p65d16s2 for La and
2s22p4 for O. We used a cutoff energy of 500 eV in the plane-wave basis set expansion.
A Monkhorst-Pack k-point sets of 6×6×6 and 2×2×2 were used for a 5-atom unit
cell and a 50-atom supercell of hexagonal La2O3 (space group P–3m1), respectively.
The 5-atom cell was used for the optimization of the cell parameters, which were
determined as a = 3.88 Å, c = 5.96 Å in good agreement with the experimental values
(aexpt. = 3.9373 Å, cexpt. = 6.1299 Å [4.9]). The unit cell was extended to the 50-atom
supercell to construct models for defects in La2O3.
4.3.4.1 Formation Energy
First, the formation energies of charge defects with charge, VO, VO+, and VO
++ (or IO,
IO-, and IO
--), were estimated by using the total energy values. The stability of these
defects was compared in terms of the formation energy defined by
++OV
−−OI
La
O
(a) (b) (c)
97
Ef(XQ) = Etot(XQ) - Etot(bulk) - noµO + Q(εF+ εv+ ∆V +Ecorr), (4.2)
where Etot(XQ) and Etot(bulk) are the total energy of a defect X (Vo or Io) with charge Q
and the bulk La2O3, which were given by our DFT calculations. Compensating
background charge was introduced for the charged defects to avoid divergence of the
total energy without any corrections afterward. The atomic positions were relaxed until
the total energy difference was converged within 0.001 eV, which results in having the
residual forces below 0.035 eV/Å. µO is the oxygen chemical potential, and no is the
number of oxygen atoms deviating from the perfect crystal; i.e., no =1 for Vo and no = 1
for Io. εF is the Fermi energy referenced with the valence band maximum εv of the bulk
La2O3. ∆V is the correction to εv for the shift in the electro static potential due to the
introduction of the charged defects into the supercell with respect to that in the bulk
La2O3, which we found is 0.1 eV at a maximum. Ecorr is a correction to εv originating
from the special k-point sampling for the shallow acceptor (IO in our case): the energy
difference between the top of the valence band at Γ and the other k-points sampled in
our calculations, which are about -0.02 eV for IO. In Eq. (4.2) εF and µO are the variable.
The µO value changes depending on atmosphere. Here, this value was determined
by a half of the total energy of an oxygen molecule: µO
max = µO
O2 = E tot (O2 ) / 2. The
formation energies of each defect were estimated as changing εF form valence band
maximum to conduction band minimum. Those results are shown in Fig.4.4
98
Figure 4.4 Formation energy of each defects with charge (VO, VO+, VO
++ and IO, IO-, IO
--) as a function of
Fermi level
It is easy for charge defects to be formed by formation energy small. Hence, as
shown in Fig. 4.4, diatomic charge (VO++, IO
--) is the stable-condition at band gap in both
charge defects. Therefore, only diatomic charge as the valence state was thought.
On the other hand, to investigate the charge defects changing referenced with µO,
εF value is set to the valence band offset of La2O3 with respect to Si (2.6 eV) [4.10].
Thus, only µO is the variable in Eq. (4.2).
The maximum value of µO is given by a half of the total energy of an oxygen
molecule: µO
max = µO
O2 = E tot (O2 ) / 2. Whereas, the minimum value of µO is determined by
the condition that a metal lanthanum precipitate in La2O3 µO
min = (µLa2O3− 2µLa
bulk ) / 3 where
µLa2O3 and µLa
bulk are the chemical potentials of a bulk La2O3 and La per unit which were
calculated from the total energies of a 5-atom cell of hexagonal La2O3 and a 4-atom cell
of α-La, respectively. To validate our computational results, we have estimated an
enthalpy of formation of La2O3 from the formula: ∆H(La 2O3 ) = µLa2O3− 2µLa
bulk − 3µO
O2 which
10 2 3 4
4
2
0
-2
-4
Fermi level [eV] Fo
rmat
ion
ener
gy [e
V]
-6
Io
Io-2
Io-1
Io0IO
IO+
IO++
10 2 3 4
10
8
6
4
2
Fermi level [eV]
Form
atio
n en
ergy
[eV]
Vo
Vo-2
Vo-1
Vo0VO
VO++
VO+
99
gives 9.5 eV per La, in good agreement with an experimental value (9.301 eV) [4.9].
In Fig. 4.5 the formation energy of each defect is shown as a function of µO. Here,
µO is referenced with µO
O2 . Only the stable charged states are depicted in Fig. 4.5. It is
understood that VO++ predominates in a low µO, while IO
-- preferably forms in a high µO.
Figure 4.5 Formation energy of each defect as a function of µO in La2O3.
4.3.4.2 Concentration of Charge Defects in La2O3
The concentration of defect was estimated by
)][
exp(][TkXE
NXnB
Qf
siteQ −= (4.3)
where Nsite is the number of defect sites available in a unit volume(Nsite (VO++)=20,
Nsite (IO--)=10). kB is Boltzmann’s constant and T is the thermodynamic temperature at
the equilibrium. Here, this equation is a function of oxygen chemical potential. Change
of the concentration value due to changing this potential value was investigated. Figure
-4
0
2
4
6
-2
Form
atio
n en
ergy
[eV]
-7 -6 -5 -4 -3 -2 -1 0Oxygen chemical potential [eV]
Vo+2
IO-2
La2O3
La2O3
Excess oxygen interstitial
Excess oxygen vacancy
100
4.6 shows that the variable area of oxygen chemical potential in La2O3 and the addition
of the two densities of VO++ (nVO) and IO
-- (nIO). As shown in this Fig. 4.6, in La2O3
single layer, the defect concentration is varied under changing µO value, which means
that the concentration of defects depend on oxygen ambient.
Figure 4.6 Total of charged defects of La material depend on oxygen partial pressure. The region of
oxygen chemical potential in La2O3 was varied in a wide range.
At high µO region, the density of interstitial oxygen is high. Decrease in oxygen
chemical potential causes the density of interstitial oxygen to decrease but the density of
oxygen vacancies to increase. At a certain value of oxygen chemical potential, the
number of oxygen vacancies exceeds to that of interstitials, and finally, oxygen
vacancies become dominant. Therefore, the density of the total charged defects show a
minimum point. The defect density has a minimum at the -4.2 eV. For the reduction of
charge defect, it’s preferable that µO is fixed at or near this value. Fixed µO means that
Den
sity
of c
harg
ed d
efec
t [cm
-3]
-7 -6 -5 -4 -3 -2 -1 0Oxygen chemical potential [eV]
1023
1020
1017
1014
1011
108
105
Total of charged defect
minimum point
O2 moleculemetal
VO2+ rich IO2- rich
La2O3 monolayer
La2O3
La2O3 monolayer
101
µO is independent of the process conditions. Therefore, the concentration of IO-- and
VO++ are constant at the oxidation and reduction ambient, respectively. In addition,
quantity of charge defects can be decreased by nearing the minimum point.
Figure 4.7 shows the mechanism of fixed chemical potential in La2O3 by CeOX
capped on La2O3 case. At reduction ambient, if only high-k film, many oxygen
vacancies are generated. However, when CeOX is capped on high-k, CeOX released
oxygen atoms to compensate the oxygen vacancies in the high-k by increasing the ratio
of Ce2O3. On the other hand, at oxidizing process, if only high-k film, interstitial
oxygen atoms are generated. But the case of CeOX is capped, oxygen atom are absorbed
into CeOX to suppress the interstitial oxygen atoms by increasing the ratio of CeO2. For
both conditions, the chemical potential of CeOX and the high-k is kept constant.
Figure 4.7 Mechanism of fixed oxygen chemical potential in host high-k.
reducing process oxidizing process
Oxygen chemical potential
µO is kept constantwith Ce-oxide capping
stable flatand voltage
CeO2→ Ce2O3 + O
VO2- + O
Ce2O3 + O→ CeO2IO2--2e-→ O
Ce2O3CeO2
Ce2O3CeO2
Vo2+Vo2+
Io2-Io2-OOrelease
La2O3
Ce2O3CeO2
Ce2O3CeO2
Vo2+Vo2+
Io2-Io2-OOabsorb
La2O3
102
By using multivalent materials, such as CeOX, EuOX and POX, this may be
attainable. For example in CeOX case, if the oxide has two phases associated with
different valences, the value of µO can be uniquely determined.
Figure 4.8 Oxygen chamical potential diagram of multivalent materials (Ce, Eu,Pr oxide) and La2O3
In this study, three multivalent materials (Ce, Eu, Pr oxide) were investigated. For
example, the µO value was estimated in CeOX. The fixed chemical potential value was
calculated as follow. If CeOX has two phases of Ce2O3 and CeO2, µO is determined by
the thermal equilibrium condition,
2322 CeOOOCe µµµ =+ (4.4)
2322 )()(2 322/ O
OOCeCeO
O OCeHCeOH µµ +∆−∆= (4.5)
Here, 2
323232
OOCeOCe )OCe(H µµµ ++∆= and 2
222
OOCeCeO )CeO(H µµµ ++∆= were used in
the derivation of Eq. (4.5). The absolute values of the measured enthalpy of formation
for Ce2O3 and CeO2 per Ce are ∆H(Ce2O3)= 9.326 eV and ∆H(CeO2)=11.301 eV,
-7-6-5-4-3-2-10
-10-9-8
Oxy
gen
Che
mic
al P
oten
tial [
eV]
La2O
3
Ce 2
O3
CeO
2
Eu2O
3
Pr2O
3Pr
O2
EuO
La Ce
Eu Pr
103
respectively [4.10]. The oxygen chemical potential is, therefore determined by
2∆H(CeO2)-∆H(Ce2O3) = -3.9 eV referenced with µOO2 . Hence, chemical potential is
fixed. Similarly other multivalent oxides can be fixed the µO value in La2O3, however,
fixed points are different depending on multivalent materials. These points are shown in
Fig. 4.9.
Figure 4.9 The oxygen chemical potential diagram of CeOX, EuOX and PrOX. Concentration of charged
defect in La2O3, by capping multivalent materials on La2O3. In this case, the density of charged defect
value in La2O3 film is fixed at red points.
Den
sity
of c
harg
ed d
efec
t [cm
-3]
-7 -6 -5 -4 -3 -2 -1 0Oxygen chemical potential [eV]
1023
1020
1017
1014
1011
108
105
Total of charged defect
minimum point
IO2- richnear minimum point with Ce-oxide capping
µο(Eu) µο(Ce)
µο(Pr)
Ce CeO2
Eu EuO Eu2O3
Pr Pr2O3 PrO2
Ce2O3
104
The result of comparison with three oxides, CeOX is nearest chemical potential to
the minimum point of the concentration of the total number of charged defects in La2O3.
Therefore, it is expected that fixed charges in La2O3 are greatly reduced by the
deposition of CeOX on La2O3.
4.4 Experimental Results
Therefore, it is expected that the combination of La2O3 and Ce-oxide has an effect
on reducing the fixed charge in La2O3. Here, it must be confirmed that different valence
states exist under an oxidation and reduction ambient.
XPS analysis shows that two phases associated with different valences of Ce (Ce3+
and Ce4+) exist in CeOX film [4.11], as shown in Fig. 4.10. The intensity ratio of the
XPS spectrum of these two phases was dependent to the annealing temperatures as well
as its ambient. However, both phases always exist [4.12].
Figure 4.10 XPS spectra ariying from CeOX layre in CeOX/La2O3 stacked capacitor [4.12].
Binding Energy [eV]
Inte
nsity
[arb
. uni
ts]
PDA
at 600°C in N2at 500°C in N2at 400°C in N2at 300°C in N2
TOA = 52° Ce 3d5/2
874878882886890894 526530534
O 1sCe3+
Ce4+
Ce3+
Ce4+
105
Additionally, Table 4.1 shows the difference between binding energy of Ce 3d5/2
and Si 2s. As this Table, those values are almost the same. Therefore, Fermi level in
both layer are always equal and the oxygen concentration is a constant.
Table 4.1 Difference between binding energy of Ce 3d 5/2 and Si 2s
It is clear that CeOX cap is useful as capping on La2O3 from theoritical calculation.
In this section, we validiate the previous first-principle calculations and CeOX capping
effect by experimental results. Figure 4.11 shows EOT-Vfb data (plots) and fitting curve
(solid line) of EuOX/La2O3, CeOX/La2O3, and PrOX/La2O3. The charged defects density
in films (Q1) was estimated using charged defect model. This model was shown in
chapter 3.
731.0O2 300
731.2N2 600
730.9N2 500
731.2N2 400
731.0N2 300
E(Ce3+)-E(Si2s)PDA
731.0O2 300
731.2N2 600
730.9N2 500
731.2N2 400
731.0N2 300
E(Ce3+)-E(Si2s)PDA
106
Figure 4.11 (a) and (b) are EOT-Vfb characteristics and estimation of fixed charged density (Q1) in
EuOX/ La2O3 and CeOX/ La2O3 layered MOS capacitors, respectively.
0
-0.5
-1.0
-1.5
-2.50.5 1.0 1.5 2.0 2.5 3.0
EOT (nm)
V fb
(V)
-2.0
Q1= -1.0×1013 /cm2
(a) W (50 nm) / EuOX (1 nm) / La2O3 (1~10 nm) / Si
2 ~ 11nm
SiLa2O3
La2O3
La2O3
La2O3Eu-oxide
Eu-oxide
Eu-oxide
Eu-oxide
WW
WW
fitting
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.80.5 1.0 1.5 2.0 2.5 3.0
EOT (nm)
Q1= 9.0×1011 /cm2
(b) W (50 nm) / CeOX (1 nm) / La2O3 (1~10 nm) / Si
2 ~ 11nm
SiLa2O3
La2O3
La2O3
La2O3
Ce-oxide
Ce-oxide
Ce-oxide
Ce-oxide
WW
WW
fitting
107
Figure 4.11 (c) is EOT-Vfb characteristics and estimation of fixed charged density (Q1) in PrOX/ La2O3
layered MOS capacitors. (d) is estimated of fixed charged density in each films.
EuOx/La2O3
CeOx/La2O3
PrOx/La2O3
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5Fixe
d ch
arge
den
sity
(×
1013
C/c
m2 )
La2O3
(d)
0.4
0.3
0
-0.1
-0.20.5 1.0 1.5 2.0 2.5 3.0
EOT (nm)
0.2
0.1
Q1= 2.3×1013 /cm2
(c) W (50 nm) / PrOX (1 nm) / La2O3 (1~10 nm) / Si
2 ~ 11nmfitting
SiLa2O3
La2O3
La2O3
La2O3
Pr-oxide
Pr-oxide
Pr-oxide
Pr-oxide
WW
WW
108
In the charged sign, only EuOX capping sample is opposite. Comparision of three
capping material, the trend of experimental result and calculation result is almost the
same. Therefore, the capping method for charged defects reduction is very useful
thehnique.
The influences of CeOX capping on electrical properties of MOSFET were
investigated. Figure 4.12 shows the electrical properties of CeOX/ La2O3 layered
MOSFET. The characteristics of La2O3 single layered sample is also shown as reference.
Figure 4.12 Electrical properties of W/CeOX/La2O3 and W/La2O3 MOSFET. (a) Cgc curves,(b) Id-Vg and
(c) calculated effective mobility.
2.0
1.5
2.5
1.0
0.5
0-1.0 -0.5 0 0.5 1.0
Gate voltage (V)
Cap
acita
nce
(µF/
cm2 )
Cgc
Ce-oxide/La2O3(EOT= 1.14nm)
La2O3(EOT= 1.27nm)
10-3
-0.5 0 0.5 1.0Gate voltage (V)
Dra
in c
urre
nt (
A)
10-4
10-5
10-6
10-7
10-8
10-9
10-10
1.5
Vd =0.05V
300
0.2 0.4 1.0Eeff (MV/cm)
250
200
150
100
50
0 1.40.6 0.8 1.2
µ eff
(cm
2 /Vs)
W/L = 50/2.5 µm
Si
La2O3
Ce-oxideW
(a)
(b) (c)
109
Although EOT value in CeOX capping sample is smaller than the other device, the
mobility was improved by capping CeOX. Especially, mobility was improved in low Eeff
region. This is due to charged defects reduction. Therefore, CeOX capping is very useful
as combination material with La2O3.
4.5 Consideration of Defect-Reduction for Other Material
Figure 4.13 shows the calculation results in HfO2 case. This high-k oxide also has
minimum point in defect density. Again, the oxygen chemical potential fixed by CeOX
was the nearest to the minimum value among three multivalent oxides. Therefore, CeOX
capping on HfO2 can be also considered as effective in charged defects reduction.
Figure 4.13 Concentration of charged defect in HfO2 by capping multivalent materials on HfO2. In this
case, the density of charged defect value in HfO2 film is fixed at blue points.
-6 -5 -4 -3 -2 -1 0Oxygen chemical potential [eV]
1
1010
1020
1025
Den
sity
of c
harg
e de
fect
[cm
-3]
minimum point
1015
105
10-5
EuEuO Eu2O3
Pr Pr2O3 PrO2
Ce Ce2O3 CeO2
110
4.6 Summary and Conclusion
In this chapter, a method for charged defects reduction in La2O3 film has been
proposed by using CeOX material. The effect of this method was investigated by
theoretical calculation. It is verified that the combination of La2O3 and CeOX has a
reducing effect on the fixed charges amount in La2O3. The same effects were also
confirmed from experimental results. Due to charged defects reduction, electriacal
properties were improved by using CeOX capping over La2O3.
Additionally, as an example of non- La2O3 high-k material, the same analysis has
been performed on HfO2. It can be concluded CeOX is the best material among
RE-oxide to reduce the charged defects in HfO2 as well. Thus, This is a useful method
for the improvement of film properties and can be applied to other materials as well.
111
Reference
[4.1] G. D Wilk, R. M. Wallace, J. M. Anthony, J. Appl. Phys. 89 5243. (2001)
[4.2] M. Copel, E. Cartier, F. M. Ross, Appl. Phys. Lett. 78 1607 (2001)
[4.3] G. Kresse and J. Hafner, Phys. Rev. B 47, RC558 (1993).
[4.4] G. Kresse and J. Furthmüller, Phys. Rev. B 54, 11169 (1996).
[4.5] M. D. Segall, P. J. D. Lindan, M. J. Probert, C. J. Pickard, P. J. Hasnip, S. J. Clark,
and M. C. Payne, J. Phys. 14 (2002) 2717.
[4.6] R. Armiento and A. E. Mattsson, Phys. Rev. B, 72 (2005) 085108.
[4.7] W. Kohn and L. J. Sham, Phys. Rev. 140, A1133 - A1138 (1965)
[4.8] Ceperley D M and Alder B J, Phys. Rev. Lett. 45 (1980) 566.
[4.9] O. Kubaschewski, C. B. Alcock, and P. J. Spencer, in Materials Thermochemistry
6th edition (Pergamon Press, April 1993)
[4.10] J. Robertson, Rep. Prog, Phys. Vol. 69, 327 (2006).
[4.11] H. Nohira et al., J.S.A.P. 69th Autumn Meeting 2008, 3a-CB-7
[4.12] H. Nohira, Y. Kon, K. Kitamura, M. Kouda, K. Kakushima, and H. Iwai, ECS Trans., 25 (6) 321-326 (2009).
112
Chapter 5 Suppression of Interfacial Reaction for EOT Scaling
5.1 Introduction 5.2 Suppression of Silicate Formation by Using Capping 5.3 High-Temperature Annealing and Spike Annealing 5.4 Effect of Thin Metal Thickness 5.5 Confirmation of Effects of PMA and Thin Metal on Device Performance 5.6 Summary and Conclusions
113
5.1 Introduction
In Chapter 3, La2O3 was selected as the base gate insulator in our device structures.
This material could achieve EOT-less-than-1 nm with fairly good electrical properties
because of its ability to form La-silicate at the La2O3/Si interface. The structure of this
silicate layer could be either Si- or La-rich (Fig. 5.1) which depends on the processing
conditions, such as annealing temperature, gate metal material and thickness [5.1]. The
dielectric constant of Si-rich silicate is lower than La-rich silicate. Therefore, formation
of Si-rich silicate should be avoided for EOT scaling purposes. The amount of radical
oxygen present within the gate stack is a key influencing factor in La-silicate layer
structure.
Figure 5.1 Reaction at La2O3/Si interface [5.1].
In this chapter, we propose capping La2O3 layer with TmOx or NdOx films. The
generation of radical oxygen atoms in both of these oxides as capping materials is small
La2O3+Si+nO2→ La2SiO5, La10(SiO4)6O3, La9.33Si6O26, La2Si2O7
114
which can suppress the formation of Si-rich phase in the La-silicate layer. Experimental
data confirmed that Si-rich La-silicate phase can be reduced by using this capping
method.
Furthermore, as alternative EOT scaling methods,
‘high-temperature-spike-annealing’ and ‘thin-metal-thickness’ are described in this
chapter.
5.2 Suppression of Silicate Formation by Using Capping
Figure 5.2 shows Si 1s photoelectron spectra for W/La2O3/Si MOS capacitors with
NdOx or TmOx capping. The photoelectrons arising from Si 1s core levels having
binding energy around 1842 to 1843 eV indicate the formation of La-rich silicates at the
interface, whereas those around 1844 eV indicate the formation of Si-rich silicates
[5.2-5.4]. It can be confirmed that formation of Si-rich phase which is observed in the
reference sample can be effectively suppressed by capping the La2O3 layer with NdOX
or TmOX. Therefore, the average dielectric constant of the overall gate oxide is
increased by this capping method.
115
Figure 5.2 Si 1s photoelectron spectra measured for the device with and without TmOx- and
NdOx-capping. By capping La2O3 with these oxides, the formation of Si-rich silicate with a low
dielectric constant were suppressed.
Figure 5.3 shows the C-V characteristics of 3-nm-thick La2O3 capacitors with
1-nm-thick NdOX, and TmOX capping. A 4-nm-thick La2O3 capacitors is shown as the
reference. Although the thicknesses of the oxides were almost the same, a much smaller
EOT of 0.86 and 0.89 nm were obtained for NdOX and TmOX capped capacitors
compared to the reference sample with 4-nm-thick La2O3 as the gate oxide. This
reduction in EOT value can be explained by the suppression of Si-rich phase formation
within the gate stack.
1846 1845 1844 1843 1842 1841 1840Binding energy (eV)
Silicate(La rich)
Silicate(Si rich)
Si1s
W/TmOX(1nm)/La2O3(3nm)/SiW/NdOX (1nm)/La2O3(4nm)/Si
W/La2O3(4nm)/Si
Si sub.
Inte
nsity
(a.u
.)
116
Figure 5.3 C–V characteristics for these kinds of MOS capacitors with physical thickness around 4 nm
(thickness of capping layers was 1 nm).
Figure 5.4 shows the leakage current density (Jg) measurement at Vg -Vfb = 1V for
capacitors with NdOX and TmOX capping on La2O3 with various thicknesses. The
capping effect on Jg reduction is clearly observed, especially Jg less than 102 A/cm2 was
achieved at EOT of 0.5 nm.
2.5
2.0
1.5
1.0
0.5
0-1.0 -0.5 0 0.5 1.0
Gate voltage (V)
Cap
acita
nce
(µF/
cm2 )
100 kHz
-1.5
3.5
3.0TmOX-cap (EOT=0.89 nm)
La2O3 (EOT=1.32 nm)
NdOX / La2O3 (EOT=0.86 nm)
117
Figure 5.4 Leakage current density-EOT characteristics. By capped La2O3 with various oxides, leakage
current was suppressed.
The influence of rare earth oxide capped over La2O3 on FET characteristics are
investigated. Owing to the reduced Jg by capping with NdOX and TmOX, satisfactory
FET operation was observed with small EOT down to 0.6 nm. Figure 5.5 shows the
electrical characteristics of FET with NdOX and TmOX capping.
0.5 0.7 0.9 1.1 1.3 1.5
102
EOT [nm]
Leak
age
curr
ent
[A/c
m2 ] 101
1
10-1
10-2
10-3
10-4
10-5
10-6
103
Vg – Vfb = 1 VITRS
La2O3
Tm-oxidecapNd-oxide
cap
118
Figure 5.5 Electrical characteristics of MOSFETs with TmOX and NdOX capped on La2O3 gate insulator.
The EOT values of both samples are around 0.6 nm. (a) Ig‒Vg, (b) effective mobility.
0 0.2 0.4 0.6 0.8 1.0
6.0
4.0
2.0
Vg = 0.6V
0.2V
0V
-0.2V
Drain voltage (V)
Dra
in c
urre
nt (m
A)
0.4V
0 0.2 0.4 0.6 0.8 1.0
6.0
4.0
2.0
Vg = 0.8V
0.4V
0.2V
0V
-0.2V
Drain voltage (V)
Dra
in c
urre
nt (m
A)
0.6V
10-4
10-3
10-2
Gat
e cu
rren
t (A
) Vd = 1.0V
0.05V
10-5
10-6
10-7-0.8 -0.4 0 0.4 0.8
Gate voltage (V)
L/W = 2.5/50 µm
-1.0 -0.5 0 0.5 1.0
10-4
10-3
10-2
Gate voltage (V)
Gat
e cu
rren
t (A
) Vd = 1.0V
0.05V
10-5
10-6
10-7
L/W = 2.5/50 µm
0.4
30
0.8 1.60
60
90
150
180
Mob
ility
(cm
2 /Vs)
Effective electrical field (MV/cm)
120
1.20.4
30
0.8 1.60
60
90
150
180
Mob
ility
(cm
2 /Vs)
Effective electrical field (MV/cm)
120
1.2
Tm-oxide
La2O3
Si
WEOT = 0.66 nm
Nd-oxide
La2O3
Si
WEOT = 0.62 nm
(a) (b)
Dra
in c
urre
nt (A
)
Dra
in c
urre
nt (A
)
119
Normal operation of MOSFET with smallest EOT of 0.45nm was achieved with NdOx
capped sample. Figure 5.6 shows the electrical characteristics of this MOSFET. In this
MOSFET, gate length (L) and width (W) are 2.5 and 50 µm, respectively. The thickness
of the W gate film was 50nm and the annealing condition of the sample was at 500 oC
for 30min (F.G ambient). Figure 5.6 (a), (b) and (c) are Id-Vd, Ig-Vg, and effective
mobility characteristics, respectively. High subthreshold slope (S.S) of about 127
mV/dec. might be caused by high interfacial state density. The effective mobility was as
low as 90 cm2/Vs.
Figure 5.6 Electrical characteristics of MOSFETs with NdOX capped on La2O3 gate insulator. The EOT
value is 0.45 nm. (a) Id-Vd, (b) Ig‒Vg, (c) effective mobility.
10-5-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6
10-4
10-3
10-2
Gate voltage (V)
Gat
e cu
rren
t (A
)
Vd = 1.0V
0.05V
0 0.2 0.4 0.6 0.8 1.0
1.8
1.5
1.2
0.9
0.6
0.3
Vg = 0.6V
0.4V
0.2V
0V
-0.2V-0.4V
Drain voltage (V)
Dra
in c
urre
nt (m
A)
0.5
20
1.0 1.50
40
60
80
100
Mob
ility
(cm
2 /Vs)
Effective electrical field (MV/cm)
Nd-oxideLa2O3
Si
W
EOT= 0.45 nmVth = -0.39 V (Vd=0.05 V)S.S = 127 mV/dec
L/W=2.5/50
(a)
(b) (c)
Dra
in c
urre
nt (A
)
120
Figure 5.7 shows the Si 1s photoelectron spectra for NdOX capped on La2O3
devices where La2O3 thickness is either 1 or 4 nm. Si-rich silicate formation was
suppressed and the thickness of silicate was constant even at different La2O3
thicknesses. Therefore, it can be concluded that interface reaction is identical for NdOx
capped devices regardless of the initial La2O3 thickness.
Figure 5.7 Si 1s photoelectron spectra measured for the device with NdOx-capping on La2O3. Identical
interface reaction with changing La2O3 thickness was achieved by NdOX capping.
Figure 5.8 shows the charged defects densities in W/La2O3/Si MOS capacitors
with NdOx or TmOx capping. The capping material does not result in any significant
effect on charged defects reduction.
1846 1845 1844 1843 1842 1841 1840Binding energy (eV)
Silicate(La rich)
Silicate(Si rich)
Si1s Nd-oxide
La2O3
Si
W1nm4nm
Nd-oxideLa2O3
Si
W 1nm1nmIn
tens
ity (a
.u.)
121
Figure 5.8 EOT–Vfb plot for (a) TmOX or （b）NdOX capping MOS capacitors. The charged defect density
which was estimated form Eq. (3.3) of fitted EOT–Vfb characteristics.
0
V fb
(V)
0.2
0.4
-0.2
-0.4
-0.6
-0.80 0.5 1.0 1.5 2.0 2.5 3.0
EOT (nm)
fitting
Tm-oxide/La2O3
Q1= 2.2×1013 /cm2
(a) W(50nm)/ TmOX (1nm)/ La2O3 (1~10 nm)/ Si
2 ~ 11 nm
Si
La2O3La2O3
La2O3La2O3
WW
WW
Tm-oxideTm-oxide
Tm-oxideTm-oxide
0
V fb
(V)
-0.4
-0.5
-0.6
-0.70 0.5 1.0 1.5 2.0 2.5 3.0
EOT (nm)
fitting
Nd-oxide/La2O3
-0.3
-0.2
-0.1
Q1= 2.4×1013 /cm2
(b) W(50nm)/ NdOX (1nm)/ La2O3 (1~10 nm)/ Si
2 ~ 11 nm
Si
La2O3La2O3
La2O3La2O3
WW
WW
Nd-oxideNd-oxide
Nd-oxideNd-oxide
122
Figure 5.9 shows C-V characteristics of CeOX, PrOX, NdOX, GdOX, EuOX, TmOX
capped on La2O3 MOS capacitors. A 4-nm-thick La2O3 capacitors is also shown as
reference. EOT scaling was not achieved except for NdOX and TmOX capping (Table
5.1).
Figure 5.9 C–V characteristics for all kind of MOS capacitors with physical thickness around 4 nm
(thickness of capping layers was 1 nm).
High generation of radical oxygen atoms in the capping material results in larger
EOT of stacked layered structure. Therefore, using materials with low radical oxygen
generation rate as a gate oxide insulator capping film is a useful technique for EOT
scaling.
1.63GdOX/ La2O3
0.89TmOX/ La2O3
1.78EuOX/ La2O3
0.86NdOX/ La2O3
1.25PrOX/ La2O3
1.30CeOX/ La2O3
1.32La2O3
EOT (nm)insulator
1.63GdOX/ La2O3
0.89TmOX/ La2O3
1.78EuOX/ La2O3
0.86NdOX/ La2O3
1.25PrOX/ La2O3
1.30CeOX/ La2O3
1.32La2O3
EOT (nm)insulator
3.0
2.5
2.0
1.5
1.0
0.5
3.5
0-1.5 -1.0 -0.5 0 0.5 1.0
Gate voltage (V)
Cap
acita
nce
(µF/
cm2 )
La2O3
TmOX/La2O3
PrOX/La2O3
CeOX/La2O3
NdOX/La2O3
GdOX/La2O3
EuOX/La2O3
Table 5.1 EOT values of all kind of MOS capacitors
123
5.3 High-Temperature Annealing and Spike Annealing
High-temperature and spike annealing treatment is reported to be an effective EOT
scaling method [5.5]. In our laboratory, the effects of this method were investigated.
Figure 5.10 shows the EOT dependence on annealing temperature. The increase in EOT
value at higher annealing temperature is caused by formation of thicker silicate layer.
Figure 5.10 EOT values dependence on annealing temperature [5.5]
Figure 5.11 shows the annealing temperature dependence on W(60nm)/ La2O3
(3nm)/n-Si capacitors EOT with annealing duration of 30min or 2s. Reducing the
annealing time can suppress EOT increase at higher annealing temperatures.
EOT(
nm)
Annealing temperature(oC)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0 100 200 300 400 500 600 700 800 900 1000
W/La2O3(3 nm)/n-SiPMA 30 min
124
Figure 5.11 Annealing temperature dependence of EOT with different annealing time. [5.5]
In this chapter, the annealing condition is 500 oC at 30min for all samples. Thus,
more EOT scaling may be achieved by using high-temperature and spike annealing.
5.4 Effect of Thin Metal Thickness
Metal thickness effect on EOT is also investigated in our laboratory [5.6, 5.7].
Figure 5.12 shows EOT dependence on annealing temperature for samples with
different W thickness.
125
Figure 5.12 EOT dependence on annealing temperature for TiN (40 nm)/ W (6 or 12 nm)/ La2O3 (3.5
nm)/n-Si and W (60 nm)/La2O3 (3.5 nm)/ n-Si capacitors annealed for 2 s. [5.6]
The increase in EOT after annealing is suppressed as the W layer becomes thinner.
The dependence of La-silicate layer formation on W film thickness is measured by hard
XPS for TiN (10 nm)/W (0–10 nm)/La2O3 (3 nm)/n-Si structures. Figure 5.13 shows the
Si 1s spectra of the samples with and without post metallization annealing at 800oC for
2 s measured at a photoelectron take-off angle of 80o. The increase in the number of
La–O–Si bonds with the thickness of the W film indicates that silicate reaction could be
controlled by changing the thickness of the W film [5.8, 5.9].
126
Figure 5.13 Si 1s photoelectron spectra arising from changing W thickness samples. [5.6]
5.5 Confirming PMA and Thin Metal effect on Device Performance
We examined the influence of the high-temperature spike annealing and thin metal
thickness techniques on the charged defect density in film. The charged defect density
was estimated from EOT-Vfb calculation. Fig. 5.14 shows the EOT-Vfb plots of W (50
nm)/RE-oxide/Si (PMA: 800oC, 2 sec), W (8 nm)/RE-oxide/Si (PMA: 500 oC, 30 min)
and W (50 nm)/RE-oxide/Si (PMA: 500oC, 30 min) structured samples. The Vfb values
of those samples are similar at same EOT values. Hence, high-temperature spike
annealing and thin metal thickness techniques have little influence on charged defects
density in film.
127
Figure 5.14 EOT-Vfb calculations. Square is using high-temperature spike annealing process and triangle
is using thin metal thickness technique.
We investigated whether high-temperature spike annealing and thin metal
thickness, are useful for RE-oxides combination layered devices. Figure 5.15 shows the
La2O3 physical thickness-EOT plot for two PMA condition and metal thickness in
Re-oxide/ La2O3 layered samples. By using thinner W films, EOT was reduced over
1 nm for the same physical thickness of La2O3.
0V f
b(V
)
-0.4
-0.5
-0.6
-0.70 0.5 1.0 1.5 2.0 2.5 3.0
EOT (nm)
-0.3
-0.2
-0.1 W=8 nm, PMA : 500oC, 30min
W=50 nm, PMA : 500oC, 30min
W=50 nm, PMA : 800oC, 2sec
128
Figure 5.15 physical thickness-EOT characteristics.
5.6 Summary and Conclusions
In this chapter, we investigated EOT scaling methods. A silicate phase with low-
dielectric constant can be formed at substrate interface in devices with only La2O3 as
the gate oxide insulator. Thus, La2O3 single layered faces EOT scaling limitation. We
have proposed reducing radical oxygen atoms, which promotes the formation of Si-rich
silicate, by using TmOx or NdOx as capping films over La2O3. Experimental results
show that generation of radical oxygen atoms can be reduced and consequently EOT
can be scaled by using these oxides as capping films. Leakage current was also
suppressed in combination with EOT scaling. Satisfactory FET operation with EOT
down to 0.6 nm was confirmed for TmOx or NdOx capped La2O3 gate oxide based
MOSFETs. MOSFET operation with EOT of 0.45nm was achieved by NdOx-capping
1.0
0.5
4Physical thickness (nm)
EOT
(nm
)
1.5
2.0
2.5
3.0
02 6 8 10
W=8nmPMA : 800oC, 2s
W=50nmPMA : 500oC, 30min
129
method.
High-temperature spike annealing and using thin gate metal are also investigated
as other scaling method options. We confirmed that these techniques have little
influence on the charged defect density in the gate oxide insulator. However, both
techniques are effective for EOT scaling in RE-oxide/La2O3 structured devices.
130
Reference
[5.1] K. Kakushima, T. Koyanagi, K. Tachi, J. Song, P. Ahmet, K. Tsutsui, N. Sugii, T.
Hattori and H. Iwai, Solid State Electron. 54, 720 (2010).
[5.2] T. Hattori, T. Yoshida, T. Shiraishi, K. Takahashi, H. Nohira, S. Joumori, K.
Nakajima, M. Suzuki, K. Kimura, I. Kashiwagi, C. Ohshima, S. Ohmi, and H. Iwai:
Microelectron. Eng. 72 (2004) 283.
[5.3] K. Kakushima, K. Tachi, J. Song, H. Nohira, E. Ikenaga, P. Ahmet, K. Tsutsui, N.
Sugii, T. Hattori, and H. Iwai: J. Appl. Phys. 106 (2009) 124903.
[5.4] K. Kakushima, K. Tachi, M. Adachi, K. Okamoto, S. Sato, J. Song, T. Kawanago,
P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, and H. Iwai: Solid- State Electron. 54 (2010)
715.
[5.5] D. Kitayama, T. Koyanagi, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, and H. Iwai, ECS Trans. 33[3] (2010) 527.
[5.6] D.Kitayama, T. Kubota, T. Koyanagi, K. Kakushima, P. Ahmet, K. Tsutsui, A.
Nishiyama, N. Sugii, K. Natori, T. Hattori, and H. Iwai, Jpn. J. Appl. Phys. 50 (2011)
10PA05.
[5.7] L.Å. Ragnarsson, T. Chiarella, M. Togo, T. Schram, P. Absil, T. Hoffmann,
Microelectronic Engineering 88 (2011) 1317.
[5.8] H. Nohira, T. Matsuda, K. Tachi, Y. Shino, J. Song, Y. Kuroki, J. A. Ng, P. Ahmet, K. Kakushima, K. Tsutsui, E. Ikenaga, K. Kobayashi, H. Iwai, and T. Hattori, ECS Trans. 3 [2] (2006) 169. [5.9] H. Nohira, ECS Trans. 28 [2] (2010) 129.
131
Chapter 6 Charged Defects Reduction
and EOT Scaling Combining Several
RE-oxides 6.1 Introduction 6.2 Charged Defect and EOT Scaling Reduction Techniques 6.3 Proposed Structure for Gate Insulator with RE-oxides 6.4 Combination of Several Processing Conditions 6.5 Summary and Conclusion
132
6.1 Introduction
We have already reported material selection guideline for charged defect reduction
(chapter 3) and EOT scaling (chapter 4) with RE-oxides. In this chapter, we have
investigated the incorporation of two different materials to find out whether both of
these effects can be satisfied.
In this chapter, we selected CeOX-capping method for reduction of charged defects
and TmOX-capping or NdOX-capping for EOT scaling [6.1, 6.2]. Moreover, since it
has been reported that further EOT scaling can be achieved by
high-temperature-spike-annealing and thin metal thickness fabrication processes [6.3,
6.4], we have also investigated the influence of these processes.
6.2 Charged Defect and EOT Scaling Reduction Techniques
Table 6.1 summarizes the gate oxide material, gate metal thickness and annealing
condition effect on EOT and charge defect density of devices. While Tm-oxide capping,
thin metal thickness, and high-temperature spike annealing are effective EOT scaling
methods, charged defects reduction was only achieved by using Ce-oxide capping. In
order to achieve both charged defects reduction and EOT scaling, we investigated
combining capping and process conditions.
133
Table 6.1 Effects of EOT scaling and charged defect reduction on La2O3 based film
6.3 Proposed Structure for Gate Insulator with RE-oxides
In this chapter, we evaluated the combination of three of RE-oxides: La2O3, CeOX,
and NdOX (or TmOX). The preferable deposition order of NdOX or TmOX layer was
also investigated. Figure 6.1 shows the C-V and J-V characteristics of MOS capacitors
with NdOX/ La2O3 and La2O3/ NdOX stacked gate dielectrics. The total deposited
thickness was controlled to be 3 nm. The annealing condition was at 500oC for 30min.
――×××××〇Charge defect
reduction
〇〇〇××〇――EOT scaling
high-temperature spike PMA
Thin Metal thickness
Tm oxide cap
Gdoxidecap
Euoxide cap
Ndoxidecap
Pr oxidecap
Ceoxidecap
――×××××〇Charge defect
reduction
〇〇〇××〇――EOT scaling
high-temperature spike PMA
Thin Metal thickness
Tm oxide cap
Gdoxidecap
Euoxide cap
Ndoxidecap
Pr oxidecap
Ceoxidecap
〇：effective ―：no effect ×：degrade
134
Figure 6.1 (a) C-V characteristics and (b) J-V characteristics of MOS capacitors with NdOX(1 nm)/
La2O3(2 nm) and La2O3(2 nm)/ NdOX(1 nm).
Although both dielectrics have the same initial thickness, extracted EOT values
were different. The reason might be due to the difference in the interfacial reaction with
Si-substrate. For NdOX/ La2O3 stacked device, formation of La-silicate with low
dielectric constant silicate layer (Si-rich phase) was suppressed owing to less generation
of radical oxygen atoms in NdOX layer. On the other hand, at NdOX/ Si interface,
Nd-silicate with the same thickness as with NdOX/ La2O3 case can be thought to be
formed as the amount of radical oxygen atoms should be the same as NdOX/ La2O3 gate
film. Figure 6.2 shows the schematic illustration of each device after annealing. The
dielectric constant of La-silicate might be higher than that of Nd-silicate as the dielectric
constant of La2O3 is higher than that of NdOX [6.4, 6.5]. Therefore it is preferable to use
La-silicate as bottom interface layer. Additionally, leakage current density of NdOX/
3.0
4.0
0Gate voltage (V)
Cap
acita
nce
(µF/
cm2 )
2.0
1.0
0.5 1.0-0.5-1.0-1.5
NdOX(1 nm)/La2O3(2 nm)(EOT=0.64 nm)
La2O3(2 nm)/NdOX(1 nm)(EOT=0.8 nm)
(a)
PMA : 500oC, 30min
103
102
101
100
10-1
10-2
10-3
10-4
10-5
1.0 2.0 3.00Gate voltage (V)
Leak
age
curr
ent d
ensi
ty (A
/cm
2 )
(b) NdOX(1 nm)/La2O3(2 nm)(EOT=0.64 nm)
La2O3(2 nm)/NdOX(1 nm)(EOT=0.8 nm)
135
La2O3 stacked device showed smaller values compared to La2O3/ NdOX stacked devices.
This could be due to difference of band gap among each silicate; La-silicates might have
a larger band gap than Nd-silicates. Therefore, La-silicates as bottom interface layer is
preferable also from the leakage current point of view.
Figure 6.2 Structure of gate insulator with NdOX / La2O3 and La2O3/ NdOX
Similar pattern can be observed with TmOX. Figure 6.3 shows the C-V and J-V
characteristics of MOS devices with TmOX/ La2O3 and La2O3/ TmOX stacked structures.
The total deposited thickness of the film was controlled to be 3 nm. Annealing was
conducted at 500 oC for 30 min.
La2O3
W
SiNdOX
Nd-silicate
La2O3
W
Si
NdOx
La-silicate
Amount of radical oxygen atoms
136
Figure 6.3 (a) C-V characteristics and (b) J-V characteristics of MOS devices with TmOX(1 nm)/ La2O3(2
nm) and La2O3(2 nm)/ TmOX(1 nm) stacked
From the above experiment results, we can conclude that the potion of NdOX and
TmOX should be deposited on top of La2O3 layer.
6.4 Combination of Several Processing Conditions
It was shown that by CeOX capping over La2O3, charged defects can be reduced
and by NdOX capping generation of radical oxygen atoms can be suppressed. By using
the CeOx/ La2O3 /NdOx / La2O3 stacked layer, the charged defects can be reduced and
at the same time the generation of radical oxygen atoms at the interface should be
suppressed, schematically shown Fig.6.4.
3.0
4.0
0Gate voltage (V)
Cap
acita
nce
(µF/
cm2 )
2.0
1.0
0.5 1.0-0.5-1.0-1.5
TmOX(1 nm)/La2O3(2 nm)(EOT=0.77 nm)
La2O3(2 nm)/TmOX(1 nm)(EOT=0.84 nm)
(a)
PMA : 500oC, 30min
103
102
101
100
10-1
10-2
10-3
10-4
10-5
1.0 2.0 3.00Gate voltage (V)
Leak
age
curr
ent d
ensi
ty (A
/cm
2 )10-6
(b) TmOX(1 nm)/La2O3(2 nm)(EOT=0.77 nm)
La2O3(2 nm)/TmOX(1 nm)(EOT=0.84 nm)
137
Figure 6.4 Schematic illustration of reduction in fixed charged defects and suppression of oxygen radicals
Figure 6.5 (a) shows the EOT-Vfb characteristics data and the estimated charged
defects density (Q1) in the film using fixed charges model (in chapter 3). (b) shows Q1
values comparison with La2O3, CeOX/ La2O3, NdOX/ La2O3, and CeOX/ La2O3 /NdOX/
La2O3 layered device
Charged defect
Radical oxygen atomO*
La2O3
W
Si
CeOx
La-silicate
Oxygen absorption
O*
O*O*
O*O*
O*
Oxygen release La2O3
W
Si
NdOx
La-silicate
O*
O*
Generating radical oxygen atom was suppressed
La2O3
W
Si
NdOx
La-silicate
O*
O*
CeOx
138
Figure 6.5 (a) EOT-Vfb characteristics of capacitors. Density of charged defects was estimated from fitting.
(b) Comparison of estimated charged defects density for 4 kind of gate structured capacitors
EuOx/La2O3
2.5
2.0
1.5
1.0
0.5
0CeOx/La2O3
NdOx/La2O3
CeOx/La2O3NdOx/La2O3
Fixe
d ch
arge
den
sity
(×
1013
C/c
m2 ) (b)
0
-0.2
-0.3
-0.50.5 1.0 1.5 2.0
EOT (nm)
V fb
(V)
-0.4
-0.1
fitting
Q1= 5.9×1012 /cm2
(a) W(50 nm)/CeOX(0.5 nm)/La2O3 (0.5~8)/ NdOX (1nm)/ La2O3 / Si
2 ~ 9.5 nm
SiLa2O3 La2O3 La2O3 La2O3
Nd-oxide Nd-oxide Nd-oxide Ndoxide
WW
WW
La2O3
Ce-oxide La2O3
Ce-oxideLa2O3
Ce-oxide
La2O3
Ce-oxide
139
The charged defects were reduced by CeOX capping on La2O3/ NdOX/ La2O3
stacked layer. However, charged defects density is still higher compared to MOS
capacitor with CeOX/ La2O3 layered insulator. Figure 6.6 and Table 6.2 show the C-V
characteristics and estimated EOT value for fabricated MOS capacitors.
Figure 6.6 C-V characteristics with physical thickness of overall dielectrics around 4 nm.
An EOT value of 1.1 nm was obtained for the CeOX/ La2O3/ NdOX/ La2O3 stacked
capacitor, which is smaller than that of CeOX/ La2O3 stacked capacitor with the same
total gate insulator thickness. The reduction in EOT can be explained by considering
that the generation of oxygen radicals is suppressed by using NdOX. However, CeOX/
La2O3/ NdOX/ La2O3 stacked capacitor has a larger EOT than NdOX/ La2O3 stacked
capacitor because oxygen radicals are generated in the CeOX film. For further scaling,
we also employed high-temperature and spike annealing and thin metal thickness
techniques simultaneously. Device fabrication conditions were changed from annealing
1.5
1.0
Cap
acita
nce
(µF/
cm2 )
2.0
2.5
3.0
3.5
0.5
0-1.0 -0.5 0 1.00.5
Gate voltage (V)
La2O3
CeOX/ La2O3
NdOX / La2O3
CeOx/La2O3/NdOx/La2O3
1.10CeOX
/La2O3/NdOX/ La2O3
0.86NdOX/ La2O3
1.30CeOX/ La2O3
1.32La2O3
EOT (nm)insulator
1.10CeOX
/La2O3/NdOX/ La2O3
0.86NdOX/ La2O3
1.30CeOX/ La2O3
1.32La2O3
EOT (nm)insulator
Table 6.2 EOT values
140
at 500oC for 30min and metal thickness 50 nm to new conditions, which were annealing
at 800oC for 2 s annealing and metal thickness 8 nm. Figure 6.7 shows the C-V and
EOT-Vfb characteristics for the new conditions.
Figure 6.7 (a) C-V and (b) Vfb-EOT characteristics in CeOX/ La2O3 /NdOX/ La2O3 layered devices with
different PMA condition and metal thickness
1.5
1.0
Cap
acita
nce
(µF/
cm2 )
2.0
2.5
3.0
3.5
0.5
0-1.0 -0.5 0 1.00.5
Gate voltage (V)
PMA:500oC, 30minMetal thickness:50nm(EOT = 1.1 nm)
PMA:800oC, 2sMetal thickness:8nm(EOT = 0.5 nm)
(a)
0
-0.2
-0.3
-0.50.5 1.0 1.5 2.0
EOT (nm)
V fb
(V)
-0.4
-0.1
0
PMA:500oC, 30minMetal thickness:50nm(Q1= 5.9×1012/cm2)
PMA:800oC, 2sMetal thickness:8nm(Q1= 3.4×1012/cm2)
(b)
141
By using new conditions, high-temperature spike annealing and thin metal
thickness, further EOT scaling was achieved with preserving charged defect reduction
effect. Therefore, the combination of CeOX/ La2O3/ NdOX/ La2O3 stacked layer and
high-temperature spike annealing and thin metal thickness techniques are very useful
for reducing charged defects and EOT scaling.
We also investigated the effect of CeOX/ La2O3/ TmOX/ La2O3 structure with the same
fabrication process as stated above. Figure 6.8 shows the C-V and EOT-Vfb
characteristics of capacitor with CeOX/ La2O3/ TmOX/ La2O3 layered gate oxide
insulator.
1.5
1.0
Cap
acita
nce
(µF/
cm2 )
2.0
2.5
3.0
3.5
0.5
0-1.0 -0.5 0 1.00.5
Gate voltage (V)
PMA:500oC, 30minMetal thickness:50nm(EOT = 1.2 nm)
PMA:800oC, 2sMetal thickness:8nm(EOT = 0.73 nm)
(a)
142
Figure 6.8 (a) C-V and (b) Vfb-EOT characteristics in Ce-oxide/ La2O3 /Tm-oxide/ La2O3 layered devices
with different PMA conditions and metal thickness
EOT and charged defects reduction effect of this structure was almost negligible.
However high-temperature spike annealing and thin metal thickness methods resulted in
smaller EOT without degradation of charged defect density which is similar to the
results of CeOX/ La2O3/ NdOX/ La2O3 stacked layered device.
6.5 Summary and Conclusion
In this chapter, we investigated the gate oxide insulator structure and MOS
capacitor process conditions for reduction of charged defects and EOT scaling. By using
Ce-oxide capping layer over La2O3, which reduces charged defect density, and Nd- or
Tm-oxide capping layer over La2O3, which suppresses the generation of radical oxygen
0.3
0.1
-0.1
-0.30.5 1.0 1.5 3.0
EOT (nm)
V fb
(V)
-0.2
0.2
PMA:500oC, 30minMetal thickness:50nm(Q1= 1.1×1013/cm2)
PMA:800oC, 2sMetal thickness:8nm(Q1= 9.3×1012/cm2)
2.0 2.5
0
(b)
143
atoms, charged defect reduction and EOT scaling could be simultaneously achieved.
Further EOT scaling was achieved by utilizing high-temperature spike annealing and
thin metal thickness method. Ce-oxide/ La2O3/ Nd-oxide/ La2O3 and Ce-oxide/ La2O3
/Tm-oxide/ La2O3 stack layered capacitors were fabricated and compared. Gate stacks
with Nd-oxide were more effective for EOT and charged defect density reduction.
144
Reference
[6.1] M. Kouda, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K.
Natori, T. Hattori, and H. Iwai, Jnp. J. Appl. Phys., 50(10) (2011) 10PA04
[6.2] M. Kouda, N. Umezawa, K. Kakushima, P. Ahmet, K. Shiraishi, C. Toyohiro, K.
Yamada and H. Iwai, VLSI Symp. 2009 , 10B-3, Kyoto June 2009
[6.3] D. Kitayama, T. Koyanagi, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N.
Sugii, K. Natori, T. Hattori, and H. Iwai, ECS Trans. 33[3] (2010) 527.
[6.4] D.Kitayama, T. Kubota, T. Koyanagi, K. Kakushima, P. Ahmet, K. Tsutsui, A.
Nishiyama, N. Sugii, K. Natori, T. Hattori, and H. Iwai, Jpn. J. Appl. Phys. 50 (2011)
10PA05.
[6.4] Kakushima K, Tachi K, Adachi M, Okamoto K, Sato S, Song J, et al. Advantage of
La2O3 gate dielectric over HfO2 for direct contact and mobility improvement. In:
Proceedings of 38th European solid-state device research conference, 2008. p. 126–9.
[6.5] T. M. Pan, J. D. Lee, W. H. Shu, and T. T. Chen, Appl. Phys. Lett. 89, 232908
(2006)
145
Chapter 7
Evaluation of High-k Film Formed by Atomic Layer Deposition and Chemical
Vapor Deposition Processes 7.1 Introduction 7.2 Chemical Vapor Deposition 7.3 Atomic Layer Deposition 7.4 Process Condition and Film Properties
7.4.1 La2O3 Film 7.4.1.1 La(iPrCp)3 7.4.1.2 La(iPrFAMD)3
7.4.2 Ce-oxide Film 7.4.2.1 Ce(Mp)4 7.4.2.2 Ce(EtCp)3 and Ce(iPrCp)3
7.5 Electrical Properties of MOS Devices 7.5.1 La2O3 Film Devices 7.5.2 CeO2 Single Layer 7.5.3 La2O3 and CeO2 Stacked Film
7.6 Summary and Conclusions
146
7.1 Introduction
We previously reported that, among rare-earth oxides, CeO2 forms gate stacks with
a low density of charged defects when combined with other high-k materials such as
La2O3 [7.1-7.3]. So far, CeO2 films for gate dielectric application have been formed
mainly by electron beam (EB) deposition. The effects should be confirmed in other film
formation process for clearing the nature of materials. From the viewpoint of
semiconductor manufacturing, CeO2 and La2O3 formation by chemical vapor
deposition (CVD) and/or atomic layer deposition (ALD) is preferred.
In previously studies, La2O3 film have been widely investigated. Table 7.1 shows
source materials used for ALD or CVD. As for the La2O3 growth, β-diketonate and
silylamide precursors were initially used as the La source [7.4, 7.5]. Recently,
cyclopentadienyls (Cp) and amidinates were often used because of their high vapor
pressures and moderate reactivity. Advantages and disadvantages of Cp and amidinates
are not clear. [7.6-7.11] Therefore we evaluated the process conditions of Cp and
amidinates gas sources and electrical properties of MOS device using those La source
gases.
147
Table 7.1 Source materials are used ALD or CVD [7.4-7.11]
On the other hand, there have been a limited number of CVD/ALD studies about
CeO2 [7.12-7.16]. Especially, there is no report for electrical properties of MOS device.
Therefore, process conditions and gas sources should be investigated.
Here, we report on the preparation of CeO2 and La2O3 films by CVD and ALD
processes and investigate their electrical properties. Through these results, we suggested
that optimum La2O3 films was formed by using La(iPrCp)3 gas source with ALD
process. These films showed good electrical properties that are comparable to EB
evaporated films. Regarding CeO2, film growth was performed by using Ce(Mp)4 gas
source with CVD process, and normal operation of MOSFET and MOS capacitor were
confirmed for the first time. Furthermore, by using CeO2/ La2O3 stacked gate insulator,
EOT scaling was achieved without degradation of mobility, reproducing the previously
amidinate
Relatively new material High vapor pressureModest reactivity with water (H2O)
Strong candidates for ALD-source
Cyclo-pentadienyl
Films contain high Si concentrationk values are rather low silylamide
Too stable O3 is necessary to form oxide. EOT increases due to Si
oxidation
β-diketonate
PropertiesStructural formulaMaterials
amidinate
Relatively new material High vapor pressureModest reactivity with water (H2O)
Strong candidates for ALD-source
Cyclo-pentadienyl
Films contain high Si concentrationk values are rather low silylamide
Too stable O3 is necessary to form oxide. EOT increases due to Si
oxidation
β-diketonate
PropertiesStructural formulaMaterials
148
reported results for EB evaporation.
7.2 Chemical Vapor Deposition
CVD is a chemical process used to produce high-purity, high-performance solid
materials. CVD has become the major method of film deposition in this important
technological field. In fact, it would hardly be an exaggeration to say that computer
chips would not exists in their present form and complexity if CVD were not available
as the method of film deposition
CVD is a method of forming thin film on a substrate by the reaction of vapor phase
chemicals which contain the required constituents. The film is reproducible and
controllable properties including purity, composition, thickness, adhesion,
microstructure, and surface morphology. The reactant gases are activated by various
energy forms such as chemical, thermal, plasma and reacted on and/or above the
temperature-controlled surface to form the thin film. The reactive species, energy, rate
of chemical supply, substrate temperature and substrate itself largely determine the film
properties. Thickness uniformity is critical to maintain the same film and device
characteristics across each substrate wafer. Hetero-junction digital and optical device
applications require that the interface concentration between successive layers of
semiconductors change over a few mono-layer or be graded in a controlled manner. The
need for film with specific electrical, optical, and mechanical properties means that
CVD reactants must be pure, must not produce by-products that become incorporated
into the growing film, and must not interact with gas handing and reactor construction
materials. Furthermore, the CVD reactor has to be designed and operated in such a
manner that the film properties noted above can be accurately controlled. Therefore, it is
149
essential to have a through understanding of the underlying principles of the CVD
method. The basic process steps in CVD are shown schematically in Figure 7.1 and the
process can be generalized as a sequence of steps [7.17].
1) gas phase diffusion from the gas flow
2) gas phase reaction
3) diffusion to the growth surface
4) adsorption
5) surface reaction
6) surface diffusion to growth sites
7) incorporation into the lattice
8) desorption of byproducts
9) gas phase diffusion of byproducts to the bulk gas flow
150
Figure 7.1 Schematic of fundamental transport and reaction processes underlying CVD
Each of those process steps must be understood and controlled so that the process
sequence results in films with the desired materials properties.
In this work, we used hot-wall thermal CVD chamber (Figure 7.2). The source gas
growth experiments were carried out using a hot-wall quartz-tube reactor, equipped with
turbo-molecular pumps. The lowest limit of the growth temperature was 300oC because
no growth was observed below this temperature. On the other hand, the highest limit
350oC, because the thickness distribution became too large above this temperature.
Source temperature is 110 oC and total pressure in reactor is 1 or 10 Pa.
Transport to surfaceSurface diffusionSurface reaction
Gas phase reactions
Redesorption of film precursor
Transfer of by-products to main flow
Desorption of volatile surface reaction products
NucleationIsland growth
Adsorption of film precursor
Step growth
Main gas flow region
Carrier gas, unreacted reactants, by-products
Carrier gas + reactants
Gas
Solid
151
Figure 7.2 Multi chamber ALD/CVD system
7.3 Atomic Layer Deposition
Atomic layer deposition (ALD) is a CVD technique suitable for manufacturing
inorganic material layers with thickness down to a fraction of a monolayer [7.18, 7.19].
ALD can be defined as a film deposition technique that is based on the sequential use of
self-terminating gas–solid reactions [7.20-7.22]. The growth of material layers by ALD
consists of repeating the following characteristic four steps [7.4]:
1) Source gas follow and a self-terminating reaction of the first reactant.
2) A purge or evacuation to remove the non-reacted reactants
3) Oxidant gas follow and a self-terminating reaction of the second reactant—or
another treatment to activate the surface again for the reaction of the first reactant
[7.23].
Furnace
Heater
Metal gas
H2O
TiW
RTA
Load lock
Sub.
Sputter
TMP
TMP
Ar (carrier gas)2 inch wafer
Heater
TMP exhaust
Hot-wall reactor
152
4) A purge or evacuation.
Step 1-4 constitute ALD reaction cycle. One cycle is illustrated schematically in Figure
7.3. Each reaction cycle adds a given amount of material to the surface, referred to as
the growth per cycle (GPC). To grow a material layer, reaction cycles are repeated until
the desired amount of material has been deposited [7.24].
Figure 7.3 Schematic illustration of one ALD reaction cycle [7.4]
ALD
reac
tion
cycl
e
Substrate before deposition
1)
2)
3)
4)
Source gas Oxidant gas Carrier gas
153
In this work, using chamber is the same as CVD process (Fig. 7.2). Ar is used as
Carrier gas and purge gas. H2O is used as oxidant gas. Source gas/H2O feed and purge
periods were 100 and 300 sccm, respectively. The gas-feed sequence of an ALD cycle is
schematically shown in Fig. 7.4.
Figure 7.4 Flow sequence of ALD
source feed Ar purge Ar purgeH2O feed
Source gas
H2O
time
0
0
0
Ar
ts tAr1 tH2O tAr2
source feed Ar purge Ar purgeH2O feed
Source gas
H2O
time
0
0
0
Ar
ts tAr1 tH2O tAr2
154
7.4 Process Condition and Film Properties
7.4.1 La2O3 Film
La2O3 insulators were prepared by ALD using La(iPrCp)3 and La(iPrFAMD)3 as the
metal source and H2O as the oxidant (Figure 7.5).
La(iPrCp)3 La(iPrFAMD)3
Figure 7.5 La source materials
7.4.1.1 La(iPrCp)3
Firstly, growth characterizations ALD using La(iPrCp)3 and H2O is considered.
Figures 7.6, 7.7, and 7.8 show, respectively, the effects of the La feed time (tS), H2O
feed time (tH2O), and Ts on the growth rate. Figure 7.6 shows that the growth rate does
not depend on tH2O for both the low Ts (175 °C) and high Ts (250 °C) conditions. In Fig.
7.7, the growth rate was almost constant for tS of 2.5 – 10 s when Ts was below 200 °C.
On the other hand, the growth rate increased with increasing tS at Ts higher than 200 °C.
These results indicate that Ts needs to be below 200 °C to achieve the self-limiting
growth and growth above 200 °C gives rise to the CVD-like mechanism. Figure 7.8
shows the Arrhenius plot of the growth rate in the Ts range from 135 to 250 °C. The
growth rate is only weakly dependent on Ts, with an activation energy of 12 kJ/mol
(0.12 eV). Fig. 7.6, 7.7, and 7.8 clearly show that La2O3 growth using La(iPrCp)3 and
H2O is self-limiting when the Ts is kept below 200°C.
La
C 3H7
3
L a
C 3H7
3
L a
C 3H7
3
CLaN
NH
C3H7
C3H7
155
La gas feed(2.5s)→Ar purge(10s)→H2O feed →Ar purge(100s)La gas feed(2.5s)→Ar purge(10s)→H2O feed →Ar purge(100s)
H2O feed time (s)
0
0.04
0.08
0.12
0.16
0.2G
row
th ra
te(n
m/c
ycle
)
Ts=150 oC
Ts=250 oC0.20
0 105
0.16
0.12
0.08
0.04
0
H2O feed time (s)
0
0.04
0.08
0.12
0.16
0.2G
row
th ra
te(n
m/c
ycle
)
Ts=150 oC
Ts=250 oC
0
0.04
0.08
0.12
0.16
0.2G
row
th ra
te(n
m/c
ycle
)
Ts=150 oC
Ts=250 oC0.20
0 105
0.16
0.12
0.08
0.04
0
Figure7.6 Dependence of growth rate on H2O feed time at 175 and 250
La gas feed→Ar purge(10s)→H2O feed(1s)→Ar purge(100s)
200 oC or higher Growth rate increases with feed time (CVD-mode)
175 oC or lower Growth rate hardly depends on La gas feed time (ALD-mode)
0
0.1
0.2
0.3
0.4
0 3 6 9 12
Gro
wth
rate
(nm
/cyc
le)
TS (oC)150175
200225
250
La gas feed time (s)
0
0.1
0.2
0.3
0.4
0 3 6 9 12
Gro
wth
rate
(nm
/cyc
le)
TS (oC)150175
200225
250
La gas feed time (s)
Figure7.7 Dependence of growth rate on La source feed time at various temperature
156
La gas feed(2.5s)→Ar purge(10s)→H2O feed(1s)→Ar purge(100s)La gas feed(2.5s)→Ar purge(10s)→H2O feed(1s)→Ar purge(100s)
0.01
0.1
1G
row
th ra
te(n
m/c
ycle
) Ea=12 kJ/mol(0.12 eV)
1.8 2.0 2.2 2.41000/T (K-1)
Ts=135~250 oC
100
10-1
10-2
Arrhenius plot
0.01
0.1
1G
row
th ra
te(n
m/c
ycle
) Ea=12 kJ/mol(0.12 eV)
1.8 2.0 2.2 2.41000/T (K-1)
Ts=135~250 oC
100
10-1
10-2
Arrhenius plot
Figure7.8 Arrhenius plot of growth rate. tS and tH2O were 2.5 s and 1 s.
Under the self-limiting growth condition, good thickness uniformity is observed
(Figure 7.9). Standard deviation of thickness is 1.8 percent.
Figure7.9 Thickness uniformity under self-limiting growth condition.
157
Table 7.2 shows comparison with the previous reports. In the previous studies,
growth temperature was in the range from 260 to 480 oC. Clear evidence of self-limiting
growth was not reported. In this study, self-limiting growth condition is clearly
identified at <200 oC.
Table 7.2 Comparison with past report
Additionally, we have found that Ar purge time after H2O feed is an important
process condition to realize self-limiting growth or to gain good thickness uniformity, as
shown below. Figure 7.10 shows growth rate uniformity along the gas flow direction in
the case of La(iPrCp)3. The Ar purge time is 10 or 100 seconds. Even if growth
temperature is 175 oC at which growth is self-limiting, it is understood that long purge
time of 100 seconds was necessary. In the case of 250 oC, CVD process contributes.
Contribution of the CVD growth becomes more remarkable with decreasing purge time.
Oxide source
Growth temperature Growth rate
S. Y. No et al. (Seoul National University)
J. Appl. Phys. 100, 024111 (2006) H2O 370 oC 0.09
nm/cycleW. He et al. (NUS,
Singapore; Samsung)J. Electrochem. Soc.
155, G189 (2008)H2O 260-480 oC 0.03-0.01
nm/cycle
S. Schamm et al. (CNR, Italy)
J. Electrochem. Soc., 156, H1
(2009)H2O 260 oC unknown
W.-S. Kim et al.(Hanyang University)
J. Vac. Sci Technol. B 26, 1588 (2008). O2 plasma 400 oC unknown
H. Jin et al. (NIMS; Chungbuk National
University; Samsung)
Appl. Phys. Lett. 93, 052904 (2008) Ozone 450 oC unknown
This study H2O < 200 oC 0.15
Oxide source
Growth temperature Growth rate
S. Y. No et al. (Seoul National University)
J. Appl. Phys. 100, 024111 (2006) H2O 370 oC 0.09
nm/cycleW. He et al. (NUS,
Singapore; Samsung)J. Electrochem. Soc.
155, G189 (2008)H2O 260-480 oC 0.03-0.01
nm/cycle
S. Schamm et al. (CNR, Italy)
J. Electrochem. Soc., 156, H1
(2009)H2O 260 oC unknown
W.-S. Kim et al.(Hanyang University)
J. Vac. Sci Technol. B 26, 1588 (2008). O2 plasma 400 oC unknown
H. Jin et al. (NIMS; Chungbuk National
University; Samsung)
Appl. Phys. Lett. 93, 052904 (2008) Ozone 450 oC unknown
This study H2O < 200 oC 0.15
158
The result that contribution of the CVD structure becomes larger with decreasing Ar
purge time shows La source reacts with the residual H2O of the infinitesimal quantity.
Purge gas flow used in this experiment replace the reactor 100 times per one second.
Reactor is tubular and has no dead volume. Nevertheless, residual H2O remains. It is
thought that source of the residual H2O is desorption at H2O from La2O3 (or the hydrate)
after H2O feed. As rare earth oxides have high hygroscopicity, this is the essential
problem when H2O is used as an oxidant. If O3 is used as an oxidant, this problem will
be avoided. However, in the case of O3, Si substrate oxidizes and EOT scaling becomes
more difficult.
0
0.05
0.1
0.15
0.2
0.25Ts=175 Ts=250 tAr2=10 s
tAr2=100 s
tAr2=10 s
tAr2=100 sGas Flow
waferGas Flow
wafer
Gro
wth
rate
(nm
/cyc
le)
Gro
wth
rate
(nm
/cyc
le)
Position in wafer (mm)Position in wafer (mm)-20 -2020 20100-100 10-10
0.8
0.6
0.4
0.2
0.20
0.10
Figure7.10 Effects of Ar purge time tAr2 on after H2O feed thickness uniformity. La source was La(iPrCp)3
and tAr was 10 or 100s. Data for TS = 175 and 250 are shown.
7.4.1.2 La(iPrFAMD)3
Figure 7.11 shows thickness profiles of the La2O3 film prepared by La(iPrFAMD)3
along the gas flow direction. TS was changed from 125 to 250 . At higher TS, there is
159
a tendency for growth rate to increase in the upstream part of the reactor. It is suggested
that the growth processed by the CVD mode. Thickness uniformity is improved with
decreasing TS. However even in that case, the growth rate increased with increasing La
source feed time. Therefore, the condition to realize a self-limiting growth was not
found for La(iPrFAMD)3.
Figure 7.11 Thickness profiles of La2O3 film along the gas-flow direction measured by charging TS from
125 to 250 . tS, tAr2 and tH2O were 10, 100 and 1s, respectively.
Gro
wth
rate
(nm
/cyc
le)
-20 2015-10 0 0Position in wafer (mm)
0.05
0.20
0.15
0.10
Gas Flow
wafer
Ts=250 °C
Ts=125 °C
Ts=175 °C
160
-20 2015-10 0
Gro
wth
rate
(nm
/cyc
le)
Position in wafer (mm)
Gas Flow
wafer
0
0.050.10
0.30
0.25
0.20
0.15
tLa= 10 s
tLa= 5 s
tLa= 2.5 s
Figure 7.12 Thickness profiles of La2O3 film along gas-flow direction. TS was fixed at 175 and tS
changed from 2.5 s to 10 s are compared.
The thickness uniformity dependence on Ar purge time was also observed for
La(iPrFAMD)3, similar to La(iPrCp)3 (Figure 7.13).
Ts=125 °CtAr2=10 s
tAr2=100 s
tAr2=10 s
tAr2=100 s
0.30
0.25
0.20
0.15
0.10
0.05
Ts=250 °C
Gas Flow
wafer
Gas Flow
wafer
0.30
0.25
0.20
0.15
0.05
0.10
-20 -2020 201000
-100
0 10-10
Position in wafer (mm)Position in wafer (mm)
Gro
wth
rate
(nm
/cyc
le)
Gro
wth
rate
(nm
/cyc
le)
Figure 7.13 La(iPrFAMD)3 source. Data for TS = 125 and 250
161
7.4.2 Ce-oxide Film
CeOX insulators were prepared by CVD using Ce(Mp)4 and ALD using Ce(EtCp)3
and Ce(iPrCp)3 as the metal source and H2O as the oxidant.
Ce(Mp)4 Ce(EtCp)3 Ce(iPrCp)3
Figure 7.14 Ce Source material using CVD or ALD
7.4.2.1 Ce(Mp)4
In this study, Ce(Mp)4 was used to form CeO2 in the CVD mode by thermal
decomposition. An important merit of Ce(Mp)4 is that we can obtain CeO2 films
without using an oxidant such as H2O, O2, and O3, because Ce(Mp)4 has oxygen atoms
in itself. This excludes any possibility of oxidizing the Si substrate in CVD, which is
preferable for forming a direct-contact interface. The growth temperature was
300-350oC, source temperature was 100 oC, and total pressures in reactor were 1 or 10
Pa. The lowest limit of the growth temperature was 300 oC because no growth was
observed below this temperature. The Ce(Mp)4 concentration in the Ar carrier gas was
estimated to be about 0.02 %.
Figure 7.15(a) shows the dependence of the growth rate on the temperature of
CVD. The Arrhenius plot of the same data set is shown as Fig.7.15(b). The growth rate
increased exponentially with increasing temperature, with an activation energy of 1.53
eV. This value is reasonable for the thermal decomposition of metal alkhoxides such as
162
Ce(Mp)4. For instance, the activation energy for the thermal CVD of SiO2 using Si
alkhoxide, Si(OC2H5)4 (TEOS), was reported to be 1.8 eV [7.25].
Figure 7.15 (a) Dependence of growth rate on temperature for CVD using Ce(Mp)4. (b) Arrhenius plot
of the same data. Circles and squares were obtained for total pressures of 1 and 10 Pa, respectively.
0
0.05
0.1
0.15
300 320 340 360 380Temperature (oC)
Gro
wth
rate
(nm
/s)
1 Pa
10 Pa
(a)
100
10-1
10-2
1.5 1.6 1.7 1.81000/T (K-1)
Gro
wth
rate
(nm
/s) Ea = 147 kJ/mol
(1.53 eV)1Pa
10Pa
(b)
163
As for the pressure dependence, the growth rate increases with increasing the total
pressure from 1 to 10 Pa. However, the pressure dependence was not linear: only a
twofold increase in the growth rate was observed as the pressure was increased by
tenfold. This sublinear behavior suggests that the growth took place via the surface
adsorption of Ce(Mp)4. Figure 7.16 shows a comparison of the thickness distribution
over a 2-in. wafer. The thickness uniformity is estimated to be 3.9 %.
Figure 7.16 Thickness distribution of CeOX films over 2-in. wafers. CVD using Ce(Mp)4 at growth
temperature of 350 oC and total pressure of 1 Pa.
Ce oxides have several crystalline phases. Although the cubic CeO2 phase is the
most stable one, Ce2O3 phases are also often observed [7.26]. To determine the Ce : O
ratio of the films, we carried out Rutherford backscattering spectroscopy (RBS), nuclear
reaction analysis (NRA), and secondary ion mass spectroscopy (SIMS) for selected
samples. Figure 7.17 shows those analysis results. These measurements showed that the
Ce : O ratio was indeed 1 : 2 for the samples grown by CVD using Ce(Mp)4. It also
σ = 3.9%
Gas flow
164
showed that the carbon impurity concentration was about 3.5 % for the as-deposited
samples.
(a)
(b)
165
Figure 7.17 (a) Nuclear reaction analysis, (b) Rutherford backscattering spectroscopy, and (c) Depth
profile of sample.
The X-ray diffraction (XRD) spectrum of the CVD- CeO2 film agreed well with
the powder pattern of the cubic CeO2 peak (Figure 7.18). Therefore, this film was
considered polycrystalline CeO2 with random orientation.
Figure 7.18 XRD analyses of CVD-CeO2 films
Figure 7.18 XRD analyses of CVD-CeO2 films
0
500
1000
1500
2000
2500
3000
3500
4000
4500
10 20 30 40 50 60 70 80
ntensty(cps)
2 Theta (degrees)
111
200
220311
222 4000
500
1000
1500
2000
2500
3000
3500
4000
4500
10 20 30 40 50 60 70 80
ntensty(cps)
2 Theta (degrees)
111
200
220311
222 400
(c)
Inte
nsity
(cps
)
166
Owing, to this polycrystalline structure, the surface roughness of the CVD CeO2
films increased with thickness. Figure 7.19 shows the atomic force microscopy (AFM)
observation. The root-mean-square (RMS) surface roughness measured by atomic force
microscopy (AFM) was 0.22 nm at a thin thickness of 2 nm, but it increased to 0.64 nm
at a film thickness of 5.3 nm. Since the CeO2 thickness in the scaled gate stack is ~1 nm
[7.26], the surface roughness mentioned above is within acceptable range.
Figure 7.19 AFM observational results for CVD-CeO2 films
The optical properties of the CeO2 films were investigated by spectroscopic
ellipsometry (SE). Figure 7.20 shows the spectra for the refractive index nSE and the
extinction coefficient kSE for the as-deposited films. The band gap estimated by the Tauc
method was 3.2 eV for. This value is in good agreement with the literature data for
CeO2 [7.27]. The nSE value at the He–Ne laser wavelength (663 nm or 1.96 eV) were
2.0 for the sample. The peak intensity of kSE at 3.95 eV and the nSE values in the
AFM (500 nm x 500 nm)
RMS 0.64 nm
RMS 0.22 nm
350ºC CVDd = 2.0 nm
350ºC CVDd = 5.3 nm
167
transparent range are generally related to the crystallinity and density of the films,
respectively.
Figure 7.20 Refractive index nSE and extinction coefficient kSE for CeO2 films prepared by the CVD
process
7.4.2.2 Ce(EtCp)3 and Ce(iPrCp)3
Ce(EtCp)3 and Ce(iPrCp)3 were used to form CeO2 in the ALD mode. The growth
conditions for ALD processes are shown as follow. The growth temperatures are
175-250oC. The highest limit for this process was 250oC, because the thickness
non-uniformity became too large above this temperature. One ALD cycle consisted of
Ce feed, Ar purge (10 s), H2O feed (1 s), and Ar purge (100 s). The Ce feed time is 5
and 2.5 s for the Ce(iPrCp)3 and Ce(EtCp)3 sources, respectively.
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3 4 5 6 7 8
refractive index:nex
tinct
ion
coef
ficie
nt:k
Photo energy (eV)
k
n
168
Figure 7.21 shows the growth rates for ALD. Growth rate increases as the
temperature increases to 250 oC from 175 oC. The extent of increase, however, was not
as large as that in Fig. 7.15, because the growth took place via hydrolysis. The data
using the Ce(iPrCp)3 source show that the growth rate increases with increasing
Ce(iPrCp)3 source temperature, i.e., the concentration of Ce(iPrCp)3 in the Ar carrier gas.
This implies that the growth is not self-limiting. Indeed, the experiments a changing the
Ce feed time (data not shown) also showed that the growth rate increases in proportion
to the feed time. The same growth characteristics were observed for Ce(EtCp)3. Thus,
strictly speaking, the film growth using the Ce(iPrCp)3 and Ce(EtCp)3 is not ALD and
should be called flow-modulated CVD. By comparing Ce(iPrCp)3 and Ce(EtCp)3, the
growth rates for Ce(EtCp)3 at a source temperature of 135 oC were found lower than the
corresponding rates for Ce(iPrCp)3 at a source temperature of 110 oC. This result is
presumably, due to the higher vapor pressure of Ce(iPrCp)3 than that for Ce(EtCp)3.
169
Figure 7.21 Dependence of growth rate on temperature for ALD using Ce(iPrCp)3 and Ce(EtCp)3. Circle
and squares were obtained for the Ce(iPrCp)3 source kept at 140 and 110 oC, respectively. The triangle
plots are for the Ce(EtCp)3 source kept at 135 oC.
Figures 7.22 show a comparison of the thickness distributions over a 2-in. wafer
for the using Ce(EtCp)3 films. Although the thickness uniformity for CVD (Fig.7.16) is
acceptable, the films prepared using Ce(iPrCp)3 and Ce(EtCp)3 showed much larger
thickness nonuniformity [σ = 20 % for Ce(EtCp)3] along the gas flow. This
nonuniformity is ascribed to the absence of a selflimiting mechanism for these Ce
sources, as mentioned above.
0
0.05
0.1
0.15
0.2
0.25
0.3
150 200 250
ALD-Ce(iPrCp)3 (source : 140)
Temperature (oC)
Gro
wth
rate
(nm
/s)
ALD-Ce(iPrCp)3 (source : 110)ALD-Ce(EtCp)3 (source : 135)
170
Figure 7.21 Thickness distribution of CeOX films over 2-in. wafers. ALD using Ce(EtCp)3 at growth
temperature of 250 oC .
Figure 7.22 show the AFM observation of ALD. The RMS roughness of the ALD-
CeO2 films was less than 0.2 nm. This RMS roughness is better than those for the CVD
films.
Figure 7.22 AFM images measured for ALD-CeO2 films
Gas flow
σ = 20%
AFM (500 nm x 500 nm)
RMS0.18nm
250ºC ALD-Ce(EtCp)3d = 3 nm
171
Figure 7.23 shows the spectra for the refractive index nSE and the extinction
coefficient kSE for the as-deposited films. The band gap estimated was 3.2 eV for both
films. This value is in good agreement with the literature data for CeO2. The kSE peak
using Ce(iPrCp)3 film near the band gap energy was larger than using Ce(EtCp)3 film.
The nSE values at the He–Ne laser wavelength 1.7 for both samples. Comparing the
CVD film with the ALD film, we find that the CVD film had a higher crystallinity and a
higher density than the ALD films because the former was grown at a higher
temperature.
Figure 7.23 Refractive index nSE and extinction coefficient kSE for CeO2 films prepared by ALD
processes.
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3 4 5 6 7 8
refractive index:nex
tinct
ion
coef
ficie
nt:k
Photo energy (eV)
k
ALD by Ce(iPrCp)4
n
ALD by Ce(EtCp)3
172
7.5 Electrical Properties of MOS Devices
7.5.1 La2O3 Film Devices
Figure 7.24 shows the C-V characteristics of La2O3 insulators prepared by ALD is
using La(iPrCp)3 (Cp 250o and Cp 175o) and La(iPrFAMD)3.
Figure 7.24 Comparison of C-V characteristics of La2O3 insulators prepared by La(iPrCp)3 and
La(iPrFAMD)3. All films received PMA at 500 oC and not in-situ process.
100
10-1
10-2
10-3
10-4
101
102
103
104
J at
V =
+1.
0V (A
/cm
2 )
10-5
0.5 1.0 1.5 2.0EOT (nm)
ITRS requirements
HP(Vdd=0.8-1V)LOP(Vdd=0.8-0.95V)
LSTP(Vdd=0.95-1.05V)Cp 250
Cp 175
Amidinate 250
EB
Cp 250 oCCp 175 oC
PMA 500 oC100 kHz
amidinate 250 oC
Cap
acita
nce
dens
ity (µ
F/cm
2 )
Gate voltage (V)-1 0 0.5 1.0 1.5-0.5
0
0.4
0.8
1.2
1.6
2.0ideal Vfb=0.3V
Growth rate
(nm/cycle)
Thickness(nm)
EOT(nm) k Vfb
(V)
Cp(Ts=175 ) 0.15 5.2 1.68 ~12 0.26
Cp(Ts=250 ) 0.17 5.5 1.73 ~12 -0.26
Amidinate(Ts=175 )
It is not possible measure because of leakage current.
Amidinate(Ts=250 ) ~0.14 － 1.45 － -0.09
Growth rate
(nm/cycle)
Thickness(nm)
EOT(nm) k Vfb
(V)
Cp(Ts=175 ) 0.15 5.2 1.68 ~12 0.26
Cp(Ts=250 ) 0.17 5.5 1.73 ~12 -0.26
Amidinate(Ts=175 )
It is not possible measure because of leakage current.
Amidinate(Ts=250 ) ~0.14 － 1.45 － -0.09
173
The leakage properties of the La(iPrFAMD)3 sample are better than those using
La(iPrCp)3. However, the sample denoted as ‘Cp 175o’ (using La(iPrCp)3 source and
growth temperature is 175oC) only showed self-limiting growth. Therefore, we selected
La(iPrCp)3 as the La source and fabricated the MOS devices under self-limiting
condition. Figure 7.25 show the C-V and J-V characteristics of as-deposition and 500 oC
PMA sample. As-deposited sample showed a large hump near the Vfb and small
hysteresis. These problems are improved by PMA at 500 oC. The k-value was estimated
about 12. Although increasing EOT was so small, leakage current was improved by the
PMA treatment.
Figure 7.25 C-V characteristics of MOS capacitor with La2O3 prepared by La(iPrCp)3 deposited at 175 oC
Figure 7.26 (a) and (b) show C-V and J-V characteristics of MOS capacitors with
ALD at 175, 250, and 300 oC. Figure 7.27 shows the electrical properties of MOSFET
for the same set of the samples.
0.0
0.4
0.8
1.2
1.6
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5Gate Voltage [V]
Cap
acita
nce
dens
ity [ µ
F/cm
2 ]
As-depo
FGA500
EOT : 1.82nmVFB : -0.19V
EOT : 1.9nmVFB : -0.16V
20 x 20μm@100 kHz
0.0
0.4
0.8
1.2
1.6
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5Gate Voltage [V]
Cap
acita
nce
dens
ity [ µ
F/cm
2 ]
As-depo
FGA500
EOT : 1.82nmVFB : -0.19V
EOT : 1.9nmVFB : -0.16V
20 x 20μm@100 kHz
1.E-06
1.E-04
1.E-02
1.E+00
1.E+02
1.E+04
0 1 2 3Gate Voltage [V]
J g [A
/cm
2 ]
As-depo500oC 30min
174
Figure 7.26 C-V and J-V characteristics with different PMA conditions.
It is known that the formation of interfacial layer (La-silicate) depends on the
process temperature [7.28]. Therefore, it is reasonable that the EOT value was increased
by ALD at higher-temperatures. Despite this EOT increase, leakage current was also
increased (Fig.7.26). This could be due to higher carbon concentration by the
non-self-limiting growth at higher temperatures, or partial crystallization of the La2O3
film.
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-1 -0.5 0 0.5 1 1.5
Gate Voltage [V]
Cap
acita
nce
dens
ity [ µ
F/cm
2 ] 100k
100k
100k
175oC250oC300oC
1.E-06
1.E-04
1.E-02
1.E+00
1.E+02
1.E+04
0 1 2 3
Gate Voltage [V]
J g [A
/cm
2 ]
175oC 250oC
300oC
..
(a)
(b)
175
Figure 7.27 Electrical characteristics of MOSFETs with different annealing temperature (black: 175, red:
250, and blue: 300 oC).
Vg=0~1V by 0.2V
W/L = 20/20µm
175oCEOT:1.78nm
250oCEOT:1.78nm
300oCEOT:2.16nm
W/L = 20/20µm
W/L = 20/20µm
175oC250oC300oC
EOT:1.78nm
EOT:2.16nm
176
Figure 7.28 shows the cross-section TEM images for EB-deposited and ALD films.
La-silicate was formed at interface in both samples. But the interfacial contrast in the
ALD sample was brighter than that for EB-deposited sample. Thus, the dielectric
constant of La-silicate in ALD film is lower than EB films. Although the dielectric
constant is slightly small, C-V curve is similar to ideal curve and hump is smaller for
the ALD sample. Therefore, the MOS properties for the ALD films are comparable to
these for the EB deposited films.
Figure 7.28 TEM image and C-V characteristics obtained by using EB deposition or ALD process.
2.8nm
0.8nm1nm
La2O3
IL
ALD
La-silicate
2nm
2nm
1nm
La2O3
BE
-0.5 0 0.5Gate voltage (V)
1.0
1.5
1.0
0.5
0-1.0
Cap
acita
nce
(µF/
cm2 )
2.5
2.0 EOT=1.3nm
BE
100kHz
-1.0 -0.5 0 0.5 1.0
EOT=1.55nmALD
100kHz
177
7.5.2 CeO2 Single Layer
Figure 7.29 shows the effects of 500 oC annealing on the C-V characteristics for
CeO2 MOS capacitors. (a) is CVD using Ce(Mp)4 at 350 oC and under 1Pa. (b) is ALD
using Ce(EtCp)4 at 250 oC. Problem of hysteresis is improved by 500 oC PMA for both
MOS capacitors using ALD and CVD. About the CVD sample (a), Vfb after PMA was
+0.21 V which was close to the ideal value, +0.3 V. By fitting the 100 kHz data using
CVC program, EOT for the 11 nm-thick film was 1.94 nm and the dielectric constant
was 22. It was observed that the C-V characteristics for CVD-CeO2 tend to exhibit
frequency dispersion under the accumulation condition. This is due to either a high
density of trapping states near the conduction band edge of Si, or the dielectric
relaxation effect. As for the ALD sample, PMA was also effective to suppressed
hysteresis and leakage current. Vfb after PMA was equal to that for CVD-CeO2, +0.21 V.
Figure 7.29 (c) shows a benchmark plot of the leakage characteristics. The leakage
current of the CVD sample was smaller than that for the ALD using sample. This might
be due to difference in the growth temperature. The growth temperature of CVD process
is higher than ALD process, thus, the film density of CVD process film is also high.
Therefore, leakage current was suppressed.
178
Figure 7.29 Effects of 500 oC annealing on the C-V characteristics of CeO2 MOS capacitors. (a)CVD at
350 oC and under 1Pa. (b) ALD at 250 oC
2.5
2.0
1.5
1.0
0.5
0-0.5 0 0.5 1 1.5
Gate voltage (V)
Cap
acita
nce
(µF/
cm2 )
500 anneal
As-depoEOT = 1.97nmVfb = +0.21V
d = 11nm
k ~ 22
500 anneal3.0
-0.5 0 0.5 1 1.5
Gate voltage (V)
500 anneal
As-depoEOT = 1.97nmVfb = +0.21V
d ~ 12nm
500 anneal (b)(a)
100kHz 100kHz
ALD-CeO2
CVD-CeO2
(c)
179
Figure 7.30 shows the electrical properties of MOSFET by CVD process at 350 oC.
EOT was estimated to 1.56 nm from Cgc curve. Vth and S factor were 0.36 V and 68,
respectively. Peak mobility was 254 cm2/Vs. Thus, a normal operation of MOSFET was
confirmed for the CeO2 gate state.
Figure 7.30 Electrical characteristics of MOSFET with Ce(Mp)4-CVD film. (a) Cgc, (b) Id-Vg, (c) Id-Vd,
and (d) effective mobility.
300
250
200
150
100
20
00.2 0.4 0.6 0.8 1.0
Eeff (MV/cm2)
µ eff
(cm
2 /Vs)
1.8
1.5
1.2
0.9
0.6
00 0.5 1.0 1.5Gate voltage (V)
Cgc
(µF/
cm2 )
-0.5
0.3 EOT = 1.56 nm
1.0
0.8
0.6
0.4
00.2 0.4 0.6 0.8 1.0
Drain voltage (V)
Dra
in c
urre
nt (×
10-4
A)
0.2
Vg=0~1V by 0.2V
10-3
Dra
in c
urre
nt (A
)
10-4
10-5
10-6
10-7
10-8
10-9
10-10
0 0.5 1.0 1.5Gate voltage (V)
-0.5
Vds=0.05 V
Vds=1.0 V(a) (b)
(c)Vg=0~1V by 0.2V
(d)
W/L = 20/20µm
180
Figure 7.31 shows cross-section TEM images for the EB-deposited and CVD film.
Interfacial layer was formed in both samples. The dielectric constant in CVD film is
slightly smaller than BE deposited film. However, C-V curve is similar to EB-deposited
sample and can be well fitted by the ideal curve. Therefore, CVD process film has
comparable properties to the EB deposited film.
Figure 7.31 TEM image and C-V characteristics measured by using EB deposition or CVD process.
10nm
1nm1nm
CVD
CeO2
IL
10nm
1nm1nm
CVD
CeO2
IL3.8nm
0.6nm1nm
Ce-oxide
IL
EB
2.5
1.5
1.0
0.5
0-1.0 -0.5 0 0.5 1.5
Gate voltage (V)
Cap
acita
nce
(µF/
cm2 )
1.0
2.0
100k
EBEOT=1.17nm(k =26 )
-1.0 -0.5 0 0.5 1.51.0
CVD
100k
EOT=1.17nm(k = 22)
181
7.5.3 La2O3 and CeO2 Stacked Film
In this section, we discuss the electrical properties of the gate dielectrics composed
of the CVD-CeO2, using Ce(Mp)4 source, and ALD- La2O3 ,using La(iPrCp)3 source. In
chapter 4, we showed that the electrical properties of EB-deposited CeO2/La2O3
structured device were better than La2O3 single layered device. We fabricated the
CVD-CeO2/ALD-La2O3 structured device for confirm the effects for the different
film0formation process. Additionally, La2O3/CeO2 stacks structured device was also
fabricated to further study compare the effect of stacking La2O3 and CeO2.
Figures 7.32 (a) and (b) show the TEM images for the CeO2/La2O3 and
La2O3/CeO2 stack structures formed by CVD/ALD. These images were taken for the
samples without PMA. La2O3 ALD was carried out for 25 cycles, targeting La2O3
thickness of 3 nm. CeO2 CVD was carried out for 12 s, targeting CeO2 thickness of 0.4
nm. The total physical thickness for Fig.7.32 (a), tphys, is 2.7 nm, which is close to the
sum of the target thicknesses. The total thickness for Fig. 7.32(b) is 2.2 nm, which is
thinner than (a). The cause for this difference may be slower growth rate of La2O3 on
CeO2 than that on Si. Figures 7.32 (c) and (d) show the corresponding that were taken
for the samples after PMA. The results of Fig. 7.32 show that the interface layer with
bright contract is more clearly seen for the La2O3/CeO2 structure than the CeO2/La2O3
one. Figure 7.31(b) shows a TEM image for a single-layer CVD-CeO2. The interface
layer with bright contrast is also observed clearly. Thus the silicate formation in the
stack structure is controlled by the kind of the layer that is in contact with the Si
substrate. Since the silicate layer is seen for the sample without PMA (Fig. 7.32(b)),
CeO2 deposition on Si at 350˚C by itself induced the silicide formation.
182
Figure 7.32 TEM images of CeO2/La2O3 and La2O3/CeO2 gate stacks with and without PMA.
The FET characteristics for CeO2/La2O3 and La2O3/CeO2 gate stacks were
investigated. The characteristics for La2O3 single-layer gate dielectrics were also
measured as the control sample. Figs. 7.33 (a), (b) and (c) are gate-channel capacitance
(Cgc), drain current-gate voltage (Id-Vg) curves, at drain voltage Vd of +0.05 V, and
2.7nm 2.2nm
2.4nm
0.6nm
1.7nm
0.7nm
(a) (b)
(c) (d)
183
effective mobilities, µeff, as a function of the effective electrical field, Eeff, respectively.
The EOT values estimated from the Cgc data were 1.39, 1.80, and 1.77 nm for
CeO2/La2O3, La2O3/CeO2, and La2O3, respectively. The Vth values for the La2O3 and
CeO2/La2O3 devices were 0.12 and 0.16 V, respectively. These Vth values are close to
each other because the interface structures are common (i.e., La2O3 on Si) between these
devices. These Vth values were negatively shifted from the ideal values. On the other
hand, Vth for La2O3/CeO2 was 0.32 V. Thus the negative shift in Vth was smaller for the
La2O3/CeO2 structure than for CeO2/La2O3, which is consistent with the Vfb shifts as
discussed above. Subthreshold slopes were 68, 67, and 68 mV/decade for CeO2/La2O3,
La2O3/CeO2, and La2O3, respectively. Therefore, interface state densities were almost
the same among these three structures.
In Fig. 7.33(c), the peak mobility was about 250 cm2/Vs for all the samples. The
shapes of µeff-Eeff curves were also almost the same. La2O3/CeO2-device show slightly
lower µeff under high Eeff. This may be due to increased roughness caused by the
formation of the interfacial silicate layer. It should be reminded that EOT for the
CeO2/La2O3 stack structure is smaller than those for the La2O3 single layer and
La2O3/CeO2 stack structure. Therefore, Fig. 7.33(c) implies that deposition of CeO2 on
La2O3 is effective for achieving EOT scaling without degrading the mobility.
184
Figure 7.33 MOSFET characteristics for CeO2/La2O3 and La2O3/CeO2 gate stacks and La2O3 single
layered sample.
In Fig 7.34, peak mobilities are plotted as a function of EOT for MOSFETs with
La2O3-based gate dielectrics by EB evaporation and CVD/ALD. The mobility of
MOSFETs with ALD-La2O3 deposited gate insulator was found to be 10~20 % lower
than that of EB deposition. However, it was confirmed that the CVD-CeO2 capped over
ALD-La2O3 gate insulator has improved on the mobility. The same effect was observed
-0.5 0 0.5 1.0 1.5
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
Gate voltage (V)
Gat
e cu
rren
t (A
)
Vd = 0.05 VW/L = 20/20 µm
(b)
0
300
250
200
150
100
50
0.2 0.4 0.6 0.8 1.0
Effe
ctiv
e m
obili
ty (c
m2 /V
s)
Effective electrical field (MV/cm)
(c)
2.0
1.5
1.0
0.5
0-0.5 0 0.5 1.0 1.5
Gate voltage (V)
Cap
acita
nce
(µF/
cm2 )
La2O3(EOT = 1.77 nm)
CeO2/La2O3(EOT = 1.39 nm)
La2O3/CeO2(EOT = 1.80 nm)
(a)
185
for the case of EB evaporation. Thus, the CeO2/La2O3 stack structure is promising for
mitigating mobility degradation
.
Figure 7.34 peak mobility vs EOT for MOSFETs with La2O3-based gate dielectrics by EB evaporation
and CVD/ALD.
We finally comment on leakage current characteristics for the La2O3/CeO2,
CeO2/La2O3, and La2O3. In Fig.7.35, leakage current densities measured at Vg – Vfb = 1
V are plotted as a function of EOT. Data for both ALD/CVD and EB evaporation
samples are shown. It is seen that the leakage characteristic for the ALD/CVD samples
were nearly comparable to those for the EB deposited samples.
1.41.2 2.0
400
300
200
100
0
EOT (nm)
Peak
mob
ility
(cm
2 /Vs)
CeOx/La2O3(EB)
1.6 1.8
La2O3(EB)
CeOx/La2O3(CVD/ALD)
La2O3(ALD)
La2O3/CeO2(ALD/CVD)
186
Figure 7.35 Leakage current vs EOT for MOS capacitors with La2O3-based gate dielectrics by EB
evaporation and CVD/ALD at Vg-Vfb=1 V
7.6 Summary and Conclusions
In this chapter, we investigated La2O3 and CeO2 formed by ALD/CVD processes,
in order to confirm that the good electrical properties of the CeO2/ La2O3 structure,
which was realized by EB evaporation, can be achieved by the ALD/CVD processes.
The La2O3 and CeO2 films with properties comparable to those for EB-deposited films
could be formed using ALD process at 175 oC and CVD process at 350 oC, respectively.
The dielectric constant for ALD-La2O3 was slightly smaller than that for EB-evaporated
La2O3.
103Le
akag
e cu
rren
t den
sity
(A/c
m2 )
102
101
100
10-1
10-2
10-3
10-40.5 0.7 0.9 1.1 1.3 1.5 1.7
EOT (nm)
Vg - Vfb = 1 V
CeO2/La2O3(CVD/ALD)
La2O3(ALD)
La2O3 (EB)
CeO2/La2O3 (EB)
La2O3/CeO2(ALD/CVD)
187
In both single layered devices, which are La2O3/CeO2 and CeO2/La2O3 gate
dielectrics, normal operation of MOSFETs was confirmed. The effective k value was
higher for CeO2/La2O3 than La2O3/CeO2. This was due to the silicate formation induced
by CeO2 deposited on Si. Although CeO2 with Si contact causes EOT increase, the
stacks with CeO2/Si interface showed the Vfb and Vth values that are close to the ideal
ones. We compared the MOSFET properties among ALD-La2O3,
CVD-CeO2/ALD-La2O3, and EB-La2O3, EB-CeO2/EB-La2O3 gate dielectrics. The
mobility of ALD-La2O3 deposited gate insulator device was lower than that of EB
deposition devices. However, the CVD-CeO2 capped over ALD-La2O3 gate insulator
has the same improving effect on the mobility as that of EB-CeO2 capped over
EB-La2O3. Additionally, it was observed that leakage current characteristics for
ALD/CVD samples were almost comparable to those for EB evaporated samples.
188
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[7.20] No universally accepted definition of ALD is currently available. The definition
used in this work is built on the recognized practice of ALD and covers most of ALD
processes with compounds as well as elements as reactants. Also other distinctively
different definitions have been suggested, for example, that the GPC should be a
monolayer or the GPC should be constant over the cycles. Most ALD processes do not
fulfill these criteria, however.
190
[7.21] In addition to “self-terminating” used to refer to ALD reactions in this work,
ALD reactions have been referred to being saturating, selflimiting, self-extinguishing,
etc.
[7.22] In this review, ALD is defined to be based on gas–solid reactions. Analogous
experiments have been made from liquid phase (e.g., S. Lindroos, T. Kanniainen, and M.
Leskelä, Appl. Surf. Sci. 75, 70 (1994)) and electrochemically (e.g., J. L. Stickney,
Electroanal. Chem. 21, 75 (1999)) as well. Although in some publications such
experiments may be classified as ALD, in this work they are excluded from the
definition.
[7.23] Instead of the reactant of Reactant B, Step 3 may be, for example, a thermal
treatment.
[7.24] Some ALD processes consist of repeating the self-terminating reactions of more
than two reactants, for example, the WF6/BEt3/NH3 (Et =ethyl) process to grow
WCxNy (e.g., A. Martin Hoyas, J. Schuhmacher, D. Shamiryan, J. Waeterloos, W.
Besling, J. P. Celis, and K. Maex, J. Appl. Phys. 95, 381 (2004)). Each new reactant
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191
Chapter 8
Summary and Conclusions
192
In this chapter, the summary of systematic studies conducted on rare-earth oxides
for EOT scaling and charge defect density reduction in gate dielectrics is presented. The
impact of these studies on device performance is also described.
1. The electrical preparation of rare-earth oxide
As described in chapter 3, the rare-earth-oxides (REOX) are predominant
candidates for gate insulator material of MOS devices in the near future. The electrical
properties of MOS devices using the oxide of one of the RE-elements such as La, Ce, Pr,
Nd, Eu, Gd, Tm oxide as gate insulator were investigated. Among these RE-oxides,
La2O3 was recognized as the most promising material in our studies because of its
ability to form contact with Si substrate through the formation of a La-silicate layer at
the La2O3/Si interface. This interfacial layer has a higher dielectric constant than SiO2
which is commonly formed at high-k/Si. Although La2O3 can be characterized by its
low interface state density, wide band gap and high dielectric constant, Si-rich
interfacial La-silicate layer formed at low temperature thermal process, does not have
dielectric constant large enough for ultra-thin EOT purposes. Furthermore, generation of
fixed charges in Si-rich La-silicate layer remains an issue which needs to be solved. To
suppress the formation of Si-rich La-silicate layer, we examined the combination of
other RE-oxides in multi-layer gate stack structures.
2. Charged defect density reduction and EOT scaling
As described in chapter 4, Ce-oxide capping of La2O3 to reduce charged defect
density in La-silicate was examined. Adjusting oxygen concentration to the minimum
point of total charged defect density was the objective of this approach and both
193
theoretical calculations and experimental studies were carried out to confirm the
effectiveness of this method for reduction of charged defect density.
As described in chapter 5, Tm- or NdOX were examined to suppress the formation
of silicate layer with low dielectric constant by reducing radical oxygen atoms
generation within the capping layer. This allowed for further EOT scaling in our device
results. Especially, by capping La2O3 with NdOX, EOT<0.5 nm was achieved.
Furthermore, high-temperature spike annealing and decreasing the thickness of gate
metal were found to be effective methods for EOT scaling.
As described in chapter 6, the introduction of CeOX, NdOX (or TmOX) into La2O3
high-k film were proved to be the best combination of elements for reduction of both
charged defect density and EOT. This capping technique in combination with
high-temperature spike annealing and decreasing metal gate thickness, enabled further
EOT scaling.
3. Formation of RE-oxides by CVD and ALD processes
In preceding chapters, the RE-oxides used in experiments were deposited by
Electron Beam evaporation (EB). However from the semiconductor manufacturing
viewpoint, CVD and/or ALD deposition methods are preferable. We developed ALD
technique for La2O3 film deposition and CVD for CeO2 deposition. The dielectric
constant of both ALD-La2O3 and CVD-CeO2 deposited films were 10~20% smaller
than that of EB deposition. Also the mobility of MOSFETs with ALD-La2O3 deposited
gate insulator was found to be 10~20% lower than that of EB deposition. However, it
was confirmed that the CVD-CeO2 capped over ALD-La2O3 gate insulator has the same
improving effect on the mobility as that of EB-CeO2 capped over EB-La2O3.
194
In conclusion, RE-oxides are predominant materials for reduction of charged
defect density and EOT scaling in gate insulator of MOS devices. By combining La2O3
with CeOX and NdOX in a multi-layer gate stack structure, charged defect density
reduction and EOT scaling could be achieved. Furthermore, using high-temperature
spike annealing and reducing the gate metal thickness enabled continues reduction of
EOT. It can be concluded that La2O3, CeOX, and NdOX gate stack structures were the
optimum combination of RE- oxides.
Considerably good electrical properties of MOS devices with La2O3, CeO2 and
CeO2/La2O3 gate insulator by using CVD/ALD deposition method were confirmed.
However it was found that further improvements in CVD and ALD techniques is
needed in order to achieve higher dielectric constant and mobility as those obtained in
EB deposition method.
195
Publications and Presentations (a) Publications
1. Miyuki Kouda, Kuniyuki Kakushima, Parhat Ahmet, Kazuo Tsutsui, Akira
Nishiyama, Nobuyuki Sugii, Kenji Natori, Takeo Hattori, and Hiroshi Iwai, ‘Rare
Earth Oxide Capping Effect on La2O3 Gate Dielectrics for Equivalent Oxide Thickness
Scaling toward 0.5nm’
Jnp. J. Appl. Phys., 50(10) (4 pages) 2011 10PA04
2. Miyuki Kouda, Kenji. Ozawa, Kuniyuki Kakushima, Parhat Ahmet, Yuji Urabe, and
Tetsuji Yasuda, ‘Preparation and Electrical Characterization of CeO2 Films for Gate
Dielectrics Application: Comparative Study of Chemical Vapor Deposition and Atomic
Layer Deposition Processes’
Jap. J. Appl. Phys., 50(10) (4 pages) 2011 10PA06
3. Miyuki Kouda, Kuniyuki Kakushima, Parhat Ahmet, Kazuo Tsutsui, Akira
Nishiyama, Nobuyuki Sugii, Kenji Natori, Takeo Hattori, and Hiroshi Iwai, ‘Interface
and electrical properties of Tm2O3 gate dielectrics for gate oxide scaling in MOS
devices’
J. Vac. Sci. Technol., B 29(6) (4 pages) 2011 062202
196
(b) International Presentations
1. Miyuki Kouda, Naoto Umezawa, Kuniyuki Kakushima, Parhat Ahmet, Kenji
Shiraishi, Chikyow Toyohiro, Keisaku Yamada and Hiroshi Iwai (Oral)
VLSI Symposium Technology 2009 ‘Charged defects reduction in gate insulator with
multivalent materials’, 10B-3, Kyoto June 2009
2. Miyuki Kouda, Kuniyuki Kakushima, Parhat Ahmet, Akira Nishiyama, Kazuo
Tsutsui, Nobuyuki Sugii, Kenji Natori, Takeo Hattori and Hiroshi Iwai (Oral)
2011 International Workshop on IWDTF ‘Rare earth oxide capping effect on La2O3 gate
dielectrics toward EOT of 0.5 nm’, S2-2, Tokyo January 20-21, 2011
3. Miyuki Kouda, Kenji Ozawa, Kuniyuki Kakushima, Parhat Ahmet, Hiroshi Iwai,
Yuji Urabe and Tetsuji Yasuda (Poster)
2011 International Workshop on IWDTF ‘Preparation and electrical characterization of
CeO2 films for gate dielectrics application: comparative study of CVD and ALD
processes’, P-4, Tokyo January 20-21, 2011
4. Miyuki Kouda, Kiichi Tachi, Kuniyuki Kakushima, Parhat Ahmet, Kazuo Tsutsui,
Nobuyuki Sugii, A. N. Chandorkar, Takeo Hattori and Hiroshi Iwai (Oral) 214th ECS
Meeting, Honolulu, Octover 12-17, 2008. ECS Transactions 16(5) 153(2008)
‘Electrical properties of CeOx/La2O3 stack as a gate dielectric for advanced MOSFET
technology’
5. Miyuki Kouda, Kuniyuki Kakushima, Parhat Ahmet, Akira Nishiyama, Kazuo
197
Tsutsui, Nobuyuki Sugii, Kenji Natori, Takeo Hattori and Hiroshi Iwai (Oral) 220th
ECS Meeting, Boston, Octover 9-14, 2011. ECS Transactions 41(7) 119(2011)
‘Electrical Properties of Rare-Earth Oxides and La2O3 Stacked Gate Dielectrics’
(c) Domestic Presentations
1. Miyuki Kouda, Takamasa Kawanago, Kuniyuki Kakushima, Parhat Ahmet, Kazuo
Tsutsui, Nobuyuki Sugii, Takeo Hattori and Hiroshi Iwai, ‘Analysis of Leakage Current
through Sc2O3 Gate Dielectric Film’, 68th Japan Society of Applied Physics (JSAP)
Autumn Meeting, Sapporo, Japan, August, 2007
2. Miyuki Kouda, Kiich Tachi, Kuniyuki Kakushima, Parhat Ahmet, Kazuo Tsutsui,
Nobuyuki Sugii, Takeo Hattori and Hiroshi Iwai, ‘Electrical properties of CeO2/La2O3
gate dielectric film’, 55th Japan Society of Applied Physics (JSAP), Chiba, Japan,
March, 2008
3. Miyuki Kouda, Naoto Umezawa, Kuniyuki Kakushima, Parhat Ahmet, Kenji
Shiraishi, Toyohiro Chikyo, Keisaku Yamada, and Hiroshi Iwai, ‘Charged defects
reduction in high-k gate dielectrics with multivalent cerium oxide’, 14th Gate stack
seminar, Shizuoka, Japan, January, 2009.
4. Miyuki Kouda, Kuniyuki Kakushima, Parhat Ahmet, Kazuo Tsutsui, Nobuyuki Sugii,
Takeo Hattori and Hiroshi Iwai, ‘Gate leakage current suppression of CeO2/La2O3 with
different thickness ratio’, 56th Japan Society of Applied Physics (JSAP), Ibaragi, Japan,
April, 2009
198
5. Miyuki Kouda, Kuniyuki Kakushima, Parhat Ahmet, Kazuo Tsutsui, Nobuyuki Sugii,
Takeo Hattori and Hiroshi Iwai, ‘Charged defects reduction in gate insulator witt
multivalent materials’, G-COE PICE International Symposium on Silicon Nano Devices
in 2030: Prospects by World's Leading Scientists
6. Miyuki Kouda, Kuniyuki Kakushima, Parhat Ahmet, Kazuo Tsutsui, Akira
Nishiyama, Nobuyuki Sugii, Kenji Natori, Takeo Hattori and Hiroshi Iwai,
‘Improvement of electrical properties of MOSFET by rare-earth oxide capping’, 57th
Japan Society of Applied Physics (JSAP), Tokai University, Japan, April, 2010
7. Miyuki Kouda, Kenji Ozawa, Kuniyuki Kakushima, Parhat Ahmet, Hiroshi Iwai,
Yuji Urabe, and Tetsuji Yasuda, ‘Preparation and characterization of CVD CeOx films’,
71th Japan Society of Applied Physics (JSAP) Autumn Meeting, Nagasaki, Japan,
August, 2010
8. Miyuki Kouda, Takuya Suzuki, Kuniyuki Kakushima, Parhat Ahmet, Hiroshi Iwai,
and Tetsuji Yasuda, ‘Stack structures of ALD-La2O3 and CVD-CeO2 : fabrication and
mobility improvement effects’, 17th Gate stack seminar, Shizuoka, Japan, January,
2012.
9. Miyuki Kouda, Maimat Mamatrishat, Takamasa Kawanago, Kuniyuki Kakushima,
Parhat Ahmet, Hiroshi Nohira, Yoshinori Kataoka, Akira Nishiyama, Kazuo Tsutsui,
Nobuyuki Sugii, Takeo Hattori and Hiroshi Iwai, ‘Valence number of Ce and Ce silicate
at cerium oxide/Si(100) interface’, 59th Japan Society of Applied Physics (JSAP),
Waseda University, Japan, March, 2012
199
Acknowledgments
I would like to express my deepest gratitude to Prof. Hiroshi Iwai of Tokyo
Institute of Technology for his excellent guidance throughout my research on doctoral
dissertation.
I am also grateful to Prof. Takeo Hattori, Prof. Kenji Natori, Prof. Nobuyuki Sugii,
Prof. Akira Nishiyama, Prof. Yoshinori Kataoka, Prof. Kazuo Tsutsui, Prof. Kuniyuki
Kakushima and Prof. Parhat Ahmet for useful discussion and encouragement.
I would like to thank Prof. Masahiro Watanabe, and Prof. Shun-ichiro Ohmi of
Tokyo Institute of Technology, Professors Ming Liu (Institute of microelectronics
Chinese academy of sciences), Hei wong (City University of Hong Kong), Zhenan Tang
(Dalian University of Technology), Zhenchao Dong (University of science and
technology of China), Junyong Kang (Xiamen University), Weijie Song (Ningbo
Institute of material technology and engineering), Chandan Sarkar (Jadavpur university),
Wang Yang (Lanzhou Jiaotong university), and Baishan Shadeke (Xinjiang University)
for their reviewing manuscript and giving valuable comments on the manuscripts at the
final examination of thesis dissertation.
I would like to thank Dr. Tetsuji Yasuda of National Institute of Advanced
Industrial Science and Technology (AIST) for kind guidance for the research in ALD
and CVD of RE-oxides.
I would like to thank Prof. Keisaku Yamada of Waseda University, Prof. Kenji
Shiraishi of University of Tsukuba, Dr. Toyohiro Chikyow, Dr. Naoto Umezawa of
National Institute for Materals Scinece (NIMS) for their guidance and encouragement
for the charged defect analysis of CeO2 capping over La2O3 using first-principle
200
calculations.
I would like to thank Prof. Hiroshi Nohira of Tokyo City University for his
valuable advice on XPS.
I am grateful to Mr. Daryoush Hassan Zadeh of Iwai Laboratory for his kind
support at English revision of this thesis.
Finally, I would like to express my profound gratitude to my father Shigeru, my
mother Megumi, my brother Kyouhei and Keisuke for all their invaluable support and
encouragement throughout this study.
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