2011 Master thesis

A study on resistive-switching

behavior of CeO2 metal-insulator-metal

structures for resistance random access

memory devices

Supervisor

Professor Nobuyuki Sugii

Department of Electronics and Applied physics

Interdisciplinary Graduate School of Science and Engineering

Tokyo Institute of Technology

09M36483

Koki Mukai

Contents Chapter1. Introduction

1.1 Background of this study 1.2 Resistive random access memory 1.3 Classification of resistive switching behavior

1.3.1 unipolar 1.3.2 bipolar

1.4 Classification of resistive switching mechanisms 1.4.1 Bulk (nanoionics) 1.4.1.1 Valency change switching processes 1.4.2 Interface-type path

1.4.2.1 Electrochemical Metallization Processes 1.5 Purpose of this work

Chapter 2. Fabrication and Characterization

Method

2.1 Fabrication Process 2.1.1 Wet Cleaning 2.1.2 Oxidation Furnace 2.1.3 RF Sputtering 2.1.4 Molecular Beam Epitaxy (MBE) 2.1.5 Reactive Ion Etching (RIE) 2.1.6 Rapid Thermal Annealing (RTA)

2.2 Electrical Characterizations 2.2.1 Jg-V measurement

2.3 References

Chapter 3. Evaluation of performance of

W/CeO2/TiN under sweeping voltage

3.1 Basic resistive switching behavior

3.1.1 I-V curve 3.1.2 Endurance 3.1.3 Retention properties 3.1.4 Temperature dependency

3.2 Influence of electrode area and compliance current 3.2.1 Influence of electrode area 3.2.2 Influence of compliance current

3.3 Proposed model for resistive switching 3.4 Performance improvement by new operation method

3.4.1 Operation oriented method to improve its function 3.5 References

Chapter 4. Pulse induced resistive switching

4.1 Pulse induce resistive switching

Chapter 5. Conclusion

7.1 Conclusion 7.2 References

Acknowledgement

Chapter1. Introduction

1.1 Background of this study 1.2 Resistive random access memory 1.3 Classification of resistive switching behavior

1.3.1 unipolar 1.3.2 bipolar

1.4 Classification of resistive switching mechanisms 1.4.1 Bulk (nanoionics) 1.4.1.1 Valency change switching processes 1.4.2 Interface-type path

1.4.2.1 Electrochemical Metallization Processes 1.5 Purpose of this work

1.1 Background of this study

Modern semiconductor nonvolatile memories, such as Flash memory, have been successfully scaled down to achieve large-capacity memories through improvements in photolithography technology. However, conventional memory scaling is expected to come up against technical and physical limits in the near future. In order to overcome this problem, ‘equivalent scaling’, i.e. functionalization by introducing new materials and/or three dimensional structures, has been proposed as a new alternative to the conventional scaling technology. Candidates for equivalent scaling based on new materials, including ferroelectric random access memory（FeRAM）, in which the polarization of a ferroelectric material is reversed, magnetroresistive RAM(MRAM), which uses magnetic tunnel junctions, and phase-change RAM(PRAM), which uses the change in resistance between crystalline and amorphous states of a chalcogenide compound, have attracted a great deal of attention for use as next-generation nonvolatile memories.

1.2 Resistive random access memory Resistance random access memory (ReRAM) is based on new materials, such as metal

oxides and organic compounds, which show a resistive switching phenomenon. The ReRAM memory cell has a capacitor-like structure composed of insulating or semiconducting materials sandwiched between two metal electrodes. Because of its simple structure, highly scalable cross-point and multilevel stacking memory structures have been proposed. In the resistive switching phenomenon, a large change in resistance occurs on applying pulsed voltages, and the resistance of the cell can be set to a desired valus by applying the appropriate voltage pulse.

1.3 Classification of resistive switching behavior The resistive switching phenomenon has been observed in a wide variety of transition

metal oxides. However, the observed switching behavior seems to differ depending on the material. On the basis of I–V characteristics, the switching behaviors can be classified into two types: unipolar (nonpolar) and bipolar, for which typical I–V curves

are shown in Figs. 1a and 1b, respectively.

Fig. 1.1 I-V curves for (a) unipolar (nonpolar) switching in a Pt/NiO/Pt cell and (b) bipolar switching in a Ti/La2 CuO4 /La1.65 Sr0.35 CuO4 cell

1.3.1 unipolar In unipolar resistive switching, the switching direction depends on the amplitude of the applied voltage but not on the polarity. An as-prepared memory cell is in a highly resistive state and is put into a low-resistance state (LRS) by applying a high voltage stress. This is called the ‘forming process’. After the forming process, the cell in a LRS is switched to a high-resistance state (HRS) by applying a threshold voltage (‘reset process’). Switching from a HRS to a LRS (‘set process’) is achieved by applying a threshold voltage that is larger than the reset voltage. In the set process, the current is limited by the current compliance of the control system or, more practically, by adding a series resistor. This type of switching behavior has been observed in many highly insulating oxides, such as binary metal oxides.

1.3.2 bipolar Bipolar resistive switching shows directional resistive switching depending on the

polarity of the applied voltage (Fig. 1.2b). This type of resistive switching behavior occurs with many semiconducting oxides, such as complex perovskite oxides.

1.4 Classification of resistive switching mechanisms In addition to classification in terms of switching behavior, the type of conducting path

is also used to categorize the resistive switching.

1.4.1 Bulk (nanoionics) One class shows a filamentary conducting path, in which the resistive switching

originates from the formation and rupture of conductive filaments in an insulating matrix (Fig. 1.2a).

Fig. 1.2 Proposed models for resistive switching can be classified according to either (a) a filamentary conducting path, or (b) an interface-type conducting path. This can be associated with both unipolar and bipolar switching behavior. Fig. 1.3

shows a possible driving mechanism for filament-type resistive switching that shows unipolar switching behavior. In the forming process (1), filamentary conducting paths form as a soft breakdown in the dielectric material. Rupture of the filaments takes place during the reset (2) process, and filament formation during the set process (3). Thermal redox and/or anodization near the interface between the metal electrode and the oxide is widely considered to be the mechanism behind the formation and rupture of the filaments.

(a) (b)

Fig. 1.3 (a) Unipolar resistive switching behavior. (b) Schematics of the initial state

(as-prepared sample) and (1) forming, (2) reset, and (3) set processes. In contrast, in bipolar-type switching, electrochemical migration of oxygen ions is

regarded as the driving mechanism. Clear visualization of the conducting filaments in insulating oxides has not been achieved. Recent studies involving highresolution transmission electron microscopy and electron energy loss spectroscopy of NiO memory cells suggest that the filamentary conducting paths form in the grain boundaries.

1.4.1.1 Valency change switching processes In many transition metal oxides, oxygen ions defects, typically oxygen vacancies, are

much more mobile than cations. If the cathode blocks ion exchange reactions during an electroforming process, an oxygen deficient region starts to build and to expand towards the anode. Transition metal cations accommodate this deficiency by trapping electrons emitted from the cathode. In the case of TiO2 or titanates, for example, this reduction reaction

)4(4 nTiTien

is equivalent to filling the Ti 3d band. The reduced valency states of the transition metal cations which are generated by this electrochemical process typically turn the oxide into a metallically conducting phase, such as, e. g., TiO2-n/2 for approx. n > 1.5. This “virtual cathode” moves towards the anode and will finally form a conductive path. At the anode, the oxidation reaction may lead to the evolution of oxygen gas. As an alternative, material of or nearby the anode may be oxidized. Once the electroforming is completed, the bipolar switching obviously takes place through local redox reactions between the virtual cathode and the anode, i. e. by forming or breaking the conductive contact.

1.4.2 Interface-type path The other type of conducting path is an interface-type path, in which the resistive

switching takes place at the interface between the metal electrode and the oxide (Fig. 1.2b). Using multilead resistance measurements on perovskite oxide cells, the contact resistance between the metal electrode and the perovskite oxide changes upon the application of an electric field has been shown recently. This switching mechanism is usually related to the bipolar-type resistive switching behavior observed in semiconducting perovskite oxides. A number of models have been proposed for the driving mechanism in resistive switching involving an interface-type conducting path, such as electrochemical migration of oxygen vacancies, trapping of charge carriers (hole or electron), and a Mott transition induced by carriers doped at the interface.

1.4.2.1 Electrochemical Metallization Processes One class within this category relies on an electrochemically active electrode metal

such as Ag, the drift of the highly mobile Ag+ cations in the ion conducting layer, their discharge at the (inert) counterelectrode leading to a growth of Ag dendrites which form a highly conductive filament in the ON state of the cell. Upon reversal of polarity of the applied voltage, an electrochemical dissolution of the conductive bridges takes place, resetting the system into the OFF state (Fig. 1.4). The redox reactions for Ag2S as an Ag ion conductor read as:

AgeSAgAgOxidation

duction

Re

'2 )(

The asymmetry of the OFF switching has been a matter of some debate, because it appeared to be unclear why the “opening” of the Ag bridge should occur at a different voltage polarity than the “closing”. Using a model system with an aqueous electrolyte we have recently been able to demonstrate that the asymmetry arises from the morphology.

Figure 1.4. Sketch of a resistive switching effect based on the electrochemical metallization process.

1.5 Purpose of this work This thesis focuses on the feasibility of cerium oxides for the ReRAM application,

because of their special character that the valence number of cerium oxide can change between +3 and +4. W/CeO2/TiN structure has been fabricated by sputter(W, TiN) and e-beam(CeO2) deposition. The device has shown resistive switching, which has an on/off window about 10 within 20 times of read-write operation. Currently, in this system with CeO2, an on/off ratio and endurance are still insufficient. In order to improve these properties, annealing conditions have been investigated. It is presumed that oxygen vacancies play an important role in the resistance switching of CeO2 film.

1.6 Reference [1] Akihito Sawa, “Resistive switching in transition metal oxides”, 2008 [2] Rainer Waser, “Electrochemical and Thermochemical Memories”, IEEE, 2008 [3] Chih-Yang Lin, “Reproducible resistive switching behabior in sputtered CeO2 polycrystalline films”, 2008

Chapter 2. Fabrication and Characterization

Method

2.1 Fabrication Procedure for RRAM

2.2 Fabrication Process 2.2.1 Wet Cleaning 2.2.2 Oxidation Furnace 2.2.3 RF Sputtering 2.2.4 Molecular Beam Epitaxy (MBE) 2.2.5 Reactive Ion Etching (RIE) 2.2.6 Rapid Thermal Annealing (RTA)

2.3 Electrical Characterizations

2.4 References

2.1 Fabrication Procedure for RRAM

Figure 2.1 summarizes device fabrication flow of La2O3, CeOX, CeOX/La2O3 MOS-capacitors. The MOS capacitors were fabricated on n-type (100)-oriented 2-5 Ω-cm Si substrate. To determine the capacitor area and to avoid unexpected peripheral effect, 300 nm-thick thermal oxide was formed and patterned photolithography. The wafers were then cleaned by a mixture of H2SO4/H2O2 at 85℃ for 5 min to remove all the resist-related organic contamination, followed by diluted HF cleaning. Thin films of high-k were deposited using e-beam evaporation from materials pressed target in an ultra-high vacuum chamber of 10-7 Pa. The tungsten (W) gate electrode of 50 nm was coated by RF sputtering with power of 150 W. Electrode was finally lithographically patterned to form MOS capacitors. Post-deposition annealing (PDA) in Forming gas (3 %-H2+97 %-N2) was carried out. Finally, aluminum (Al) was thermally evaporated on backside of the wafers for bottom electrode.

Figure 2.1 Fabrication process flow of ReRAM The detailed explanation of each process and experimental equipment will be described in next section.

Highly doped Si substrate

SPM, HF last treatment

TiN metal gate electrode deposition by RFsputtering

Tungsten (W) metal gate electrode deposition by RFsputtering

CeO2 deposition by EB evaporation

PMA (Post Metallization Annealing) 400℃, 30s, N2

Bottom electrode Al deposition

J-V measurement

Thermal oxidation

Electrode pattern[10nm×10nm, 20nm×20nm, 50nm×50nm]

Highly doped Si substrate

SPM, HF last treatment

TiN metal gate electrode deposition by RFsputtering

Tungsten (W) metal gate electrode deposition by RFsputtering

CeO2 deposition by EB evaporation

PMA (Post Metallization Annealing) 400℃, 30s, N2

Bottom electrode Al deposition

J-V measurement

Thermal oxidation

Electrode pattern[10nm×10nm, 20nm×20nm, 50nm×50nm]

2.2.1 Si Substrate Cleaning Process At first, high quality thin films require ultra clean Si surface without particle

contamination, metal contamination, organic contamination, ionic contamination, water absorption, native oxide and atomic scale roughness.

One of the most important chemicals used in Si substrate cleaning is DI (de-ionized) water. DI water is highly purified and filtered to remove all traces of ionic, particulate, and bacterial contamination. The theoretical resistivity of pure water is 18.25 MΩcm at 25℃. Ultra-pure water (UPW) system used in this study provided UPW of more than 18.2 MΩcm at resistivity, fewer than 1 colony of bacteria per milliliter and fewer than 1 particle per milliliter. In this study, the Si substrate was cleaned on a basis of RCA cleaning process, which was proposed by W. Kern et al. But some steps were reduced. The first step, which use a solution of sulfuric acid (H2SO4) / hydrogen peroxide (H2O2) (H2SO4: H2O2=4:1), was performed to remove any organic material and metallic impurities. After that, the native or chemical oxide was removed by diluted hydrofluoric acid (HF:H2O=1:99). Then the cleaned wafer was dipped in DI water. Finally, the cleaned Si substrate was loaded to chamber to deposit as soon as it was dried by air gun.

2.2.2 Oxidation Furnace Thermal oxidation is accomplished by using an oxidation furnace (or diffusion

furnace, since oxidation is basically a diffusion process involving oxidant species), which provides the heat needed to elevate the oxidizing ambient temperature. A furnace typically consists of: 1) a cabinet; 2) a heating system; 3) a temperature measurement and control system; 4) fused quartz process tubes where the wafers undergo oxidation; 5) a system which transfers process gases into and out of the process tubes; and 6) a loading station used for loading (or unloading) wafers into (or from) the process tubes.

The heating system usually consists of several heating coils that control the temperature of the furnace tubes. The wafers are placed in quartz glassware known as boats, which are supported by fused silica paddles inside the process tube. A boat can support many wafers. The oxidizing agent (oxygen or steam) then enters the process

tube through its source end, subsequently diffusing to the wafers surface where the oxidation occurs. In this study, Figure 2.1 shows a photo of Oxidation Furnace.

Depending on oxidant species used (O2 or H2O), the thermal oxidation of SiO2 may either be in the form of dry oxidation (wherein the oxidant is O2) or wet oxidation (wherein the oxidant is H2O). The reactions for dry and wet oxidation are governed by the following equations: 1) for dry oxidation: Si (solid) + O2 (vapor) → SiO2 (solid); and 2) for wet oxidation: Si (solid) + 2H2O (vapor) → SiO2 (solid) + 2H2 (vapor). Figure 2.2 shows the thermal oxidation rate using bulk P-Si substrate and SOI substrate which has 51 nm thick SOI, 137.8 nm thick BOX layer. The figure indicate 16 that SiO2 thickness increases and residual SOI thickness decreases as increasing oxidation time.

2.2.4 RF Sputtering

In this experiment, gate metals W and TaSi2 were deposited using RF sputtering. The

base pressure of sputtering chamber was maintained to be 10-7 Pa by TRP and RP

(shown in Fig.2.7). In sputtering, Ar was flowed into the chamber and the pressure of

which was set to be 10-4 Pa, the AC current power was 150W.

Sputtering Chamber10 x10-7 Pa

To GrowthChamber

TMPRP

Substrate Folder

WTaSi2

Ar

Figure 2.7 Schematic model of RF Sputtering

2.2.3 Molecular Beam Epitaxy (MBE)

As discussed and reported in various literatures, there are many ways to deposit high-k

dielectric films on Si substrate. Various deposition methods have been proposed. These

include MOCVD, LPCVD, ALD, PLD and e-beam evaporation. In this study, e-beam

evaporation method was adopted. High-k materials were deposited in ultra high vacuum

chamber as shown in figure 2.6. There are four compartments to allocate

same/difference solid sources at the bottom of the chamber. HfO2 and La2O3 were

placed there and subsequently heated by the e-beam which was located near the each

high-k source. The electron beam was controlled by a magnetic sweep controller, and

the power of the beam is set to be 5 kV. The base pressure inside growth chamber is

maintained at 10-8 Pa by TMP, when high-k was deposited the pressure inside the

chamber increased to 10-7 Pa. Then, since the chamber is maintained at the ultra high

vacuum state, the La2O3 molecule begins to evaporate when the temperature is reported

as 3620 oC. In deposition, the physical thickness of each high-k film was measured by

crystal oscillator and the sample folder was rotated. Deposition rate was set to be 0.3

nm/s, the rate was important for the film quality. Too fast deposition rate made the

quality worse than slow deposition rate.

Growth Chamber10 x10-7 Pa

To LL Chamber

Substrate Folder

E-beam

To SputteringChamber

TMP RP

Thickness monitor

HfO2 La2O3

Substrate Heater

Figure 2.6 Schematic model of molecular beam epitaxy (MBE)

2.2.5 Reactive Ion Etching (RIE)

Reactive Ion Etching (RIE) which uses one of chemical reactive plasma to remove

materials deposited on wafers was adopted to etch gate electrode in this study. There are

two electrodes in vacuum chamber (shown in fig. 2.8). One is usually connected to

ground and gas is put into the chamber and exits to the pump, in this study SF6 and O2

are used to remove gate W, TaSi2 and resist each. And plasma is generated and ion direct

for substrate and remove gate electrode and resist chemically.

2.2.6 Rapid Thermal Annealing (RTA)

Thermal annealing processes are often used in modern semiconductor fabrication for

defects recovery, lattice recovery and impurity electrical activation of doped or ion

implanted wafers. In this study, MOS capacitors and MOSFETs were post metallization

annealed after gate electrode deposition. To confirm the EOT growth of MOSFET in

gate-last-process after PMA, annealing temperature was mainly set to 500 oC.

Chapter 3. Evaluation of performance of

W/CeO2/TiN under sweeping voltage

3.1 Basic resistive switching behavior

3.1.1 I-V curve 3.1.2 Endurance 3.1.3 Retention properties 3.1.4 Temperature dependency

3.2 Influence of electrode area and compliance current 3.2.1 Influence of electrode area 3.2.2 Influence of compliance current

3.3 Proposed model for resistive switching

3.4 Performance improvement by new operation method 3.4.1 Operation oriented method to improve its function

3.5 References

Chapter 4. Pulse induced resistive switching

4.1 Pulse induce resistive switching

Chapter 5. Conclusion

7.1 Conclusion 7.2 References

Acknowledgement

3.1 Basic resistive switching behavior 3.1.1 I-V curve Fig. 3.1 shows the typical I–V curves of the device with initial positive bias. For the

initial sweep and the SET process, the current is clamped at a given value of 5mA to avoid permanent device damages. A forming process is necessary to activate the W/CeO2/TiN device from as-deposited film state to observe any resistive switching phenomenon. After a forming process by applying about 9 V with a 5 mA current compliance (not shown here), typical current–voltage (I–V) characteristics in semi-logarithmic plot of the W/CeO2/TiN device performed by applying voltage sweeps are shown in Fig. 3.1, and the resistance ratio between OFF-state and ON-state can reach five orders of magnitude

Figure 3.1 Typical I-V curves of the W/CeO2/TiN device

3.1.2 The switching endurance of W/CeO2(20nm)/TiN

0 4 8 12 16102

103

104

HRS

LRS

Read@1.0V

Switching Cycle(回)

Res

ista

nce(

Ω)

0 4 8 12 16102

103

104

HRS

LRS

Read@1.0V

Switching Cycle(回)

Res

ista

nce(

Ω)

3.1.3 Retention properties 3.1.4 Temperature dependency

stan

ce(Ω

）

102

103

104

105

LRS

HRS

stan

ce(Ω

）

102

103

104

105

LRS

HRS

3.2 Influence of electrode area and compliance current

3.2.1 Influence of electrode area

10 1000

3.0

4.0

2.0

5.0

6.0

1.0Res

ista

nce(

103 Ω

) ■HRS▲LRS

10 1000

3.0

4.0

2.0

5.0

6.0

1.0Res

ista

nce(

103 Ω

) ■HRS▲LRS

3.2.2 Influence of compliance current

3 4 5 6 7 8 9 10

3

4

5

6

7

8

HRS

LRS

Compliance current(mA)

Window

(HR

S/LR

S)

8

2

6

4

Res

ista

nce(×

103 Ω

)

3 4 5 6 7 8 9 10

3

4

5

6

7

8

HRS

LRS

Compliance current(mA)

Window

(HR

S/LR

S)

8

2

6

4

Res

ista

nce(×

103 Ω

)

3.3 Proposed model for resistive switching

2CeO2Ce2O3 + ½ O2 +Vo··

Oxygen ions at grain boundary

W electrode

CeO2

Initial state

on state （LRS） off state (HRS)

Forming process

+VFormation of oxygen vacancies:

-2e-

E

oxygen vacancies drift under electric field

+V -V elimination of oxygen vacancies

Ce2O3 + ½ O2 +Vo··

2CeO2+2e-

2CeO2Ce2O3 + ½ O2 +Vo··

Oxygen ions at grain boundary

W electrode

CeO2

Initial state

on state （LRS） off state (HRS)

Forming process

+VFormation of oxygen vacancies:

-2e-

E

oxygen vacancies drift under electric field

+V -V elimination of oxygen vacancies

Ce2O3 + ½ O2 +Vo··

2CeO2+2e-

3.4 Performance improvement by new operation method 3.4.1 Operation oriented method to improve its function

4

5

6

7

8

HRS

LRS

Window

(HR

S/LR

S)

8

2

6

4

Res

ista

nce(×

103 Ω

)

4

5

6

7

8

HRS

LRS

Window

(HR

S/LR

S)

8

2

6

4

Res

ista

nce(×

103 Ω

)