A Study On Different 32 And 16-bit Processors For Low-Earth Orbit Space Applications
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2000-10-11 RYP-KS
A Study On Different 32 And 16-bit Processors
For Low-Earth Orbit Space Applications
Krister Sundström
Master’s Project
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Background Data
Low-Earth Orbit: 400 - 600 km altitude
Short Lifetime: ~ 3 years
Small-Satellite Constellation: ~ 60 kg/satellite
>100 satellites
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Background Information
On-Board Computer Systems (OBC)
Real-Time Systems (RTS)
Single Event Effects (SEE)
Parasitic Silicon Controlled Rectifier
Interrupt Phillosophy
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Data Handling System
Central Part of The Satellite
• Mission Software
• Subsystem Master
• Shared Processing Power
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Availability
Error Tolerance And Recovery
•Error Detection And Correction (EDAC)
•Watchdog
Study Topics
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Peripheral Support
Serial & parallel ports / Bus controllers
Memory types
Multitask Support
Real-time system
Context switching
Processor Architectures
Study Topics
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What Is A Real-Time System? Correct functionality, at the right time
Soft RTS Instrument Data Collection Missed Soft Deadline
System still functional Some degradations
Hard RTS Attitude & Orbit Control System (AOCS) Missed Hard Deadline
Catastrophe may follow
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Single Event Effects (cont.)
A Simple Memory Cell Model
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Single Event Effects (cont.)
Spread Out Data Bits Less risk for multiple bit error
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Parasitic SCR
Can Cause Permanent Damage
•Single Event Latch-up
•Single Event Burn-out (SEB)
Current Limiter
Silicon On Insulator (SOI)
SCR - Silicon Controlled Rectifier
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EDAC (cont.)
Checkbit
Generator
=
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Interrupts
Masked Threshold
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Different Processors
RH Thor (32) Saab Ericsson
ERC32 (32) Temics
Leon (32) ESA
HS-RTX2010 RH (16) Harris
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RH Thor
32-bit, 4-Stage Pipelined RISC Processor
2 Giby Address Space
1 Giby = 230 bytes
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RH Thor (cont.)
Hardware Support For Task Switching
Exception Resume
SOI – Silicon On Insulator
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ERC32 Fully SPARC v7 Compatible
3 Main Blocks; IU, MC, FPU
IU
FPUMC
DMA
I/O
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ERC32
32 Miby Address Space
Multitask Support – Windows Register File
1 Miby = 220 bytes
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Leon
Open-sourced – Free VHDL Code
Small Design – 30 kGates (without FPU)
100% ERC32 Compatible
Fully SPARC v8 Compatible
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Leon (cont.)
Many On-Chip Peripheral Interfaces
1 Giby Address Space
Multitask Support
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HS-RTX2010 RH
Small, Well Used 16-bit Processor
High Radiation Tolerant (>300 kRAD)
1 Miby Address Space
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Why Leon?
Open-sourced architecture Free VHDL-code Optimisation On-chip add-on possibilities
Small design Only 27’000 gates + RAM
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Why Leon? (cont.)
Re-Configurable
Fully SPARC v8 Compatible
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Disadvantages With Leon?
No Support For Integer Division DIVU – unsigned division DIVS – signed division
New Design
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- The End -
www.acc.umu.se/~moschler/x2000
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OBC Tasks
•Processing of Uplink Telecommand (TC) Data Stream•Assemble, decode, and distribute incoming telecommands
•Generate Downlink Telemetry (TM) Data StreamCollect telemetry dataGenerate TM frames
•Provide General I/O for Command Distribution and Telemetry Data Collection
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OBC Tasks (cont.)
•Provide Processing Power for Various Tasks
Battery charging control
Calculations for non-intelligent payload
Antenna pointing (attitude controlling)
Payload and thermal control
•Provide With Timing Functionalities
On-Board Timer (OBT) counter
Time pulse synchronisation, by using GPS receivers
Queuing of internal spacecraft commands
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OBC Tasks (cont.)
•Provide With Autonomy Functionalities
System supervision and context switching (OS aspects)
Automatic system reconfiguration in case of system error(s)
Automatic spacecraft recovery (Sun & Earth)
•Bus Controlling and Peripheral Communications
Bus master
Instrument/ Payload interfacing
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Single Event Effects
Incoming Particles Single Event Upset (SEU) Single Event Latch-up (SEL) Other Single Event Phenomena (SEP)
Technology Dependent Silicon Wafers vs Silicon On Isolator (SOI)
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What Is A Real-Time System?
“The correctness of a real-time system depends not only on the logical result of the computation but also on the time at which the results are produced.” – [RTSAPL]
Correct functionality, at the right time
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EDAC
Error Detection And Correction
Scrubbing
Hamming Coded(min) = s + t + 1 (I)
d(min) = 2 t + 1 (II)
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A Typical Data Handling System
Data Flow
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ToDo
Förklara: SCR P/L egen intelligens som klarar sig självt, fristående från OBC. Bara busstrafik mellan Realtidssystem och deras hårda och mjuka tidskrav Att DHU och OBC är tätt sammanfogade i småsatelliter och att de här tituleras OBC Hur EDAC fungerar Förslag på EEPROM uppsättnigar och resten av ett OBDH. Kolla in WALT-projektet Olika interruptfilosofier, typ Masked, Threshold, etc Atomic Actions? Pipeline In 1950, a smart guy named Richard W. Hamming figured out a method of
implementing ECC memory using the theoretical minimum number of redundant bits (this is called the Hamming Code).
FPGA En bild på olika bitorganiseringar I minnen
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