A Strategy for Routing the MPC8536E in a Six-Layer PCB · 2016. 11. 23. · A Strategy for Routing...
Transcript of A Strategy for Routing the MPC8536E in a Six-Layer PCB · 2016. 11. 23. · A Strategy for Routing...
Freescale SemiconductorApplication Note
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Freescale Confidential Proprietary
This application note is a design guide to assist the customer in creating a low-layer, low-cost PCB design when using the MPC8536E device. Key items of discussion include assumed PCB stackup, power delivery to the device, and proper signal referencing. Additionally, layout plots for the device fan-out are also included.
NOTEThe schematic and Gerber data shown within this application note is intended merely to demonstrate the fan-out and power delivery strategy necessary to achieve a six-layer PCB. The schematic and Gerber data does not include all the decoupling, nor do they show all the necessary pull-ups and AC caps required outside the BGA fan-out area. This level of detail is captured as part of the MPC8536E development system.
AN3444Rev. 0, 10/2007
Contents1 Ballmap Organization . . . . . . . . . . . . . . . . . . . . .22 Interface Support in Six Layers . . . . . . . . . . . . . .23 Board Stackup Considerations . . . . . . . . . . . . . .4
3.1 Stackup Proposal . . . . . . . . . . . . . . . . . . . .44 Signal Breakout . . . . . . . . . . . . . . . . . . . . . . . . . .6
4.1 Inside the BGA area. . . . . . . . . . . . . . . . . .64.2 Outside the BGA Area . . . . . . . . . . . . . . . .84.3 Trace Spacing Outside the BGA Area . . . .8
5 Via Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Power and Ground Strategy. . . . . . . . . . . . . . . .10
6.1 Power Planes . . . . . . . . . . . . . . . . . . . . . .106.2 Current Delivery . . . . . . . . . . . . . . . . . . . .146.3 PLL Filters . . . . . . . . . . . . . . . . . . . . . . . .146.4 Sharing Power Supplies . . . . . . . . . . . . . .156.5 Bypass Capacitor Placement . . . . . . . . . .166.6 Bulk Capacitors . . . . . . . . . . . . . . . . . . . .20
7 Signal Layer Gerber Plot . . . . . . . . . . . . . . . . . .218 Fan-Out Schematics . . . . . . . . . . . . . . . . . . . . .269 Current Delivery in the BGA Field . . . . . . . . . . .40
9.1 Via Current Capacity . . . . . . . . . . . . . . . .419.2 Alternate Plane Current Capacity . . . . . .42
10 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4511 Revision History. . . . . . . . . . . . . . . . . . . . . . . . .46
A Strategy for Routing the MPC8536E in a Six-Layer PCBby Michael George
DSD ApplicationsFreescale Semiconductor, Inc.Austin, Texas
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
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Ballmap Organization
1 Ballmap OrganizationThe MPC8536E is a 783-pin, 28 × 28 BGA array. The bus organization of the device is shown in Figure 1.
Figure 1. MPC8536E Bus Groupings (Viewed from the top of the device)
2 Interface Support in Six LayersThough the MPC8536E device can be fully broken out in six layers, there are a handful of signals that are not necessarily optimal from a signal integrity perspective, mainly due to splits in the reference plane. Such cases are very limited and are, therefore manageable. Table 1 enumerates the MPC8536E interfaces and whether there is proper signal referencing in the six-layer PCB fan-out example.
Table 1. Interface Support in Six Layers
Interface Configuration Reference Plane Comment
DDR2 Full 64-bit + ECC DDR Data—GND
DDR ADDR—1.8 V
DDR CLKs—1.8 V
Fully supported.
ETSEC RGMII RGMII I/O—2.5 V
GTX_CLK125—GND
Both Ethernet ports can be fully routed in RGMII mode with proper signal referencing to the TVDD/LVDD power split, set at 2.5 V.
Signals needed for GMII can be broken out, but have breaks in their reference plane.
TSEC
USB
PCI and3.3 V I/O
Srds1
LocalBus
DDR
Srds2 CoreandPlat
A1 A28
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Interface Support in Six Layers
POR Config All user defined POR pins are accessible.
GND and PWR Fully supported. Some POR pins cross splits but since they are static, there is no concern.
PCI Full 32-bit PCI with 3 GNTs and 3 REQs
GND PCI_REQ[4:5] and PCI_GNT[4:5] not broken out on same layer as rest of the PCI bus.
LB All signals are accessible GND and PWR LB_LAD[23:31] cross split boundaries. These signals are not edge sensitive, therefore imperfections in their transitions can be managed. Use of stitching caps could be used.
SERDES1 All eight lanes accessible GND Fully supported
SERDES2 Both lanes accessible GND Fully supported
IRQ All IRQs (0–11) and IRQ_OUT useable
GND and PWR Fully supported
SPI All signals are accessible GND Fully supported
SDHC All signals are accessible GND Fully supported
JTAG/COP All signals are accessible GND and PWR Fully supported
DUARTS Both UART ports are fully accessible
GND and PWR Fully supported
USB All three ports fully accessible GND Fully supported
Power pins and AVDD filters
All unique powers accessible N/A Fully supported
I2C Both I2C port accessible GND and PWR Fully supported
Clocking SYSCLK, RTC, and DDRCLK accessible
GND and PWR Fully supported
1588 All signals are accessible GND and PWR Signals cross split boundaries. Most customers do not use. Use of stitching caps could be used.
GPIO and miscellaneous
signals
All signals are accessible GND and PWR Fully supported
DEBUG TRIG_OUT PWR Signal crosses split boundaries. Noncritical debug signal. Use of stitching cap could be used.
Table 1. Interface Support in Six Layers (continued)
Interface Configuration Reference Plane Comment
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Board Stackup Considerations
3 Board Stackup ConsiderationsThis section presents the considerations associated with the PCB and its stackup. Table 2 list the target impedances needed in a six-layer design.
Additional considerations for the stackup include
• Must utilize high volume, low cost PCB technology
• Routing density
• Aspect ratio less than 10:1
• Drill size set at 10 mil
• Common core construction
• Proper signal referencing for all critical signals
3.1 Stackup ProposalFigure 2 shows a viable stackup for achieving the target impedances noted in Table 2. The target card thickness used is 62 mils (±7 mils). All signal routing is done on the inner two signal layers, or on the top and bottom signal layers. No signal routing is performed on the power and ground layers.
Table 2. Target Impedance for a Typical MPC8536E Design
Interface Connection Target Impedance
DDR2 8536E-to-DDR2 memory Single ended impedance = 55–60 ΩDifferential impedance = 100 Ω ± 10%
SERDES1 (PCIe) 8536E-to-PCIe connector or device MicroStrip
Single ended impedance = 60 ± 15%
Differential impedance = 100 Ω ± 20%
Stripline
Single ended impedance = 60 ± 15%
Differential impedance = 100 Ω ± 15%
SERDES2 (SGMII/SATA)
8536E-to-connector or device Differential impedance = 100 Ω ± 15%
All 8536E signals 8536E-to-connector or device Single ended interface = 55–60 Ω
Other system Items:
USB differential USB Phy to connector Differential impedance = 90 Ω ± 15%
Ethernet differential Ethernet Phy to connector Differential impedance = 100 Ω ± 15%
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Board Stackup Considerations
Figure 2. Example Six-Layer PCB Stackup (Provided by Sanmina-SCI; www.sanmina-sci.com)
Table 3. Impedance Information (Provided by Sanmina-SCI; www.sanmina-sci.com)
Layer Type Line Width Center-to-Centertpd
(ps/in.)Impedance
(Ω)
1 Single-endedMicrostrip
5 mil n/a 153 55.15
1 DifferentialMicrostrip
4 mil 8 mil 154 93.28
1 DifferentialMicrostrip
5 mil 12 mil 154 96.54
3 Single-endedStripline
4 mil n/a 179 56.0
3 DifferentialStripline
4 mil 10 mil 181 96.38
4 Single-endedStripline
4 mil n/a 179 56.0
4 DifferentialStripline
4 mil 10 mil 181 96.38
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Signal Breakout
4 Signal Breakout
4.1 Inside the BGA areaThe key strategy used in breaking-out the MPC8536E is centered on the use of inexpensive through-hole vias and the use of two track routing for the inner and bottom layers (see Figure 4). For all mainstream PCB fabrication shops, this approach is considered “production-level” technology and is capable of being produced in high volumes. Additionally, this approach produces a cheaper overall PCB design, avoiding the additional cost associated with blind and buried type approaches.
The key items of the strategy are as follows:
• 1 mm (39.3 mil) ball pitch
• Plastic substrate
• 22 mil attach pad on top layer
• 19 mil via pad
• 28 mil anti-pad
• Single track routing on top layer (between attach pads)
• Two track routing on inner layers and on the bottom layer
— Using 4 mil traces and 4 mil space
Figure 3 and Figure 4 show the track routing strategy used for each of the signal layers.
6 Single-endedMicrostrip
5 mil n/a 153 55.15
6 DifferentialMicrostrip
4 mil 8 mil 154 93.28
6 DifferentialMicrostrip
5 mil 12 mil 154 96.54
Table 3. Impedance Information (Provided by Sanmina-SCI; www.sanmina-sci.com) (continued)
Layer Type Line Width Center-to-Centertpd
(ps/in.)Impedance
(Ω)
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Signal Breakout
Figure 3. Signal Routing (Top and Layer #2)
2 traces per rowWidth >= 4 mil
Signal Layer #2
3 traces per rowWidth = 4 milSpace = 4 mil
Drill = 10 milPad = 19 mil
Attach Pad 22 mil
Row 1
Row 12
Row 7
Signal Layer #1 (top)
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Signal Breakout
Figure 4. Signal Routing (Signal Layer #3 and Bottom)
4.2 Outside the BGA AreaInside the BGA area, two track routing limits the minimum trace width to 4 mils and the minimum spacing to 4 mils. Outside the BGA area, this is not the case. Since wider traces have less dielectric loss, the designer may find it useful to use larger trace widths once outside the via array. Similarly, in the cases of differential pairs, the air gaps can be adjusted as needed in order to hit desired impedance targets.
4.3 Trace Spacing Outside the BGA AreaTo minimize crosstalk opportunities once outside the BGA area, the spacing between differing signal groups must be observed. This spacing, denoted as ‘S,’ is based on the dielectric thickness ‘H’ (shown in Figure 5). For the stackup shown in Figure 2, the dielectric thickness is 4.0. Using a 3:1 spacing rule, the air gap between differing signal groups should be at least 12 mil.
Signal Layer #3
2 traces per rowWidth = 4 mil
Signal Layer #4
2 traces per rowWidth = 4 mil
Row 3
Row 12
Row 7
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Via Usage
Figure 5. Trace Spacing Outside the BGA Area
5 Via UsageFor the six-layer PCB a 10-mil drill is used. A 10-mil drill has favorably cost advantages since smaller drill sizes incur additional cost. During fabrication, the drill tolerance is specified as +0/–3 mil, giving a finished hole size (FHS) of approximately 7–7.5 mil.
Using a 10-mil drill an aspect ratio of ~ 6:1 is realized. This aspect ratio is based on an 0.062-inch board thickness and is well within the high volume, production capabilities of all mainstream PCB vendors. Figure 6 depicts the via model used for the six-layer PCB.
Figure 6. Cross Section of PCB
Reference Plane
Trace 1 Trace 2
H
S
39.3 mil (1 mm) BGA Pitch
19.3 mil
11.3 mil
28 mil Anti-Pad
Standard Via
= Section of power plane flowing between vias
19 mil Pad
7–7.5 mil FHS
= Outer layer signal tracks= Inner layer signal tracks
= Via barrel/via pad copper
= PCB
Legend
10 mil Drill
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Power and Ground Strategy
6 Power and Ground StrategyThe MPC8536E requires several power supplies for each subsystem (DDR, Ethernet, SerDes, and so forth) as well as the interconnect fabric itself (the platform voltage). The total number of supplies a system needs depends on the interfaces, the interface voltages required to connect with external peripherals, and the number of those voltages that are common and shareable.
Consult the MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications for accurate voltage and current requirements. For convenience, Table 4 provides a snapshot of the MPC8536E power requirements at the date of this application note. The table also reflects the unique power splits which where constructed in the six-layer PCB example (refer to the Power Rails column). In short, a total of seven unique power rails are used.
Note that Table 4 lists the power requirements for the MPC8536E only; it does not include requirements for external devices, memory, and so forth. At the very least, additional power is needed to drive connected I/O pins, and the internal logic of the other devices often shared with the MPC8536E supplies.
6.1 Power PlanesThe following pictures (Figure 7 through Figure 10) highlight the power strategy used for the six-layer PCB. The ground reference for the PCB is a solid ground plane at layer 2. Since it is a solid plane with no splits, the ground layer is not shown.
Table 4. MPC8536E Power Requirements 1
1 These figures are subject to change without notice. Consult the latest version of the MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications.
Power Rails SymbolTypical Voltage
Tolerance PMAX
Core power VDD_COREAVDD_CORE
1.1 Vor
1.0 V
±50 mV 7 W
Platform (internal buses)
VDD_PLATAVDD_PLATAVDD_PCIAVDD_DDRAVDD_LBIUAVDD_SRDSAVDD_SRDS2
1.0 V ±50 mV 5 W
SerDes SVDDXVDD
1.0 V ±50 mV 0.71W
DDR2 bus GVDD 1.8 V ±90 mV 2.5 W
Ethernet LVDDTVDD
2.5 V ±125 mV 0.24 W
Local bus BVDD 3.3 V ±125 mV 0.33 W
Misc/PCI OVDD 3.3 V ±125 mV 0.33 W
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Power and Ground Strategy
Figure 7. Power Plane (Layer 5 of 6)
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Power and Ground Strategy
Figure 8. SXVDD Power (Layer 2 of 6)
Figure 9. VDD PLAT (Layer 4 of 6)
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Power and Ground Strategy
Figure 10. OVDD, VDD_PLAT, and Rest of SXVDD (Layer 6 of 6—Bottom)
For sensitive supplies (such as XVDD and SVDD), a key requirement for power sharing is that the planes be relatively isolated. One effective strategy is to route the power planes separately and tie them together at the power source. See Figure 11.
Figure 11. Common Source Split Planes
Another strategy is to use a low-pass filter to eliminate coupled noise, as long as there is sufficient current capacity in the components and connections. In either case, once separated, treat the two as independent power planes and route and bypass them separately.
MPC8536E
1.0 V Power Supply
VDD_PLAT
XVDDSVDD
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Power and Ground Strategy
6.2 Current DeliveryAn important consideration in the six-layer PCB is ensuring all power rails have sufficient copper for proper current delivery. The two highest power rails on the MPC8536E are VDD_CORE and VDD_PLAT. The max power requirement for VDD_CORE is 7 W and the max power requirements for VDD_PLAT is 5 W.
Within a congested BGA array, the current travels down multiple 11-mil trace segments as it travels to the power pins, assuming the via stackup referenced in Figure 6 is used. The current-carrying capacity of these 11-mil traces is highly dependent on the current model chosen, either IPC2221A or the newer research performed by Johannes Adam of Flomerics Ltd. For greater detail on these two approaches see Section 9, “Current Delivery in the BGA Field.”
In short, Table 5 depicts the current capacity differences between the two approaches assuming a maximum temperature rise of 20°C. Additionally, the last column highlights the current capacity assumed for the MPC8536E six-layer PCB.
Table 5. Current Capacity of an 11-mil Trace Adam’s Model vs. IPC
Taking the last column from Table 5 and the number of 11-mil channels achieved in the six-layer PCB, Table 6 highlights the current capacity for both VDD_CORE and VDD_PLAT.
6.3 PLL FiltersThe MPC8536E has six PLLs which each require a filter circuit. The PLL pins are placed on the package in order to minimize noise and to allow ease during layout. An example layout for the filters are shown in Figure 12. This figure shows the filters for AVDD_PCI, AVDD_DDR, AVDD_CORE, and AVDD_PLAT. The
LocationCopper Plating
(oz.)
11-mil Trace(Adam’s Model)
(A)
11-mil Trace(IPC2221A)
(A)
11-mil Trace(Capacity Assumed for theMPC8536E Six-Layer PCB)
(A)
Outer 0.5 1.210 0.777 1.0
1.0 1.711 1.285 1.5
1.5 2.420 1.730 N/A
2.0 3.422 2.130 N/A
Inner 0.5 1.149 0.390 0.75
1.0 1.625 0.582 1.1
1.5 2.299 0.865 N/A
2.0 3.251 1.065 N/A
Table 6. Current Capacity Achieved in the Six-Layer PCB
Power RailCopper Weight
Used(oz.)
No. of 11-mil TracesSupplying Power
Current per Trace
(A)
Total Current Suppliedin Six-Layer PCB
(A)
Total Current Required
VDD_CORE 1.0 13 1.1 14.3 6.4 A (7 W/1.1 V)
VDD_PLAT 0.5 11 0.75 8.25 5.0 A (5 W/1.0 V)
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Power and Ground Strategy
residual filters would be similar. For the exact filter values refer to the MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications.
To ensure a high quality filter is realized, use the following rules:
• Place the components of the filter as close a possible to their respective pin
• Keep the traces as short as possible
• Use a 10-mil trace width or larger. An area fill is also a possibility.
• Maintain at least 20-mil clearance between the filter and other signals.
Figure 12. Example Layout for AVDD Filters
6.4 Sharing Power SuppliesThe six-layer design referenced in this application note assumes all processor powers referenced in Table 4 are supplied by unique power supplies. If the customer chooses, further sharing of power supplies can be achieved to reduce the number of supplies needed at the board-level. Table 7 shows some acceptable options for sharing MPC8536E power rails.
Filters
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Power and Ground Strategy
6.5 Bypass Capacitor PlacementBecause of the high current transients on the VDD_CORE and VDD_PLAT power pins, take care to bypass these power pins and to provide a good connection between the BGA pads and the power and ground planes. In particular, the SMD capacitors should have pads directly attached to the via ring (or even better, within it using via-in-pad methods). Figure 13 shows the dispersion of VDD_CORE and VDD_PLAT power pins along with the ground pattern.
Table 7. MPC8536E Power Requirements
Power Source Symbol Voltage Comments
Core power + PLL filter
VDD_COREAVDD_CORE
1.0 V If core and platform rails are shared, the upper core frequency is restricted. Additionally, there is no option for disabling the core power when the device is in ‘deep sleep’ state and the platform is alive.
PLLs are sourced from RC filter circuit derived from 1.0 V rail.
Platform (internal buses)
+ other PLL filters
VDD_PLATAVDD_PCIAVDD_DDRAVDD_LBIUAVDD_SRDSAVDD_SRDS2
SerDes SVDDXVDD
Separate filtered plane but derived from the same 1.0 V power regulator.
Memory GVDD 1.8 V Unique rail on the MPC8536E device. Could possibly be shared with another 1.8 V device on the board.
Ethernet LVDDTVDD
2.5 V 2.5 V is readily usable by most PHYs; however, 3.3 V is not suitable for RGMII mode.
Local bus BVDD 2.5 V requires low-voltage flash memory and so forth
Or alternatively
Ethernet LVDDTVDD
3.3 V 3.3 V is not suitable for RGMII mode
Local bus BVDD
PCI/Misc OVDD
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Power and Ground Strategy
Figure 13. MPC8536E VDD_CORE, VDD_PLAT, and Ground Pattern (Bottom View)
NOTE
This is a bottom view of the center portion of interest within the BGA array.
VDD_PLAT Ground
L M N P R T U
11
12
13
14
15
16
V W Y
17
18
19
20
21
22
23
VDD_CORE
24
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Power and Ground Strategy
After the power and grounds are escaped, the SMD 0402 capacitors can be placed so that the capacitor pads attach directly to the power vias on the side. Minimize or eliminate the trace between the via and the capacitor pad. Figure 14 shows three possible attachment methods.
Figure 14. MPC8536E SMD Capacitor Via Placement
Using either of these methods, Figure 15 shows the relative attachment of the SMD 0402 capacitors. Again, this is a view through the top of the board.
Vias Embedded in Pads Vias to the Side of Pads
All are SMD0402
Vias Offset From PadsBest Good OK
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Power and Ground Strategy
Figure 15. MPC8536E CORE, PLAT, and Ground SMD 0402 Capacitor Placement (Bottom View)
Other capacitors, such as those required for the other power rails, are not shown but can be attached in the same manner. If the PCB is not permitted to use via-in-pad connections, the capacitors can be shifted to attach to a pad in the area between the BGA pads. In that case, use the same relative pattern, but each capacitor shifts a little.
VDD_PLAT GROUND
L M N P R T U
11
12
13
14
15
16
V W Y
17
18
19
20
21
22
23
VDD_CORE
24
C
C C C C C
C C C C C C
C
C
C C C C C C C
CCC
22
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Power and Ground Strategy
6.6 Bulk CapacitorsBulk capacitors can be placed outside the periphery of the MPC8536E die, as close as reasonably possible. Systems with heatsinks and/or sockets probably need some additional spacing, but the high-frequency capacitors handle the fastest transients, allowing the bulk capacitors to be spaced a little further away. Keep them within 2 cm. Figure 16 shows the MPC8536E VDD_CORE and VDD_PLAT bulk capacitor placement.
Figure 16. MPC8536E Bulk Capacitor Placement (Top View)
MPC8536E0.46 mils
Low-ESRBulk Capacitors
0.46 mils
VCORE
Low-ESRBulk Capacitors
VPLAT Power Split
PowerSplit
A28A1
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Signal Layer Gerber Plot
7 Signal Layer Gerber PlotFigure 17 through Figure 20 show the signal layers for the six-layer PCB example. Again, the intent is to demonstrate that the MPC8536E signals can be broken in a six-layer PCB and does not include all the decoupling, nor does it show all the necessary pull-ups, AC caps, and other circuitry that would be required outside the BGA fan-out area. This level of detail is captured as part of the MPC8536E development system.
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Signal Layer Gerber Plot
Figure 17. Top Gerber Plot (Layer 1 of 6)
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Signal Layer Gerber Plot
Figure 18. Signal #2 Gerber Plot (Layer 3 of 6)
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Signal Layer Gerber Plot
Figure 19. Signal #3 Gerber Plot (Layer 4 of 6)
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Signal Layer Gerber Plot
Figure 20. Bottom Gerber Plot (Layer 6 of 6)
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Fan-Out Schematics
8 Fan-Out SchematicsThis section contains the fan-out schematics used to perform the six-layer PCB study. It does not include all the decoupling, nor does it show all the necessary pull-ups, AC caps, and other circuitry that would be required outside the BGA fan-out area. This level of detail is captured as part of the MPC8536E development system.
8536 DDR SECTION
P2
MAPAR_OUT
9C2
10C2
9C2 10C29C2 10C2
9B2 10B2
9C2
9A5 10A5
9A5 10A5
9D2
9A2 10A2
9A5 10A5
9C2 10C2
10C210C29C29C2
9B5 10B59B5 10B59B5 10B59B5 10B59B5 10B59A5 10B59A5 10A59A5 10A5
9A5 10A59A5 10A5
9A5 10A5
9A5 10A59A5 10A59A5 10A59A5 10A5
10C2
9C2
10C210C29C2
10D210D210D210D210D210D29D29D29D29D2
9C2
9D2 10D3
9A2 10B2
9D2 10D2
9C610C6
9B2 10B2
MCS0_B
MCS2_B
8536_FAN_OUT_SCHEMATIC
MRAS_BMCAS_B
MBA<0..2>
5
C11
MCKE0
MDQS2
MDQS3
M4
B4
A28
C5
F6E6H7E5
D12C13F14G14
F11D14G12
E13D13M2N1
M3C1D2J5K5A17B16C18E17B22A22D24C23
R2
K2J2R1P1K1J1P4N4K4J3P3N3L4L5F1E1B3A2G2F2C3B2J4H3G5E4H2G1F3D1
B15A16A19B19B14A15A18B18D16F17F18F19C16E16D19E19A21B21B24A25A20B20A23A24E21D22B25D25D21C22B26A26
F13L2L3C2G4B17D18B23C25
K15H15
G6C4H6D3
H9G10K10H10
J8H8
H13J13B8A8K6J6
H11J11B9A9
E7
B13B5A4
A6A13
F10E10F7D11A12A5B12E9F9A11C10D9A10C8G8B7
U1
C1
R4
R3
GVDD
18
MDIC0
MCK0_B
MECC_<0..7>
MDQS4_B
MWE_B
MODT3MODT2MODT1MODT0
MDQS8_BMDQS8MDQS7_BMDQS7MDQS6_BMDQS6MDQS5_BMDQS5
MDQS4MDQS3_B
MDQS2_B
MDQS1_BMDQS1MDQS0_BMDQS0
MCS3_B
MCS1_B
MCKE3MCKE2MCKE1
MCK5_BMCK5MCK4_BMCK4MCK3_BMCK3MCK2_BMCK2MCK1_BMCK1
MCK0
09
48
3534
12
08
37
MDM<0..8>
01
03
39
47
63
38
2120
11
24
17
43
46
62
10
MDIC1
18
50
5657
40
58
6160
MVREF
123
67
210
43
5
76
2
111213
0102030405
0708
1009
06
0706
02
0405
1314
16
1819
2223
25
29
3233
36
4142
4445
49
5152535455
59
1514
15
MDQ<00..63>
3130
0
MA<00..15>
0.1UF
8
01
00
4
00
26
2827
ENGINEER NAMEENGINEER:
5 6
FREESCALE C fid i l P i42 3
75 642 3
7
PROJECT:
MPC8536
PBGA_28X28X1MM_SKT
DDR_SDRAM
1 OF 10
MECC7MECC6MECC5MECC4MECC3MECC2MECC1MECC0
MWE_B
MVREF
MRAS_B
MODT3MODT2MODT1MODT0
MDQS8_BMDQS8
MDQS7_BMDQS7
MDQS6_BMDQS6
MDQS5_BMDQS5
MDQS4_BMDQS4
MDQS3_BMDQS3
MDQS2_BMDQS2
MDQS1_BMDQS1
MDQS0_BMDQS0
MDQ63MDQ62MDQ61MDQ60MDQ59MDQ58MDQ57MDQ56MDQ55MDQ54MDQ53MDQ52MDQ51MDQ50MDQ49MDQ48MDQ47MDQ46MDQ45MDQ44MDQ43MDQ42MDQ41MDQ40MDQ39MDQ38MDQ37MDQ36MDQ35MDQ34MDQ33MDQ32MDQ31MDQ30MDQ29MDQ28MDQ27MDQ26MDQ25MDQ24MDQ23MDQ22MDQ21MDQ20MDQ19MDQ18MDQ17MDQ16MDQ15MDQ14MDQ13MDQ12MDQ11MDQ10MDQ09MDQ08MDQ07MDQ06MDQ05MDQ04MDQ03MDQ02MDQ01MDQ00
MDM8MDM7MDM6MDM5MDM4MDM3MDM2MDM1MDM0
MDIC1MDIC0
MCS3_BMCS2_BMCS1_BMCS0_B
MCKE3MCKE2MCKE1MCKE0
MCK5_BMCK5MCK4_BMCK4MCK3_BMCK3MCK2_BMCK2MCK1_BMCK1MCK0_BMCK0
MCAS_B
MBA2MBA1MBA0
MAPAR_OUTMAPAR_ERR_B
MA15MA14MA13MA12MA11MA10MA09MA08MA07MA06MA05MA04MA03MA02MA01MA00
DRAWING
BIBIBIBI
BIBI
BIBI
BIBI
BIBI
BIBI
BIBIBIBI
OUT
OUTOUTOUTOUT
OUTOUTOUTOUT
BI
BI
OUT
OUT
OUTOUTOUTOUT
OUTOUT
OUTOUTOUTOUTOUTOUTOUTOUTOUTOUT
BI
OUT
IN
OUTOUT
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor Freescale Confidential Proprietary 27
Fan-Out Schematics
SATA OR SGMIIGMII
SS PCI EXPR
11C3
11C611C6
11C6
11C6
11C311C3
11C311C311C311C311C3
11C311C311D311D311D311D311D311D3
11C611C611C611C611C6
11C611D611D611D611D611D611D6
SD1_TX6_B
AC27SD1_RX7_BSD1_RX7
SD1_RX3_B
SD1_RX4
AA28
N21
TP14
M12M11P12P11
L9L8
N9N8P7P6
M7M6
L7T3
L6R7
T2
U1
Y22Y23W20W21V22V23U20U21
R20R21P22P23N20
M22M23
T23T22
AC28AB25AB26AA27
Y25Y26
T25T26R27R28P25P26N27N28
U27U28
V28V26
AE28M26V27
U1
TP112
TP48
TP142
TP141
TP90
TP89
TP18
TP17
TP4
TP3
TP2
TP1
TP10
TP9
TP6
TP5
TP12
TP11
R10
R9
TP16
TP15
R7
R8
TP13TP8TP7
SD2_RX0_B
SD1_IMP_CAL_RX
SD1_PLL_TPDSD1_PLL_TPA
SD1_IMP_CAL_TX
SD2_TX1_BSD2_TX1SD2_TX0_BSD2_TX0
SD2_TST_CLK_BSD2_TST_CLK
SD2_RX1_BSD2_RX1
SD2_RX0
SD2_REF_CLK_BSD2_REF_CLK
SD2_PLL_TPDSD2_PLL_TPA
SD2_IMP_CAL_TXSD2_IMP_CAL_RX
SD1_TX7_BSD1_TX7
SD1_TX6SD1_TX5_BSD1_TX5
SD1_TX4_BSD1_TX4
SD1_TX3_BSD1_TX3
SD1_TX2_BSD1_TX2
SD1_TX1_BSD1_TX1
SD1_TX0_BSD1_TX0
SD1_TST_CLK_BSD1_TST_CLK
SD1_RX6_BSD1_RX6SD1_RX5_BSD1_RX5SD1_RX4_B
SD1_RX3SD1_RX2_BSD1_RX2SD1_RX1_BSD1_RX1SD1_RX0_BSD1_RX0
SD1_REF_CLK_BSD1_REF_CLK
200
200
100
8536_FAN_OUT_SCHEMATIC
100
DRAWINGENGINEER NAME
ENGINEER:
5 6
SC C f42 3
75 642 3
7
PROJECT:
PBGA_28X28_1MM_SKT
MPC8536SERDES 23 OF 10
SD2_TX1_BSD2_TX1
SD2_TX0_BSD2_TX0
SD2_TST_CLK_BSD2_TST_CLK
SD2_RX1_BSD2_RX1SD2_RX0_BSD2_RX0
SD2_REF_CLK_BSD2_REF_CLK
SD2_PLL_TPDSD2_PLL_TPA
SD2_IMP_CAL_TXSD2_IMP_CAL_RX
AGND_SRDS2
PBGA_28X28_1MM_SKT
MPC8536SERDES 12 OF 10
SD1_TX7_BSD1_TX7
SD1_TX6_BSD1_TX6
SD1_TX5_BSD1_TX5
SD1_TX4_BSD1_TX4
SD1_TX3_BSD1_TX3
SD1_TX2_BSD1_TX2
SD1_TX1_BSD1_TX1
SD1_TX0_BSD1_TX0
SD1_TST_CLK_BSD1_TST_CLK
SD1_RX7_BSD1_RX7SD1_RX6_BSD1_RX6SD1_RX5_BSD1_RX5SD1_RX4_BSD1_RX4
SD1_RX3_BSD1_RX3SD1_RX2_BSD1_RX2SD1_RX1_BSD1_RX1SD1_RX0_BSD1_RX0
SD1_REF_CLK_BSD1_REF_CLK
SD1_PLL_TPDSD1_PLL_TPA
SD1_IMP_CAL_TXSD1_IMP_CAL_RXAGND_SRDS
INININ
INININININ
ININININININININ OUT
OUTOUTOUTOUTOUTOUTOUT
OUTOUTOUTOUTOUTOUTOUTOUT
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
28 Freescale Confidential Proprietary Freescale Semiconductor
Fan-Out Schematics
PCI 32 BIT
12B1
12B612B3
12B612B3
12B1 12B3 12B6
12D1 12D3 12D5
12B8 12C3 12C612B6 12B8 12C312B6 12B8 12C312B3 12B6 12B8
12B1 12B3 12B6
12B1 12B3 12B6
12B1 12B3 12B6
12C3 12C6 12C8
12B1 12B3 12B6
12B1 12B3 12B6
12B1 12B3 12B6
12B1
PCI1_REQ0_B
PCI1_REQ2_B
TP23
PCI1_REQ1_B
PCI1_GNT2_BPCI1_GNT1_B
GPIO02_PCI1_GNT3_B
GPIO00_PCI1_REQ3_BGPIO01_PCI1_REQ4_B
PCI1_SERR_B
PCI1_IDSEL
8536_FAN_OUT_SCHEMATIC
0100
0302
04050607
0908
101112
1413
1516171819202122
2423
25
TP145
2726
28
3029
31
PCI1_AD<31..00>
TP25
TP19
U1
Y15AE15
AA15
AE25AF26AG26AF25AC24AG27AD24AG25AE24AG24AH23AH24
AE23AF23AC20AE19AF18AC19AE18AB19AB18AE17AD17AA18AC16AB17AC15AA17Y17AB15
AH25AD22AD20AD18
AH26
AC21
AE20
W18Y16AF14
AE16
AB20
AC22
AB21
AA16W16AF13
AF22
AD21
AF21
AC14
AC23
GPIO03_PCI1_GNT4_B
PCI1_CLK
PCI1_C_BE0_BPCI1_C_BE1_BPCI1_C_BE2_BPCI1_C_BE3_B
PCI1_DEVSEL_B
PCI1_FRAME_B
PCI1_IRDY_B
PCI1_PAR
PCI1_PERR_B
PCI1_STOP_B
PCI1_TRDY_B
TP144
PCI1_GNT0_B
TP22
AD26
DRAWINGENGINEER NAME
ENGINEER:
5 6
SC C f42 3
75 642 3
7
PROJECT:
BIBI
BIBI
PBGA_28X28_1MM_SKT
MPC8536PCI1
4 OF 10
PCI1_GNT0_B
PCI1_TRDY_B
PCI1_STOP_B
PCI1_SERR_B
PCI1_REQ2_BPCI1_REQ1_BPCI1_REQ0_B
PCI1_PERR_B
PCI1_PAR
PCI1_IRDY_B
PCI1_IDSEL
PCI1_GNT2_BPCI1_GNT1_B
PCI1_FRAME_B
PCI1_DEVSEL_B
PCI1_C_BE3_BPCI1_C_BE2_BPCI1_C_BE1_BPCI1_C_BE0_B
PCI1_CLK
PCI1_AD31PCI1_AD30PCI1_AD29PCI1_AD28PCI1_AD27PCI1_AD26PCI1_AD25PCI1_AD24PCI1_AD23PCI1_AD22PCI1_AD21PCI1_AD20PCI1_AD19PCI1_AD18PCI1_AD17PCI1_AD16PCI1_AD15PCI1_AD14PCI1_AD13PCI1_AD12PCI1_AD11PCI1_AD10PCI1_AD09PCI1_AD08PCI1_AD07PCI1_AD06PCI1_AD05PCI1_AD04PCI1_AD03PCI1_AD02PCI1_AD01PCI1_AD00
GPIO03_PCI1_GNT4_BGPIO02_PCI1_GNT3_B
GPIO01_PCI1_REQ4_BGPIO00_PCI1_REQ3_B
BIBIBIBI
BI
BI
BI
BI
BIBI
BIBIBIBIBI
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor Freescale Confidential Proprietary 29
Fan-Out Schematics
LOCAL BUS
13D2
13B2
13C1
13A2
LDP0
LDP3LDP2LDP1
LA<27..31>
SPI_CS3_SDHC_DAT7SPI_CS2_SDHC_DAT6SPI_CS1_SDHC_DAT5SPI_CSO_SDHC_DAT4
SPI_MOSI
SPI_CLKSPI_MISO
SDHC_DAT3SDHC_DAT2SDHC_DAT1SDHC_DAT0
SDHC_CMDSDHC_CLK
LWE3_B_LBS3_BLWE2_B_LBS2_BLWE1_B_LBS1_B
LWE0_B_LBS0_B_LFWE_B
LSYNC_OUTLSYNC_IN
LGPL5LGPL4_LGTA_B_LUPWAIT_LPBSE_LFRB
LGPL3_LFWP_BLGPL2_LOE_B_LFRE_B
LGPL1_LFALELGPL0_LFCLE
LCS7_B_DMA_DDONE2_BLCS6_B_DMA_DACK2_BLCS5_B_DMA_DREQ2_B
LCS4_BLCS3_BLCS2_BLCS1_BLCS0_B
LCLK2LCLK1LCLK0
LBCTL
LALE
GPIO5_SDHC_WPGPIO4_SDHC_CD
LAD<00..31>
TP185
TP132TP131TP130
31
2930
2827
31302928272625
U1
AH11AG10L19
K16K17H17G17
K22L21L22K23K24L24L25K25L28L27K28K27J28H28H27G27G26F28F26F25E28E27E26F24E24C26G24E23G23F22G22G21
J26
J25
J24H25
K18G19H19H20G16H16J16L18
K26G28B27E25
J20K20G20H18L20K19
D27D28
J22H22H23H21
AG13AH10
AG12AH12AH13AG11
AD8
AE8AC10AF9AA10
AD9AF8
H24242322212019181716151413121110
0809
0706050403020100
TP161TP160TP129
TP128TP127TP126
TP124TP125
TP123TP122
TP120
TP121
TP118TP119
TP117
TP26TP46
TP41TP40TP39
TP49TP43
TP45TP42
TP47TP44
TP38
TP36TP37
TP35
TP34TP33TP32TP31TP30TP29TP28TP27
8536_FAN_OUT_SCHEMATIC
ENGINEER NAMEENGINEER:
5 6
FREESCALE Confidential Proprietary42 3
75 642 3
7
PROJECT:
DRAWING
INTERFACESPI & SD
PBGA_28X28_1MM_SKT
MPC8536LOCAL BUS5 OF 10
SPI_CS3_SDHC_DAT7SPI_CS2_SDHC_DAT6SPI_CS1_SDHC_DAT5SPI_CS0_SDHC_DAT4
SPI_MOSI
SPI_CLKSPI_MISO
SDHC_DAT3SDHC_DAT2SDHC_DAT1SDHC_DAT0
SDHC_CMDSDHC_CLK
LWE3_B_LBS3_BLWE2_B_LBS2_BLWE1_B_LBS1_B
LWE0_B_LBS0_B_LFWE_B
LSYNC_OUTLSYNC_IN
LGPL5LGPL4_LGTA_B_LUPWAIT_LPBSE_LFRB
LGPL3_LFWP_BLGPL2_LOE_B_LFRE_B
LGPL1_LFALELGPL0_LFCLE
LDP3LDP2LDP1LDP0
LCS7_B_DMA_DDONE2_BLCS6_B_DMA_DACK2_BLCS5_B_DMA_DREQ2_B
LCS4_BLCS3_BLCS2_BLCS1_BLCS0_B
LCLK2LCLK1LCLK0
LBCTL
LALE
LAD31LAD30LAD29LAD28LAD27LAD26LAD25LAD24LAD23LAD22LAD21LAD20LAD19LAD18LAD17LAD16LAD15LAD14LAD13LAD12LAD11LAD10LAD09LAD08LAD07LAD06LAD05LAD04LAD03LAD02LAD01LAD00
LA31LA30LA29LA28LA27 GPIO5_SDHC_WP
GPIO4_SDHC_CD
OUT
OUT
OUT
BI
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
30 Freescale Confidential Proprietary Freescale Semiconductor
Fan-Out Schematics
GIBABIT ETHERNET - RGMII
14C3
14C3
14B3
14B3
14B314B314B314B3
14B314B314B314C3
14C3
14C314C314C314C3
14D3
14D314D314D314D3
14C3
14A114A1
14D3
TSEC3_RXD7
TSEC3_RX_DVTSEC3_RX_ERTSEC3_RX_CLK
EC_GTX_CLK125
TSEC_1588_CLK_OUTTSEC_1588_TRIG_OUT0TSEC_1588_TRIG_OUT1TSEC_1588_PULSE_OUT1
TP167TP166
TSEC3_RXD6
TP178TP179
TSEC3_GTX_CLKTSEC3_TX_CLK
TSEC3_TX_EN
V8U8
W10U11
W7W8
T11V11
V10W9
T12
V9T8T7T5T6
U9V5
U10
U12U13U6V6V1U3U2V3
T4V2
U1
U5T10T9
AA8AA5Y8Y5W3W5W4W6
AB5W1
AB4
AB3AB7AB8Y6
AA2Y3Y1Y2
Y9AA1
AA3
W2AA9AB6
Y11Y10 AA6
U1
TP24TP21TP20
TP180TP181TP182TP183
TP184TP177
TP176TP175TP174TP173
TP172TP162
TP165TP164TP163
TP151TP150
TP149TP148TP147TP146
TP157TP156
TP155TP154TP153TP152
TP50
TSEC3_TXD5
TSEC3_TXD7
TSEC_1588_TRIG_IN1TSEC_1588_TRIG_IN0
TSEC_1588_PULSE_OUT2
TSEC_1588_CLK
TSEC3_TX_ER
TSEC3_TXD6
TSEC3_TXD4TSEC3_TXD3TSEC3_TXD2TSEC3_TXD1TSEC3_TXD0
TSEC3_RXD5TSEC3_RXD4TSEC3_RXD3TSEC3_RXD2TSEC3_RXD1TSEC3_RXD0
TSEC3_CRSTSEC3_COL
TSEC1_TX_ERTSEC1_TX_EN
TSEC1_TX_CLK
TSEC1_TXD7TSEC1_TXD6TSEC1_TXD5TSEC1_TXD4
TSEC1_TXD3TSEC1_TXD2TSEC1_TXD1TSEC1_TXD0
TSEC1_RX_ERTSEC1_RX_CLK
TSEC1_RXD7TSEC1_RXD6TSEC1_RXD5TSEC1_RXD4
TSEC1_RXD3TSEC1_RXD2TSEC1_RXD1TSEC1_RXD0
TSEC1_GTX_CLKTSEC1_CRSTSEC1_COL
EC_MDIOEC_MDC
8536_FAN_OUT_SCHEMATIC
TSEC1_RX_DV
ENGINEER NAMEENGINEER:
75 642 3
PROJECT:
PBGA_28X28_1MM_SKT
MPC8536ETHERNET6 OF 10
TSEC_1588_TRIG_OUT1TSEC_1588_TRIG_OUT0
TSEC_1588_TRIG_IN1TSEC_1588_TRIG_IN0
TSEC_1588_PULSE_OUT2TSEC_1588_PULSE_OUT1
TSEC_1588_CLK_OUTTSEC_1588_CLK
TSEC3_TX_ERTSEC3_TX_EN
TSEC3_TX_CLK
TSEC3_TXD7TSEC3_TXD6TSEC3_TXD5TSEC3_TXD4TSEC3_TXD3TSEC3_TXD2TSEC3_TXD1TSEC3_TXD0
TSEC3_RX_ERTSEC3_RX_DV
TSEC3_RX_CLK
TSEC3_RXD7TSEC3_RXD6TSEC3_RXD5TSEC3_RXD4TSEC3_RXD3TSEC3_RXD2TSEC3_RXD1TSEC3_RXD0
TSEC3_GTX_CLKTSEC3_CRSTSEC3_COL
TSEC1_TX_ERTSEC1_TX_EN
TSEC1_TX_CLK
TSEC1_TXD7TSEC1_TXD6TSEC1_TXD5TSEC1_TXD4TSEC1_TXD3TSEC1_TXD2TSEC1_TXD1TSEC1_TXD0
TSEC1_RX_ERTSEC1_RX_DV
TSEC1_RX_CLK
TSEC1_RXD7TSEC1_RXD6TSEC1_RXD5TSEC1_RXD4TSEC1_RXD3TSEC1_RXD2TSEC1_RXD1TSEC1_RXD0
TSEC1_GTX_CLKTSEC1_CRSTSEC1_COL
EC_MDIOEC_MDC EC_GTX_CLK125
INININ
OUTOUTOUT
OUT
IN
IN
ININININ
OUT
OUT
OUTOUTOUTOUT
IN
BIOUT
IN
IN
OUT
OUT
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor Freescale Confidential Proprietary 31
Fan-Out Schematics
MISC / OTHERS
8536_FAN_OUT_SCHEMATIC
CLK_OUT
AB14
AA12
AF10
AF12
AC12
AD12
AB12
Y12
AE11
AH21
V19W19
AH27
AA13
R5R4
AF28AH28
AG28
AH14
AG19
AF15
AC26AE27
W11W14V12W13W12
V13
Y14
AC25
AA20AA21
AC17
AD14AD13AE13AB22Y19AA22AF16AG17AF19AB23AF17AG22
AG14AH15
AH22AG21
AG15
AG16
AD11AB10
AB11AA11
AE10AD6
AC13W15
AH17AG18
AG20
U1
TP114TP115
TP113
TP159TP158
TP81
TP79TP78TP77TP76
TP75TP74TP73
TP71
TP70TP69TP68
TP61TP62TP63TP64TP65TP66TP67
TP60
TP72
TP80
TP59
TP58
TP57TP56
TP55TP54
TP53TP52
TP51
TP111
TP110
TP109
TP108TP107TP106TP105TP104
TP103TP102
TP101TP100
TP99 TP98
TP97
TP96
TP92TP93TP94TP95
TP91
TP88TP87TP86
TP85TP84
TP83TP82
TEST_SEL_B
UDE_B
UART_SOUT1
UART_SOUT0
UART_SIN1
UART_SIN0
UART_RTS1_B
UART_RTS0_B
UART_CTS1_B
UART_CTS0_B
TRST_B
TRIG_OUT_READY_QUIESCE_BTRIG_IN
TMS
TEMP_CATHODETEMP_ANODE
TDOTDI
TCK
SYSCLK
SRESET_B
RTC
POWER_OKPOWER_EN
MSRCID4MSRCID3MSRCID2MSRCID1MSRCID0
MDVAL
MCP_B
LSSD_MODE_B
L2_TSTCLKL1_TSTCLK
IRQ_OUT_B
IRQ11_DMA_DDONE3_BIRQ10_DMA_DACK3_BIRQ09_DMA_DREQ3_BIRQ08IRQ07IRQ06IRQ05IRQ04IRQ03IRQ02IRQ01IRQ00
IIC2_SDAIIC2_SCL
IIC1_SDAIIC1_SCL
HRESET_REQ_B
HRESET_B
GPIO15_DMA_DREQ1_BGPIO14_DMA_DREQ0_B
GPIO13_DMA_DDONE1_BGPIO12_DMA_DDONE0_B
GPIO11_DMA_DACK1_BGPIO10_DMA_DACK0_B
DDRCLK
CKSTP_OUT_BCKSTP_IN_B
ASLEEP
ENGINEER NAMEENGINEER:
75 642 3
PROJECT:
PBGA_28X28_1MM_SKT
MPC8536MISC
7 OF 10TEST_SEL_B
UDE_B
UART_SOUT1
UART_SOUT0
UART_SIN1
UART_SIN0
UART_RTS1_B
UART_RTS0_B
UART_CTS1_B
UART_CTS0_B
TRST_B
TRIG_OUT_READY_QUIESCE_BTRIG_IN
TMS
TEMP_CATHODETEMP_ANODE
TDOTDI
TCK
SYSCLK
SRESET_B
RTC
POWER_OKPOWER_EN
MSRCID4MSRCID3MSRCID2MSRCID1MSRCID0
MDVAL
MCP_B
LSSD_MODE_B
L2_TSTCLKL1_TSTCLK
IRQ_OUT_B
IRQ11_DMA_DDONE3_BIRQ10_DMA_DACK3_BIRQ09_DMA_DREQ3_BIRQ08IRQ07IRQ06IRQ05IRQ04IRQ03IRQ02IRQ01IRQ00
IIC2_SDAIIC2_SCL
IIC1_SDAIIC1_SCL
HRESET_REQ_B
HRESET_B
GPIO15_DMA_DREQ1_BGPIO14_DMA_DREQ0_B
GPIO13_DMA_DDONE1_BGPIO12_DMA_DDONE0_B
GPIO11_DMA_DACK1_BGPIO10_DMA_DACK0_B
DDRCLKCLK_OUT
CKSTP_OUT_BCKSTP_IN_B
ASLEEP
A S
trategy for R
ou
ting th
e MP
C8536E
in a S
ix-Layer P
CB
,R
ev. 0
32Freescale C
onfidential Proprietary
Freescale Sem
iconductor
Fan
-Ou
t Sch
ematics
PCI EXPRESS RCVR PWR
MISC SIGNALS
ANALOG FILTERS
GIGABIT ETHERNET
DDR POWER
CORE
PCI EXPRESS XMTR PWR
10
10
1
1
10
10
10
LOCAL BUS
PLATFORM
7
Tue Jul 31 12:15:27 2007
AH16
E22
SENSEVSSSENSEVDD
AVDD_SRDS2AVDD_SRDS
AVDD_PLATAVDD_PCI1AVDD_LBIU
AVDD_DDR
AVDD_CORE
SXVDD
VDD_PLAT
BVDD
U1
AH19C28
AH20
AH18 W28 T1L23
J18
J23
J19
F20
F23
H26
J21
B1 B11
C7 C9 C14
C17
D4 D6 R3 D15
E2 E8 C24
E18
F5 E14
C21
G3 G7 G9 G11
H5 H12
F15
J10
K3 K12
K14
H14
D20
E11
M1 N5
AA7
AA4
Y18AG2AD4AB16AF6AC18AB13AD10AE14AD16AD25AF27AE22AF11AF20AF24
R6N7M9
V15
V16
M27N25P28R24R26T24T27U25W24W26Y24Y27AA25AB28AD27
V4 U7
P13U16L16M15N14R14P15N16M13U14T13L14T15
T19
M17
T17
V17
U18
R18
N18
M19
P19
P17
R11N12L11
M21N23P20R22T20U23V21W22Y20AA23
R16
LTVDD
TP134TP133
OVDD
GVDD
VDD_CORE
SXVDD
14
C135
C133
C134
C132
C136
C130
C131
C116
C129C122
C123
C118
C119
C127
C121 C128
C124
C126
C125
C120
C117
R13
R11
R5
R6
R2
R12
R1
VDD_CORE
2.2UF
2.2UF
AVDD_PLAT
AVDD_PCI1
2.2UF
2.2UF
AVDD_LBIU
2.2UF
0.1UF
0.1UF
2.2UF2.2UF
2.2UF
0.1UF
AVDD_CORE
2.2UF
AVDD_SRDS2
3300PF
0.1UF
0.1UF
AVDD_DDR
VDD_PLAT2.2UF 2.2UF
AVDD_SRDS
2.2UF
2.2UF
2.2UF
3300PF
SXVDD
8536_FAN_OUT_SCHEMATIC
X1
7C87C8
7D87D87D8
7C8
7D8
7D5
7D5
7D5
7D5
7D5
7D5
7D5
ENGINEER NAMEENGINEER:
5 6
FREESCALE Confidential Proprietary42 31
A
B
C
D
7 85 642 31
OFPAGE:
8
REV
DATE:
7
PROJECT:
DRAWING
PBGA_28X28_1MM_SKT
MPC8536
POWER
8 OF 10
VDD_PLAT9
VDD_PLAT10
XVDD10
BVDD03
BVDD08
XVDD09XVDD08XVDD07XVDD06XVDD05XVDD04XVDD03XVDD02XVDD01
X2VDD03X2VDD02X2VDD01
GVDD34
GVDD33
VDD_PLAT8
VDD_PLAT7
VDD_PLAT6
VDD_PLAT5
VDD_PLAT4
VDD_PLAT3
VDD_PLAT2
VDD_PLAT1
VDD_CORE14VDD_CORE13VDD_CORE12VDD_CORE11VDD_CORE10VDD_CORE09VDD_CORE08VDD_CORE07VDD_CORE06VDD_CORE05VDD_CORE04VDD_CORE03VDD_CORE02VDD_CORE01
TVDD2
TVDD1
SVDD15SVDD14SVDD13SVDD12SVDD11SVDD10SVDD09SVDD08SVDD07SVDD06SVDD05SVDD04SVDD03SVDD02SVDD01
SENSEVSS
SENSEVDD
S2VDD03S2VDD02S2VDD01
OVDD16OVDD15OVDD14OVDD13OVDD12OVDD11OVDD10OVDD09OVDD08OVDD07OVDD06OVDD05OVDD04OVDD03OVDD02OVDD01
LVDD2
LVDD1
GVDD32
GVDD31
GVDD30
GVDD29
GVDD28
GVDD27
GVDD26
GVDD25
GVDD24
GVDD23
GVDD22
GVDD21
GVDD20
GVDD19
GVDD18
GVDD17
GVDD16
GVDD15
GVDD14
GVDD13
GVDD12
GVDD11
GVDD10
GVDD09
GVDD08
GVDD07
GVDD06
GVDD05
GVDD04
GVDD03
GVDD02
GVDD01
BVDD07
BVDD06
BVDD05
BVDD04
BVDD02
BVDD01
AVDD_SRDS2
AVDD_SRDS
AVDD_PLAT
AVDD_PCI1
AVDD_LBIU
AVDD_DDR
AVDD_CORE
A S
trategy for R
ou
ting th
e MP
C8536E
in a S
ix-Layer P
CB
,R
ev. 0
Freescale Sem
iconductorFreescale C
onfidential Proprietary
33
Fan
-Ou
t Sch
ematics
8
Tue Jul 31 11:49:05 20
USB2_D5
8536_FAN_OUT_SCHEMATIC
X1
USB3_PWRFAULT
AH8
AH9
AG7AG8
AH7AG6AH6AG5AG4AH4AG3AH3
AH5
AD7
AC8
AC7AF7
AE6AC6AF5AE5AF4AE4AE3AD3
AD5
AG1
AH2
AF2AH1
AF1AE2AE1AD2AC2AC1AB2AB1
AD1
R9L13V25K9W17J9R8N10N24W27M25P10J7F12B6R10L10K13D10D7C19
AC9AG9
AC4AC3
U1
Y21W23V20U22T21R23P21N22M24M20
L12N11M10R12
AD28AB27AB24AA26AA24Y28W25V24U26U24T28R25P27P24N26M28
M8N6P9P8
R13N13AA14AB9AE12
Y4U4
AC5Y7V7
A27AE9AG23AD15L15AD23AD19AC11B28
AE21AA19AE26Y13C27V18U19U17U15L17T18T16R19R17R15M14P18P16P5N2
N19N17N15P14M18M16V14T14K8K7
L26K11J27M5
F27J17J15J12C20H4
G25A7
A14C6
G18G15G13H1
F21L1
D17E15E12F16A3F8
K21J14E3
AF3B10D8
E20C15C12D23D26F4
AE7D5 U1
TP171TP170
TP169TP168
1110
2337
8
15
4
12913
16
25
6
5
14
171819202224
12
21
U2
1110
2337
8
15
4
12913
16
25
6
5
14
171819202224
12
21
U4
1110
2337
8
15
4
12913
16
25
6
5
14
171819202224
12
21
U3
ISP1505CBS
USB2_PWRFAULT
GPIO08_USB2_PCTL0GPIO09_USB2_PCTL1
USB2_PWRFAULT
USB3_D1USB3_D2
NC07
NC21NC20NC19NC18NC17NC16NC15NC14NC13
USB3_STP
USB3_NXTUSB3_DIR
USB3_D7USB3_D6USB3_D5USB3_D4USB3_D3
USB3_D0
USB3_CLK
USB2_STP
USB2_NXTUSB2_DIR
USB2_D7USB2_D6USB2_D5USB2_D4USB2_D3USB2_D2USB2_D1USB2_D0
USB2_CLK
USB1_STP
USB1_PWRFAULT
USB1_NXTUSB1_DIR
USB1_D7USB1_D6USB1_D5USB1_D4USB1_D3USB1_D2USB1_D1USB1_D0
USB1_CLK
NC12NC11NC10NC09NC08
NC06NC05NC04NC03NC02NC01
GPIO07_USB1_PCTL1GPIO06_USB1_PCTL0
USB1_D6
USB1_D4
USB1_DIR
ISP1505CBS
USB3_D7
USB3_NXTUSB3_CLK
USB3_D0USB3_D1USB3_D2
USB3_STPUSB3_DIR
USB2_NXTUSB2_CLK
USB3_D3USB3_D4
USB3_D6
USB2_DIRUSB2_STP
USB3_D5
USB1_PWRFAULT
USB1_STPUSB1_NXT
USB1_D7
USB1_D5
USB1_D3USB1_D2USB1_D1USB1_D0
USB2_D0USB2_D1USB2_D2USB2_D3USB2_D4
USB2_D6USB2_D7
USB1_CLK
ISP1505CBS
USB3_PWRFAULT
8B6
8D6
8C6
8B6
8D48D4
8D4
8D48D4
8D48D48D48D48D4
8D4
8D4
8C4
8C48C4
8C48C48C48C48C48B48B48B4
8C4
8A4
8A6
8B48A4
8A48A48A48A48A48A48A48A4
8B4
8B6
8B6
8B6
8C6
8C68C6
8C68C68C6
8C68C6
8C68C6
8C68C6
8C6
8C68C6
8C6
8B6
8B68B6
8B6
8B6
8B68B68B68A6
8B68B68B68B68B6
8B68C6
8B6
8D6
DRAWINGENGINEER NAME
ENGINEER:
5 6
FREESCALE Confidential Proprietary42 3
7 85 642 3
OFPAGE:
8
REV
DATE:
7
PROJECT:
PBGA_28X28_1MM_SKT
MPC8536USB
10 OF 10NC07
NC21NC20NC19NC18NC17
USB3_PWRFAULT
NC16NC15NC14NC13
USB3_STP
USB3_NXTUSB3_DIR
USB3_D7USB3_D6USB3_D5USB3_D4USB3_D3USB3_D2USB3_D1USB3_D0
USB3_CLK
USB2_STP
USB2_PWRFAULT
USB2_NXTUSB2_DIR
USB2_D7USB2_D6USB2_D5USB2_D4USB2_D3USB2_D2USB2_D1USB2_D0
USB2_CLK
USB1_STP
USB1_PWRFAULT
USB1_NXTUSB1_DIR
USB1_D7USB1_D6USB1_D5USB1_D4USB1_D3USB1_D2USB1_D1USB1_D0
USB1_CLK
NC12NC11NC10NC09NC08
NC06NC05NC04NC03NC02NC01
GPIO09_USB2_PCTL1GPIO08_USB2_PCTL0
GPIO07_USB1_PCTL1GPIO06_USB1_PCTL0
PBGA_28X18_1MM_SKT
MPC8536GROUND9 OF 10
GND11
X2GND04
XGND10XGND09XGND08XGND07XGND06XGND05XGND04XGND03XGND02XGND01
X2GND03X2GND02X2GND01
SGND16SGND15SGND14SGND13SGND12SGND11SGND10SGND09SGND08SGND07SGND06SGND05SGND04SGND03SGND02SGND01
S2GND04S2GND03S2GND02S2GND01
GND89GND88GND87GND86GND85GND84GND83GND82GND81GND80GND79GND78GND77GND76GND75GND74GND73GND72GND71GND70GND69GND68GND67GND66GND65GND64GND63GND62GND61GND60GND59GND58GND57GND56GND55GND54GND53GND52GND51GND50GND49GND48GND47GND46GND45GND44GND43GND42GND41GND40GND39GND38GND37GND36GND35GND34GND33GND32GND31GND30GND29GND28GND27GND26GND25GND24GND23GND22GND21GND20GND19GND18GND17GND16GND15GND14GND13GND12
GND10GND09GND08GND07GND06GND05GND04GND03GND02GND01
RESET*
VCC_2VCC_1
VBUS_FAULT
GND_PAD
XTAL2XTAL1
CLOCKNXTSTPDIR
DATA7DATA6DATA5DATA4DATA3DATA2DATA1DATA0
RREF
DM
DP
REG1V8
VCC
REG3V3
RESET*
VCC_2VCC_1
VBUS_FAULT
GND_PAD
XTAL2XTAL1
CLOCKNXTSTPDIR
DATA7DATA6DATA5DATA4DATA3DATA2DATA1DATA0
RREF
DM
DP
REG1V8
VCC
REG3V3
RESET*
VCC_2VCC_1
VBUS_FAULT
GND_PAD
XTAL2XTAL1
CLOCKNXTSTPDIR
DATA7DATA6DATA5DATA4DATA3DATA2DATA1DATA0
RREF
DM
DP
REG1V8
VCC
REG3V3
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
34 Freescale Confidential Proprietary Freescale Semiconductor
Fan-Out Schematics
MEMORY CONNECTOR #1
1D6
1D610C2
1C610B2
1B610A2
1B5 10B51B5 10B51B5 10B5
1A5 10A5
1A5 10A5
1B5 10B5
1A5 10A5
1A5 10A5
1A5 10A5
1A5 10A5
1A5 10A5
1A5 10A5
1A5 10A5
1A5 10A5
1A5 10A5
1A5 10A5
1B5 10B5
1B5 10B5
1A21A2
10D21D11A710D2
1A2
1D610C2
1D6
1D6
1D6
10D210D2
1A2
1D61D6
1C610B2
1B610B2
1B2 10C6
1D610D3
1A21A2
1D610C2
Tue
CONN_240_DDR2_VERT_SPECIAL_1OF2
161
233
73
1
238
119120
101240239
76193
18
55
192
1968
77195
45461131141041059293838436372728151667
1312129
236235230229
128
117116111110227226218217108107
123
999821521420920896959089
122
20620520019987868180159158
10
15315240393433150149144143
9
313025241411401321312221
43
164232223211202155146134125
17152
221
138
186
220
137
185
168167162
49484342
74
5419071
17717958180606118263
1731741961765770
183188 P1
1811751707875726256
194191
51
18718417817269676459
197189
53
6650
224212203165156147135126102
P2 GVDD
GVDD
CONN_240_DDR2_VERT_SPECIAL_1OF2
MCS0_B
MWE_B
MA<00..15>
DDR2 DIMM
MECC_<0..7>
MDQS8_BMDQS8MDQS7_B
MDQS4_B
MDQS5_B
MDQS6_B
MDQS2_B
MDQS3_B
MDQS0_B
MDQS1_B
MDQS0
MDQS1
MDQS2
MDQS3
MDQS4
MDQS5
MDQS6
MDQS7
07
MCK2MCK2_B
MAPAR_ERR_BMVREF
MCK1_B
MRAS_B
MODT0
MCS1_B
MODT1
I2C_SDAI2C_SCL
MCK0
MCKE1MCKE0
1
0001
45
7
2
02
06
09
07
050403
MBA<0..2>
MDM<0..8>
654
MDQ<00..63>
0908
06050403020100
23
8536_FAN_OUT_SCHEMATIC
0
7
MAPAR_OUT
11
0
12
6
35
10111213
151617
19202122
24252627
3334
3637
39404142434445464748495051525354555657585960616263
31
14
18
12
10
08
8
3210
3
282930
32
131415
MCK1MCK0_B
MCAS_B
38
DRAWINGENGINEER NAME
ENGINEER:
5 642 3
75 642 3
REV
7
PROJECT:
DQS0n
(DQS16)(DQS17)
(ECC0)(ECC1)(ECC2)(ECC3)
(AP)
(ECC4)(ECC5)(ECC6)(ECC7)
NC
Normally NC on DDR2
165, 203, 212, 224233
102
Not Supported126, 135, 147, 156
(DQS9)(DQS10)(DQS11)(DQS12)(DQS13)(DQS14)(DQS15)
DM8
DQ12
DQ61
DQ48
DQ60
DM5DM4
DQ33
DQ62
DQ18
CK_L0
DQ54
DQ9
A15
DQ51
S1
BA2
CK_L2
DQ36
VDDSPD
DM3
DQS3nDQS4
DM0
DQ53
DQ55
DQS7
ODT0
DQ47
A12
DQ39
DQ14
DQ58
A5
DQ46
RAS
DQ26
DQ23
DQ1
DQ52
DQ45
A11
DQS6n
DQS8
CB5
DQ30
CKE1
DQ43
DQ28
A3A4
CB6
A2
A10
DQ15
DQ38
DQ56
DQ42
CB1
DQ25
DQ41
DM1
RESET
A14
SCL
DQ20
A13
DQS2
DQ3
A8A9
DQ6
DQ44
DQ32
DQ7
WE
DQ4
DM7
A6
CK_H2
CB2
CB4CB3
CK_H0
A1
DQ29
DQ8
DQ63
DQS2n
CAS
CB7
DQ5
DQ0
BA0
SA0
DQ34
DQS7n
DQ22DQ21
DQ13
DQ11
DQ35
DQ49
BA1
DM6
DQ19
CK_L1
DQ59
ODT1
CK_H1
PWR1_SEL_OPT1PWR2_SEL_OPT1
SA2
DQS1nDQS1
DQS0
DQS6DQS5nDQS5
DQS4n
DQS8n
RC
DQ2
S0
DQ40
DQ24
SA1
CB0
VREF
SDA
A0
DQ17
DQ10
DQ57
A7
DQ37
DQ16
DQ50
DQ27
DQ31
DM2
DQS3
CKE0
2, 5, 8, 11, 14, 17, 20,GROUND
225, 228, 231, 234, 237210, 213, 216, 219, 222,169, 198, 201, 204, 207,154, 157, 160, 163, 166,139, 142, 145, 148, 151,124, 127, 130, 133, 136,109, 112, 115, 118, 121,94, 97, 100, 103, 106,79, 82, 85, 88, 91,41, 44, 47, 65,23, 26, 29, 32, 35, 38,
NC10
NC9NC8NC7NC6NC5NC4NC3NC2NC1
PWR2_SEL_OPT2PWR1_SEL_OPT2
VDD4VDD5VDD6VDD7VDD8VDD9VDD10VDD11
VDD1VDD2VDD3
VDDQ1
VDDQ11
VDDQ8
VDDQ2VDDQ3
VDDQ9
VDDQ6VDDQ7
VDDQ5
VDDQ10
VDDQ4
IN
BIBIBIBIBIBIBIBIBIBIBI
BIBI
BIBIBIBIBI
OUT
IN
BI
IN
BIIN
IN
ININININININ
ININ
ININ
ININ
IN
IN
IN
BI
BI
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor Freescale Confidential Proprietary 35
Fan-Out Schematics
MEMORY CONNECTOR #2
9D29D2
1A79D2
1A2
1A21A21A21A2
1A2
1D61D6
1D6
1D61D6
1D6
1D69C2
1D69C21D69C2
1A5 9A51A5 9A5
1B5 9B51B5 9B5
1B5 9B5
1A5 9A51A5 9A5
1B5 9B5
1A5 9A5
1A5 9A51A5 9A5
1A5 9A5
1B5 9A51A5 9A51A5 9A51A5 9A5
1B5 9B5
1A5 9A5
1C69B2
1C69B2
1B69A2
1B69A2
1B2 9C6
1D69D2
9D21D1
Tue Jul 31
83
I2C_SDAI2C_SCL
MVREF
MCK5_B
MCK3_BMCK4MCK4_BMCK5
MCK3
MCKE2MCKE3
MODT3
MCS2_BMCS3_B
MODT2
MCAS_B
MWE_BMRAS_B
MDQS3_BMDQS4
MDQS7MDQS6_B
MDQS8
MDQS2MDQS2_B
MDQS7_B
MDQS0_B
MDQS1_BMDQS1
MDQS0
MDQS6MDQS5_BMDQS5MDQS4_B
MDQS8_B
MDQS3
MA<00..15>
MBA<0..2>
MDM<0..8>
MECC_<0..7>
MDQ<00..63>
MAPAR_OUT
MAPAR_ERR_B
15
DDR2 DIMM
P2188
7057176196174173
63182616018058179177
7119054
74
4243
49161162167168
185
137
220
186
138
221
52171
125134146155202211223
164
34
212213113214014124253031
9
14314414915033343940152153
10
15815980818687199200205206
122
899095962082092142159899
123
107108217218226227110111116117
128
229230235236
1291213
7616152827373684
939210510411411346
19577
6819
192
55
18
19376
239240101
120119
238
1
73
48
183
CONN_240_DDR2_VERT_SPECIAL_1OF2
232
45
14
1213
111009
0708
0605
0304
020100
210
876
45
3210
76
45
3210
63626160
5859
5756
5455
535251
4950
4847
4546
444342
4041
393837
3536
3433
3132
302928
2627
2524
2223
212019
1718
1615
1314
121110
0809
0706050403020100
CONN_240_DDR2_VERT_SPECIAL_1OF2
P1102
233
126135147156165203212224
5066
53
189197
59646769172178184187
51
191194
5662727578170175181
GVDDGVDD
8536_FAN_OUT_SCHEMATIC
X1DRAWING
ENGINEER NAMEENGINEER:
5 642 3
75 642 3
REV
DATE
7
PROJECT:
DQS0n
(DQS16)(DQS17)
(ECC0)(ECC1)(ECC2)(ECC3)
(AP)
(ECC4)(ECC5)(ECC6)(ECC7)
NC
Normally NC on DDR2
165, 203, 212, 224233
102
Not Supported126, 135, 147, 156
(DQS9)(DQS10)(DQS11)(DQS12)(DQS13)(DQS14)(DQS15)
DM8
DQ12
DQ61
DQ48
DQ60
DM5DM4
DQ33
DQ62
DQ18
CK_L0
DQ54
DQ9
A15
DQ51
S1
BA2
CK_L2
DQ36
VDDSPD
DM3
DQS3nDQS4
DM0
DQ53
DQ55
DQS7
ODT0
DQ47
A12
DQ39
DQ14
DQ58
A5
DQ46
RAS
DQ26
DQ23
DQ1
DQ52
DQ45
A11
DQS6n
DQS8
CB5
DQ30
CKE1
DQ43
DQ28
A3A4
CB6
A2
A10
DQ15
DQ38
DQ56
DQ42
CB1
DQ25
DQ41
DM1
RESET
A14
SCL
DQ20
A13
DQS2
DQ3
A8A9
DQ6
DQ44
DQ32
DQ7
WE
DQ4
DM7
A6
CK_H2
CB2
CB4CB3
CK_H0
A1
DQ29
DQ8
DQ63
DQS2n
CAS
CB7
DQ5
DQ0
BA0
SA0
DQ34
DQS7n
DQ22DQ21
DQ13
DQ11
DQ35
DQ49
BA1
DM6
DQ19
CK_L1
DQ59
ODT1
CK_H1
PWR1_SEL_OPT1PWR2_SEL_OPT1
SA2
DQS1nDQS1
DQS0
DQS6DQS5nDQS5
DQS4n
DQS8n
RC
DQ2
S0
DQ40
DQ24
SA1
CB0
VREF
SDA
A0
DQ17
DQ10
DQ57
A7
DQ37
DQ16
DQ50
DQ27
DQ31
DM2
DQS3
CKE0
2, 5, 8, 11, 14, 17, 20,GROUND
225, 228, 231, 234, 237210, 213, 216, 219, 222,169, 198, 201, 204, 207,154, 157, 160, 163, 166,139, 142, 145, 148, 151,124, 127, 130, 133, 136,109, 112, 115, 118, 121,94, 97, 100, 103, 106,79, 82, 85, 88, 91,41, 44, 47, 65,23, 26, 29, 32, 35, 38,
NC10
NC9NC8NC7NC6NC5NC4NC3NC2NC1
PWR2_SEL_OPT2PWR1_SEL_OPT2
VDD4VDD5VDD6VDD7VDD8VDD9VDD10VDD11
VDD1VDD2VDD3
VDDQ1
VDDQ11
VDDQ8
VDDQ2VDDQ3
VDDQ9
VDDQ6VDDQ7
VDDQ5
VDDQ10
VDDQ4
BIBIBI
BIBI
BIBIBI
BIBI
BI
BIBI
BIBI
BIBIBI
IN
OUT
BI
IN
IN
INININ
ININ
ININ
ININ
ININININININ
IN
IN
BI
BI
BI
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
36 Freescale Confidential Proprietary Freescale Semiconductor
Fan-Out Schematics
X4 LANE
X4 LANE
X4 LANE
X4 LANE
PCI EXPRESS CONNECTOR
2B7
2B72B7
2B72B7
2B72B7
2B72B7
2B72B7
2B72B7
2B72A7
2B22B2
2B22B2
2B22B2
2B22B2
2B2
2B7
2B2
2B2
2B22B2
2B2
2B22A2
B11 B9
A8
A7
A6
A5B6
B5
A13
A14
B81
B48
B31
B17
A1
B54
B50
B45
B41
B37
B33
B27
B23
B78
B74
B70
B66
B62
B58
B19
B14
B55
B51
B46
B42
B38
B34
B28
B24
B79
B75
B71
B67
B63
B59
B20
B15
A11
A56
A52
A47
A43
A39
A35
A29
A25
A80
A76
A72
A68
A64
A60
A21
A16
A57
A53
A48
A44
A40
A36
A30
A26
A81
A77
A73
A69
A65
A61
A22
A17
B10
J1
8536_FAN_OUT_SCHEMATIC
pciexpress_conn_x16
SD1_TX7
SD1_TX6_BSD1_TX6
SD1_TX5_BSD1_TX5
SD1_TX4_BSD1_TX4
SD1_TX3_BSD1_TX3
SD1_TX2_BSD1_TX2
SD1_TX1_BSD1_TX1
SD1_TX0_BSD1_TX0
SD1_RX7_BSD1_RX7
SD1_RX6_BSD1_RX6
SD1_RX5_BSD1_RX5
SD1_RX4_BSD1_RX4
SD1_RX3_B
SD1_TX7_B
SD1_RX1
SD1_RX3
SD1_RX2_BSD1_RX2
SD1_RX1_B
SD1_RX0_BSD1_RX0
DRAWENGINEER NAME
ENGINEER:
5 642 3
75 642 3
7
PROJECT:
ININ
ININ
OUTOUT
OUTOUT
OUTOUT
OUTOUT
OUTOUT
OUTOUT
OUTOUT
OUTOUT
ININ
ININ
ININ
ININ
ININ
ININ
A27 A28 B29 A31 B32B22 A23 A24 B25 B26B16 B18 A18 A20 B21B4 A4 B7 A12 B13 A15
GND
B1 B2 B3 A2 A3
B80 A82
A75 B76 B77 A78 A79A70 A71 B72 B73 A74
B65 A66 A67 B68 B69
B60 B61 A62 A63 B64A55 B56 B57 A58 A59A49 A51 B52 B53 A54
B8 A9 A10
+12V
+3.3V
B3 B12 B30 A32 A33
NC
A50 B82 A19
B44 A45 A46 B47 B49B39 B40 A41 A42 B43A34 B35 B36 A37 A38
PETn10
PETn8
PERp13
PETn7
PERn1
PERp6
PERp0
TRST
PERp14
PETn3
TDI
PERn3
PERn6
PERn4
PETp7
PERn7
TCK
TMS
PERn5
PERp4
PRSNT1
PERn0
PERp7
PERp8
PRSNT2_1
PERp10
PERn8
PERp9PETp9
PETp8
P3.3V_AUX
PERp12
PETn9
WAKE_N
SMDAT
PERp1
PETn5
PERn9
PRSNT2_3
REFCLKN
PETn0
SMCLK
PERp5
PERn11
PETn4
TDO
PERn10
PERn12
PERp11
PETn2
REFCLKP
PERn13
PETn1
PETn14
PETn15
PERp15
PETn12
PERn14
PETn11
PERST
PERn15
PERp3
PETn13
PRSNT2_2
PETp6
PETp5
PETp4
PETp3
PETp2
PETp1
PETp0
PETp15
PETp14
PETp13
PETp12
PETp11
PETp10
PERn2
PERp2
PRSNT2_4
PETn6
A S
trategy for R
ou
ting th
e MP
C8536E
in a S
ix-Layer P
CB
,R
ev. 0
Freescale Sem
iconductorFreescale C
onfidential Proprietary
37
Fan
-Ou
t Sch
ematics
PCI 32-BIT CONNECTOR PCI 32-BIT CONNECTORPCI 32-BIT CONNECTOR
12
3C612B112B33C612B112B3
3C612B112B33B612B112B33C612B112B33C612B112B33B612B112B3
3B6 12C3 12C8
3B6 12B8 12C33B6 12B8 12C33B6 12B8 12C33B6 12B3 12B8
3B6 12C3 12C6
3B6 12C3 12C63B6 12B6 12C33B6 12B6 12C33B6 12B3 12B6
3D412D112D3
3D412D112D5
3B6 12C6 12C8
3B6 12B8 12C63B6 12B6 12B83B6 12B6 12B83B6 12B6 12B8
3C612B112B6
3C6 3C63C6
3C6
3C612B112B6
3B612B112B63C612B112B6
3B612B112B6
3C612B112B6
3C612B112B6
3D412D312D5
3C612B312B6
3C612B312B63C612B312B6
3C612B312B6
3B612B312B6
3C612B312B63B612B312B6
3C63C6
Tue Jul 31 12:15:30 2007
PCI1_SERR_BPCI1_PERR_B
PCI1_STOP_BPCI1_TRDY_BPCI1_IRDY_BPCI1_DEVSEL_BPCI1_FRAME_B
PCI1_PAR
PCI1_C_BE0_BPCI1_C_BE1_BPCI1_C_BE2_BPCI1_C_BE3_B
PCI1_PAR
PCI1_C_BE0_BPCI1_C_BE1_BPCI1_C_BE2_BPCI1_C_BE3_B
PCI1_AD<31..00>PCI1_AD<31..00>
PCI1_PAR
PCI1_C_BE0_BPCI1_C_BE1_BPCI1_C_BE2_BPCI1_C_BE3_B
B9
B60
14
B59
B19
A59
A16
A10
A1A36 A3
B4A4
B2
A38
B42
A40A41
A15
A60
B18
B11B9
B40
A43
B14B10A19A14
A11
A9
B49
B39
B35
B8A7B7A6
A26
A17
A34B37
B16
B26B33B44A52
A49B52B53A54B55A55
B20A20
B56
B21A22B23A23B24A25B27A28B29A29
A57
B30A31B32A32A44B45A46B47A47B48
B58A58
B60
J7
B59
B19
A59
A16
A10
A1A36 A3
B4A4
B2
A38
B42
A40A41
A15
A60
B18
B11B9
B40
A43
B14B10A19A14
A11
A9
B49
B39
B35
B8A7B7A6
A26
A17
A34B37
B16
B26B33B44A52
A49B52B53A54B55A55
B20A20
B56
B21A22B23A23B24A25B27A28B29A29
A57
B30A31B32A32A44B45A46B47A47B48
B58A58
J6
B59
B19
A59
A16
A10
A1A36 A3
B4A4
B2
A38
B42
A40A41
A15
A60
B18
B11
B40
A43
B14B10A19A14
A11
A9
B49
B39
B35
B8A7B7A6
A26
A17
A34B37
B16
B26B33B44A52
A49B52B53A54B55A55
B20A20
B56
B21A22B23A23B24A25B27A28B29A29
A57
B30A31B32A32A44B45A46B47A47B48
B58A58
B60
J5
5V: 145154-1
PCICONN_3V_32BIT_BLOCK
3V: 145154-1
PCI1_STOP_B
5V: 145154-1
PCICONN_3V_32BIT_BLOCK
PCI1_GNT1_BPCI1_REQ2_BPCI1_GNT2_B
PCI1_REQ1_B
PCI1_PERR_B
VCC_3.3
3V: 145154-1
PCICONN_3V_32BIT_BLOCK
5V: 145154-1
3031
292827
2526
2423
2122
201918
1617
151413
1112
10090807060504
0203
0100
VCC_3.3
3031
292827
2526
2423
2122
201918
1617
151413
1112
10090807060504
0203
0100
PCI1_TRDY_BPCI1_IRDY_B
PCI1_FRAME_B
PCI1_SERR_B
PCI1_DEVSEL_B
PCI1_AD<31..00>
PCI1_DEVSEL_B
PCI1_PERR_BPCI1_SERR_B
PCI1_STOP_B
PCI1_FRAME_B
PCI1_IRDY_BPCI1_TRDY_B
PCI1_REQ0_BPCI1_GNT0_B
0001
0302
04050607080910
1211
131415
1716
181920
2221
2324
2625
272829
3130
3V: 145154-1
VCC_3.3
X1
8536_FAN_OUT_SCHEMATIC
DRAWINGENGINEER NAME
ENGINEER:
5 642 31
A
B
C
D
7 85 642 31
OFPAGE:
8
REV
DATE:
7
PROJECT:
BI
B22 B28 B34 B38 B46B57
B1
+5V
A53 B25 B31 B36 B41B43 B54
NC
B10 B14
A2
B6 B61 B62A5 A8 A61 A62 B5
A9 A11 A14 A19
A21 A27 A33 A39 A45
+12V
VIO: 3.3V or 5V
-12V
A12 A13 B12 B13 A18
GND
A24 A30 A35 A37 A42A48 A56 B3 B15 B17
+3.3V
NC5NC6
NC4NC3
NC2
NC1
ACK64
AD21
AD20
AD2
C_BE3
PRSNT2
AD3
DEVSEL
AD5
AD4
C_BE2
AD26
AD17
AD16
REQ64
AD18
AD19
AD10
PERR
AD12
AD11
LOCK
AD13
CLK
TDO
TDI
TRST
TMS
TCK
AD9
C_BE1
AD15
SERR
AD28
STOP
AD6
AD7
SDONE
AD8
C_BE0
M66EN
AD23
IDSEL
INTA
AD30
AD25
AD27
FRAME
SBO
INTD
RST
IRDY
TRDY
PRSNT1
PAR
AD22
AD24
AD31
REQ
INTC
INTB
GNT
AD29
AD1
AD0
AD14
OUTIN
BI
BIBI
BIBI
BIBI
IN
BIBIBIBI
BI
B22 B28 B34 B38 B46B57
B1
+5V
A53 B25 B31 B36 B41B43 B54
NC
B10 B14
A2
B6 B61 B62A5 A8 A61 A62 B5
A9 A11 A14 A19
A21 A27 A33 A39 A45
+12V
VIO: 3.3V or 5V
-12V
A12 A13 B12 B13 A18
GND
A24 A30 A35 A37 A42A48 A56 B3 B15 B17
+3.3V
NC5NC6
NC4NC3
NC2
NC1
ACK64
AD21
AD20
AD2
C_BE3
PRSNT2
AD3
DEVSEL
AD5
AD4
C_BE2
AD26
AD17
AD16
REQ64
AD18
AD19
AD10
PERR
AD12
AD11
LOCK
AD13
CLK
TDO
TDI
TRST
TMS
TCK
AD9
C_BE1
AD15
SERR
AD28
STOP
AD6
AD7
SDONE
AD8
C_BE0
M66EN
AD23
IDSEL
INTA
AD30
AD25
AD27
FRAME
SBO
INTD
RST
IRDY
TRDY
PRSNT1
PAR
AD22
AD24
AD31
REQ
INTC
INTB
GNT
AD29
AD1
AD0
AD14
OUTIN
BI
BIBI
BIBI
BIBI
IN
BIBIBIBI
BIBIBIBI
IN
OUTIN
BIBI
BIBIBIBIBI
BI
B22 B28 B34 B38 B46B57
B1
+5V
A53 B25 B31 B36 B41B43 B54
NC
B10 B14
A2
B6 B61 B62A5 A8 A61 A62 B5
A9 A11 A14 A19
A21 A27 A33 A39 A45
+12V
VIO: 3.3V or 5V
-12V
A12 A13 B12 B13 A18
GND
A24 A30 A35 A37 A42A48 A56 B3 B15 B17
+3.3V
NC5NC6
NC4NC3
NC2
NC1
ACK64
AD21
AD20
AD2
C_BE3
PRSNT2
AD3
DEVSEL
AD5
AD4
C_BE2
AD26
AD17
AD16
REQ64
AD18
AD19
AD10
PERR
AD12
AD11
LOCK
AD13
CLK
TDO
TDI
TRST
TMS
TCK
AD9
C_BE1
AD15
SERR
AD28
STOP
AD6
AD7
SDONE
AD8
C_BE0
M66EN
AD23
IDSEL
INTA
AD30
AD25
AD27
FRAME
SBO
INTD
RST
IRDY
TRDY
PRSNT1
PAR
AD22
AD24
AD31
REQ
INTC
INTB
GNT
AD29
AD1
AD0
AD14
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
38 Freescale Confidential Proprietary Freescale Semiconductor
Fan-Out Schematics
LOCAL BUS LATCHES
4B2
4C2
4B6
4B6
T2P2M2K2H2F2D2B2
R2N2L2J2G2E2C2A2
J3
T6R6P6N6M6L6K6J6
T4T3
J4 T5R5P5N5M5L5K5J5
T1R1P1N1M1L1K1J1
A3
H6G6F6E6D6C6B6A6
H4H3
A4 H5G5F5E5D5C5B5A5
H1G1F1E1D1C1B1A1
1U508
T2P2M2K2H2F2D2B2
R2N2L2J2G2E2C2A2
J3
T6R6P6N6M6L6K6J6
T4T3
J4 T5R5P5N5M5L5K5J5
T1R1P1N1M1L1K1J1
A3
H6G6F6E6D6C6B6A6
H4H3
A4 H5G5F5E5D5C5B5A5
H1G1F1E1D1C1B1A1
1U507
74ALVCH32973KR_LFBGA96
313029
01
0908
070605040302
LAD<00..31>
00
12
8536_FAN_OUT_SCH
23
LA<27..31>
LALE
LBCTL
1514
282930
74ALVCH32973KR_LFBGA96
16
2425
1011
13
2728
17181920
31
2122
2627
ENGINEER NAMEENGINEER:
5 642 3
75 642 3
PROJECT:
IN
IN
IN
IN
GND
B3 B4
R3 R4N3 N4M3 M4K3 K4G3 G4E3 E4D3 D4
pwr pinssee map for
REV 4OCT 23 2002
2B5
2B6
2B7
2B8
2Q1
2Q2
2Q3
2Q4
2A1
2A5
2A4
2A3
2A2
2A8
2A7
2A6
D8
D7
D6
D5
D4
D3
1Q4
1A1
1B4
1B5
1B6
1B7
2TOE
2LE
2DIR
2LOE
1A6
1A7
1A8
1A2
1TOE
1A3
1A4
1A5 1Q5
1Q6
1Q7
1Q8
2Q5
1B1
1B2
1B3
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
1Q2
1Q3
1Q1
1B8
2B1
2B2
2B3
2B4
D1
D2
2Q6
2Q7
2Q8
1LE
1DIR
1LOE
GND
B3 B4
R3 R4N3 N4M3 M4K3 K4G3 G4E3 E4D3 D4
pwr pinssee map for
REV 4OCT 23 2002
2B5
2B6
2B7
2B8
2Q1
2Q2
2Q3
2Q4
2A1
2A5
2A4
2A3
2A2
2A8
2A7
2A6
D8
D7
D6
D5
D4
D3
1Q4
1A1
1B4
1B5
1B6
1B7
2TOE
2LE
2DIR
2LOE
1A6
1A7
1A8
1A2
1TOE
1A3
1A4
1A5 1Q5
1Q6
1Q7
1Q8
2Q5
1B1
1B2
1B3
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
1Q2
1Q3
1Q1
1B8
2B1
2B2
2B3
2B4
D1
D2
2Q6
2Q7
2Q8
1LE
1DIR
1LOE
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor Freescale Confidential Proprietary 39
Fan-Out Schematics
GBE PHY 1 OF 3 GBE PHY 3 OF 3GBE PHY 2 OF 3
5C3
5B6
5C6
5C35C3
5B2
5C25C25C25C2
5B25B25B25B2
5C65C6
5C65C65C6
5B6
5B6
5B6
5B65B6
5C3
5B2
EC_MDIO
TSEC3_GTX_CLK
TSEC3_RXD3
TSEC1_RX_CLKTSEC1_RX_DV
TSEC1_GTX_CLK
TSEC1_RXD3TSEC1_RXD2TSEC1_RXD1TSEC1_RXD0
TSEC1_TXD0TSEC1_TXD1TSEC1_TXD2
C1B1
VSC8244HG
vsc8244_1of3_ports_pbga260
U6
F16
E18
E17
E16
D16
C18
C17
C16
H16
F17
A2
G3
H17
F18
B2
F3
H18
G16
C3
E3
J17
G17
C4
D3
J18
G18
C5
A1
R18
R13
R10
R8
T3
B18
B14
B10
B6
B17
B13
B9
B5
B16
B12
B8
B4
B15
B11
B7
B3
A18
A14
A10
A6
A17
A13
A9
A5
A16
A12
A8
A4
A15
A11
A7
A3
vsc8244_2of3_macs_pbga260
VSC8244HG
TSEC1_TXD3
U6
C2C6C7
C15
D2D1E1E2
E15
G1F1G2
H2
J1J2K1L1L2M1
N1M2
N2P1R1
T1
R2
T2U1U2V1
V15
T11
T7
V2
U15
U11
U7
U3
T16
T12
V8
V4
U16
U12
U8
U4
V16
V12
T8
T4
T15
V11
V7
V3
V17
U13
T9
T5
U17
V13
U9
U5
T18
T14
V10
V6
U18
U14
U10
U6
V18
V14
T10
T6
T17
T13
V9
V5
TSEC3_RX_CLKTSEC3_RX_DV
TSEC3_RXD0TSEC3_RXD1TSEC3_RXD2
TSEC3_TXD0
TSEC3_TX_EN
TSEC3_TXD1
TSEC3_TXD3TSEC3_TXD2
VSC8244HGEC_MDCvsc8244_3of3_sys_pwr_pbga260
U6
R17
M18
L17
L18
P16
P18
N16
N17
N18
P17
C10
C9
M16
M17
K17
J16
K16
K18
L16
D14
D15
E4
F4
H3
J3
M3
N3
R3
C8
F15
G15
L4
R16
D4
D5
D6
D9
D10
D11
D12
D13
K15
L15
H4
H15
J4
J15
P4
R4
R14
R15
R5
R6
R7
R9
R11
R12
C11
G8
G9
G10
G11
G12
H7
H8
H9
H10
H11
C12
H12
J7
J8
J9
J10
J11
J12
K2
K3
K4
C13
K7
K8
K9
K10
K11
K12
L3
L7
L8
L9
C14
L10
L11
L12
M4
N4
N15
P2
P3
P15
D7
D8
F2
G4
G7
M7 M8 M9
M10
M11
M12
M15
D17
D18
8536_FAN_OUT_SCHEMAT
H1
TSEC1_TX_EN
ENGINEER NAMEENGINEER:
5 642 31
75 642 31
7
PROJECT:
0
31
2
TXVNA_1
TXVPD_0
TXVPC_1
TXVNC_0
TXVPC_0
TXVNC_1
TXVND_1
TXVNB_0
TXVPB_0
TXVPD_1
MICRO_REF
TXREF_3
TXREF_2
TXVPC_3
TXVNB_3
TXVPB_3
TXVNA_3
TXVPA_3
TXVND_2
TXVPD_2
TXVNC_2
TXVPC_2
TXVNB_2
TXVPB_2
TXVNA_2
TXVPA_2
TXVPD_3
TXVND_0
TXVPA_1
TXVND_3
TXVNC_3
TXVNB_1
TXREF_0
CMODE7
CMODE6
CMODE5
CMODE4
CMODE3
CMODE2
CMODE1
CMODE0
LED1_3
LED2_3
LED3_3
LED4_3
LED0_2
LED1_2
LED2_2
LED3_2
LED4_2
LED0_1
LED1_1
LED2_1
LED3_1
LED4_1
LED0_0
LED1_0
LED2_0
LED3_0
LED4_0
LED0_3
TXVNA_0
TXVPA_0
TXVPB_1
TXREF_1
ININ
IN
IN
IN
IN
OUTOUTOUTOUT
OUTOUT
NC33NC32NC31NC30NC28
NC29NC27NC26NC25NC23NC24
NC21NC20NC19NC18NC17
NC22
NC01NC02NC03NC04NC05NC06
NC07NC08NC09NC10NC11
NC12NC13
NC16NC15NC14
RX_CTL_3
RXD_2_0
RXD_1_3
RXD_2_3
RXD_0_3
RX_CTL_1
RXD_0_0
TX_CLK_1
TX_CLK_2
RX_CTL_0
RX_CLK_3
RX_CLK_2
TX_CLK_3
RX_CTL_2
TXD_1_0
TXD_2_0
TXD_0_3
TXD_0_0
TXD_3_3
RX_CLK_1
TXD_1_3
RX_CLK_0
TX_CTL_2
TXD_1_1
TX_CTL_1
TX_CTL_0
TXD_0_1
TXD_2_3
TXD_3_1
TX_CTL_3
TXD_2_1
RXD_3_2
RXD_1_2
RXD_3_0
TXD_0_2
TX_CLK_0
RXD_1_1
RXD_3_3
TXD_2_2
TXD_3_2
RXD_0_2
RXD_0_1
RXD_3_1
TXD_1_2
RXD_2_2
RXD_2_1
RXD_1_0
TXD_3_0
ININININ
IN
IN
OUTOUT
OUTOUT
OUTOUT
BIIN
See spec.
NC
VSS_35
VSS_34
VSS_33
VSS_32
VSS_31
VSS_30
VSS_22
VSS_21
VSS_20
VSS_19
MDC
MDIO
VDDIO_MAC_2
VDD33_11
VDD12_5
VDD12_6
VDD12_7
TRST
VDD12_8
VDD12_9
VSS_16
VSS_15
VSS_14
VSS_13
VSSIO_3
VSSIO_2
VSSIO_1
VSS_48
EECLK
SOFT_RESET
VDDIO_MAC_1
VDDDIG_2
VSS_4
VSS_3
VSS_2
VSS_1
VDDDIG_1
VDDDIG_8
VSS_47
VSS_46
VSS_45
VSS_44
MDINT_0
MDINT_1
MDINT_2
MDINT_3
VDDDIG_3
VDDDIG_4
VDDDIG_7
VDDDIG_5
VDDDIG_6
XTAL2
VSS_26
VSS_25
VSS_24
VSS_23
CLK125MICRO
TMS
TDO
TDI
VSS_39
VSS_38
VSS_37
VSS_36
VDD33_5
VDD33_4
VDD33_3
REF_REXT
TCK
REF_FILT
VSS_29
VSS_28
VSS_27
VDD33_1
VSS_12
VSS_11
VSS_10
VSS_9
VDD33_10
VDD33_9
VDD33_8
RESET
VDD33_13
VDD33_12
VSSIO_7
VSSIO_6
VSSIO_5
VSSIO_4
VDD33_2
VDD12_2
VDD12_3
VDD12_4
VSS_8
VSS_7
VSS_6
VSS_5
VDDIO_MAC_3
VDDIO_MAC_4
VDDIO_MAC_5
VDDIO_MAC_6
VDD_MICRO
VDD_CTL
VDD12_1
XTAL1
CLK125MAC
EEDAT
VSS_43
VSS_42
VSS_41
VSS_40
VSS_18
VSS_17
VDD33_7
VDD33_6
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
40 Freescale Confidential Proprietary Freescale Semiconductor
Current Delivery in the BGA Field
9 Current Delivery in the BGA FieldThe MPC8536E comes in a 1 mm pitch, 783 BGA package arranged as a 28 × 28 array (with pin A1 missing). The BGA pads and vias usually have the physical parameters listed Table 8.
Keep the following points in mind while reading this section:
• The remainder of this section is based on the padstack dimensions in Table 8. If a different padstack is used, most or all of the numbers derived probably need to be recalculated.
• It is assumed that each BGA connection carries current equally, no matter its proximity to the power supply and/or processor internal power pads. In reality, the current is nonuniformly distributed due to internal BGA-to-die substrate connections and other factors. There are no guaranteeable distributions among the power pins.
All comments in this section about power planes apply equally to the return ground. Multilayer PCBs often have multiple ground planes, so this restriction is occasionally overlooked; however, the ground return path requirements are exactly equal to the power source path requirements.
In addition to bypass capacitor placement, the designer must also consider the wholesale delivery of power to the VDD pins. On most PCBs, the power plane is not actually solid, but is perforated by numerous vias. This is illustrated in Figure 21, where the wide plane is actually only as wide as its narrowest point.
Figure 21. Restricted Current Flow
Table 8. MPC8536E Escape Dimensions
Dimension Size Notes
Drill diameter 10 mils Via drill
Finished hole size (FHS) 7–7.5 mils After plating
Pad 19 mils
Anti-pad 28 mils Clearance from via pads to adjacent plane area-fills
Thermal relief 33 mils2
Via keepout 23 mils As above, but for traces on signal (inner) planes
W=7 Units
W=3 * 1U
PSU
CPU
Power Plane Area-Fill
Effective Width =
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor Freescale Confidential Proprietary 41
Current Delivery in the BGA Field
For many applications, the effect of the vias passing through the power plane on the flow of current is insignificant. However, as the power reaches the outer periphery of the MPC8536E, it must flow through the outer array of signal BGA vias. While some BGA pads may not need vias (outer BGA pads may be able to route out on the top layers); in most cases the number of interfering vias ranges from 8 to 11.
For many layouts, the outer one or two BGA pads do not require vias as these signals are usually “escaped” on the top layer of the PCB. Delivering power properly to the power pins requires planning the flow of current around these vias, or more properly, the antivias or antipads that surround the via and cause a hole on the power plane layer. When coupled with a 1-mm spacing, the cross section of the PCB typically resembles that shown in Figure 6.
The anti-pad is larger than the spacing between the via barrels, which in effect reduces the width and capacity of the trace. In effect, the power plane is not a solid plane but a parallel array of traces with one of the following widths:
• 11.3 mils, when planes must be isolated from both vias
• 19.3 mils, when planes connect to one of the vias
The standard formulae to determine the limits of the copper trace are described in the IPC-2221A standard and are given by:
Eqn. 1
Eqn. 2
Using these formulae, and using an 11-mil trace as a standard (rounded down from the actual 11.3-mil max trace width), for various layout rules the amount of current that can be safely carried, assuming a maximum temperature rise of 20°C, is shown in Table 9.
9.1 Via Current CapacityUnless the power is delivered on the top plane and attaches directly to the BGA pad of the processor (which as noted is fairly difficult to accomplish), power is delivered from one or more PCB planes to the processor through vias. Given the padstack parameters in Table 8 and the number of vias allocated, the next step to
Table 9. Current-Carrying Capacity per Standard IPC2221A
Location Copper Plating(oz.)
11-mil Trace(A)
Outer 0.5 0.777
1.0 1.285
1.5 1.730
2.0 2.130
Inner 0.5 0.390
1.0 0.582
1.5 0.865
2.0 1.065
I Trace, Outer( ) 0.048 maxTempRise( )0.44× viaPlating viaDiameter π××( )0.725×=
I Trace, Inner( ) 0.024 maxTempRise( )0.44× viaPlating viaDiameter π×¥( )0.725×=
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
42 Freescale Confidential Proprietary Freescale Semiconductor
Current Delivery in the BGA Field
ensure a quality PDS is to evaluate the individual and aggregate via current capacity using the following formula:
Eqn. 3
Table 10 shows a few via current capacities for given PCB process parameters.
At 1.609 A/via, we have a maximum current capacity of 22.5 A for VDD_CORE (14 vias * 1.609), and 16 A for VDD_PLAT (10 * 1.609).
9.2 Alternate Plane Current CapacityResearch performed by Johannes Adam of Flomerics as preparatory work for a revision to one of the rules of the IPC2221 standard (specifically, design rule 2152), found that the formula for outer traces was based on materials and assumptions no longer prevalent. Additionally, he discovered that the 50 percent derating factor used for inner traces is wholly arbitrary and should be approximately 5 percent. In particular, thermal conduction to adjacent traces and power planes was found to be vastly more important than conduction to free space. Refer to Section 10, “References,” for details on this paper and associated historical data.
At the time of publication, the IPC2221 has not been updated based on these findings, so the designer can either follow the published standards and accept overly conservative numbers or incorporate the pending changes. Freescale cannot recommend one course over the other and advises designers to consult the original source documentation and decide for themselves. Examining the IEEE paper, “case 5” shows an outer trace of variable width over a 35 um (1 oz. copper) plane. This correlates nicely with an external power connection residing over an inner ground plane immediately adjacent to it. Such a plane is desirable not only for power purposes but for routing differential pairs such as those on the SerDes or DDR interfaces. Extracting the data for a 0.3 mm trace (~11 mils), and applying a curve fitting process to the data produces the following formula, which is represented in Figure 22:
Eqn. 4
Table 10. Via Capacity
maxTempRise(°C)
viaPlating(mil)
viaDiameter(mil)
IVIA(A)
Notes
10 1 10 1.609 Standard
10 1 11 1.724 —
10 1 15 2.159 —
10 1.5 10 2.159 —
20 1 10 2.183 —
IVIA 0.048 maxTempRise( )0.44× viaPlating viaDiameter π××( )0.725×=
T trace( ) 19.473 3.228IMAX 4.469IMAX2 0.385IMAX3+ + +=
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor Freescale Confidential Proprietary 43
Current Delivery in the BGA Field
Figure 22. Extrapolated Current Flow
CAUTIONThis curve is valid only for the 0.3 mm trace. The IPC standard will likely include a more complicated curve equation that accepts both current and trace width as a parameter.
Note that the Y-axis is the total trace temperature. Because we are concerned with a maximum 20°C rise, the Y-axis starts at 20 as the ambient temperature is also assumed to be 20°C. The crossover point of 40°C occurs when I = 1.711 A. Using this new data, Table 9 can be updated as shown in Table 11:
Table 11. Current-Carrying Capacity Extrapolated from Adams
LocationCopper Plating
(oz.)A/11-mil Trace
(A)
Outer 0.5 1.210
1.0 1.711
1.5 2.420
2.0 3.422
0
10
20
30
40
50
60
70
80
90
0 0.5 1 1.5 2 2.5 3 3.5
Current, A
Tra
ce T
emp
, deg
C
0.3 mm (ADAMS)
0.3 mm (curve fit)
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
44 Freescale Confidential Proprietary Freescale Semiconductor
Current Delivery in the BGA Field
The IEEE paper included in the references explains why the classic IPC-275/IPC2221A values for inner current layers are extremely misleading. IPC-2152 is not published at the time of this application note.
Inner 0.5 1.149
1.0 1.625
1.5 2.299
2.0 3.251
Table 11. Current-Carrying Capacity Extrapolated from Adams (continued)
LocationCopper Plating
(oz.)A/11-mil Trace
(A)
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor Freescale Confidential Proprietary 45
References
10 ReferencesTable 12 lists useful resources for further reading.
Table 12. References
Document Source
IPC Standards:IPC-D-275IPC-2221AIPC-2152
www.ipc.org
New Correlations Between Electrical Current and Temperature Rise in PCB TracesJohannes Adam,Flomerics Ltd.
20th IEEE SEMI-THERM Symposium
0-7803-8363-X/04/$20.00 ©2004 IEEE
www.flomerics.com/flotherm/technical_papers/t341.pdf
Martin Tarr, University of Bolton www.ami.ac.uk/courses/ami4817_dti/u02/pdf/meah0221.pdf
Decoupling Capacitors, a Designer’s Roadmap to Optimal Decoupling Networks for Integrated Circuits(CSC240_MUCCIOLI)Freescale Semiconductor
http://www.freescale.com/files/ftf_2005/doc/reports_presentations/CSC240_MUCCIOLI.pdf
Interactive trace-width calculator http://circuitcalculator.com/wordpress/2006/01/31/pcb-trace-width-calculator
DC Line Resistance and Current Carrying CapacityMerix Inc.
http://www.merix.com/technology.php?section=processes&page=technology/_processes.html
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
46 Freescale Confidential Proprietary Freescale Semiconductor
Revision History
11 Revision HistoryTable 13 provides a revision history for this application note.
Table 13. Document Revision History
Rev.Number
Date Description
0 10/07 Initial release.
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor Freescale Confidential Proprietary 47
Revision History
Freescale Confidential Proprietary
Document Number: AN3444Rev. 010/2007
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