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Int. J. Electron. Commun. (AEÜ) 66 (2012) 884– 891

Contents lists available at SciVerse ScienceDirect

International Journal of Electronics andCommunications (AEÜ)

j our na l ho mepage: www.elsev ier .de /a eue

simple CMOS-based inductor simulator and frequency performancemprovement techniques

hahram Minaeia,∗, Erkan Yuceb

Dogus University, Department of Electronics and Communications Engineering, Acibadem, Kadikoy 34722, Istanbul, TurkeyPamukkale University, Department of Electrical and Electronics Engineering, 20070 Kinikli, Denizli, Turkey

r t i c l e i n f o

rticle history:eceived 30 January 2011ccepted 12 March 2012

a b s t r a c t

In this paper, a new CMOS grounded positive tunable inductor simulator based on using two simpleCMOS transconductors and an inverting amplifier is presented. The introduced inductor simulator usesa grounded capacitor; accordingly, it is suitable for integrated circuit (IC) fabrication. In addition a CMOS

eywords:nductor simulatorMOSransconductornverting amplifier

circuit for realizing negative tunable resistor which can be used for parasitic cancellation in inductorsimulators and consequently enhancing their frequency performances is developed. A novel method forproviding high-frequency performance improvement of simulated inductors is also introduced. Simu-lation and experimental results are given to demonstrate the performance of the developed inductorsimulator and validity of the proposed frequency performance improvement method.

egative resistor

. Introduction

Inductor simulators find applications in many electronic circuitsuch as filters, oscillators, biasing and impedance matching. Theirlectronic tunability by means of a voltage or a current source, highuality factor and wide frequency range of operation make themttractive with respect to physical inductors. Many CMOS-basedctive inductors which are employed in different applications cane found in the literature [1–6]. For example, an RF band-pass filteresign based on CMOS active inductors has been proposed in [1].n active tunable inductor employing six CMOS transistor with oneontrol current has been presented in [2]. Alternatively, a widebandunable active inductor employing four CMOS transistors with aontrol current and a bias voltage has been reported in [3]. An activenductor with seven CMOS transistors and two control currents haslso been developed in [4]. In [5], a noise-cancelling CMOS basedctive inductor has been implemented. Apart from these, CMOSased active transformers have been proposed in [6]. It should beointed out that in all of the circuits in [1–6], current sources aresed to tune the simulated inductor.

On the other hand, many inductor simulators constructedith active building blocks such as operational amplifiers (OAs),

econd-generation current conveyors (CCIIs), current feedbackperational amplifiers (CFOAs), and external passive componentsave been reported [7–23]. However they employ a large number

∗ Corresponding author.E-mail addresses: sminaei@dogus.edu.tr, sminaei@yahoo.com (S. Minaei),

rkanyuce@yahoo.com (E. Yuce).

434-8411/$ – see front matter © 2012 Elsevier GmbH. All rights reserved.oi:10.1016/j.aeue.2012.03.005

© 2012 Elsevier GmbH. All rights reserved.

of transistors (typically more than 10) and consequently sufferfrom high power consumption and large area occupation in inte-grated circuits (ICs). It should be mentioned that the use of onlygrounded capacitors and external tunability of circuits withoutrequiring passive component matching conditions are importantissues in IC design [24–27].

In this paper, a simple inductor simulator employing only sixMOS transistors and a grounded capacitor is presented. The pro-posed inductor can be tuned electronically by control voltages.Additionally, a CMOS circuit with only four CMOS transistors forrealizing negative tunable resistor is developed which can beuseful in parasitic cancellation. A novel technique to improve high-frequency performance of inductor simulators is also developed. Anew method for providing high frequency performance improve-ment of simulated inductors is also introduced. The proposedcircuit ideas are validated by SPICE program and experimentaltests.

2. Proposed CMOS inductor simulator

Basic CMOS transconductors and inverting amplifiers are usedto realize a simple inductor simulator. A simple transconductorusing two CMOS transistors and two control voltages is depicted inFig. 1a. It is assumed that both of the transistors operate in satura-tion region satisfying the conditions VGS > VTN and VDS > VGS − VTN for

M2 (NMOS) besides VSG > |VTP| and VSD > VSG − |VTP| for M1 (PMOS)transistor. Here, VTN and VTP are the threshold voltages of the NMOSand PMOS transistors, respectively. Assuming square-law behaviorfor the current–voltage relationship of the MOS transistors in

S. Minaei, E. Yuce / Int. J. Electron. Commun. (AEÜ) 66 (2012) 884– 891 885

or and

sd

I

I

whc

I

T

a

a

a

IwHcbsakbi

V

H

bt

V

as

Zin(s) = sC

G3G4= sLeq (7)

Fig. 1. (a) Simple transconduct

aturation and ignoring channel-length modulation effect, therain current of the NMOS and PMOS transistors can be given as

D = kn

2(VGS − VTN)2 (1a)

D = kp

2(VSG − |VTP |)2 (1b)

here, kn = (W/L)n�nCox and kp = (W/L)p�pCox, W, L, �n, �p and Cox

ave their usual meanings. Using Eqs. (1a) and (1b), the outputurrent of the transconductor circuit of Fig. 1a is found as:

out = a0 + a1Vin + a2V2in (2)

he coefficients in (2) are found as

0 = kp

2(VA − |VTP |)2 − kn

2(VB − VTN)2 (3a)

1 = −kp(VA − |VTP |) − kn(VB − VTN) (3b)

2 = kp

2− kn

2(3c)

t should be mentioned that the CMOS transconductance of Fig. 1aith a single supply voltage was previously investigated in [28].owever, as shown in [28] to eliminate the nonlinearity of theircuit a balanced structure composed of four transistors shoulde used. Here, in the transconductor circuit of Fig. 1a with twoupply voltages, the current–voltage relationship in (2) can bepproximated as Iout ∼= a1Vin (linear transconductor) by settingp ∼= kn and VB ∼= VA + VTN − |VTP|. These conditions are assumed toe satisfied for the rest of the paper. In order to keep the transistors

n saturation region, the following constraints should be satisfied:

D1 + VTN ≥ Vin ≥ VD1 − |VTP | (4)

ere, VD1 is the drain voltage of transistors M1 and M2.A simple inverting amplifier employing two NMOS transistors

oth in saturation region is shown in Fig. 1b [29,30]. This circuit hashe following output voltage as a function of input voltage:

o = b0 + b1Vin (5)

(b) simple inverting amplifier.

The coefficients in (5) are computed by

b0 = VDD − VTN1 +√

kn2

kn1(VSS + VTN2) (6a)

b1 = −√

kn2

kn1(6b)

In (6a) and (6b), choosing VTN1 = VTN2, VSS = −VDD and kn1 = kn2results in b1 = −1 and b0 = 0, thus a linear inverting amplifier with-out DC offset is obtained. In order to keep the transistor M2 ofthe inverting amplifier of Fig. 1b in saturation region the condi-tion Vin < Vo + VTN2 should be satisfied. Note that the transistor M1always operates in saturation region since its drain and gate termi-nals are connected together.

Employing the linear transconductor and inverting amplifier ofFig. 1a and b, the introduced tunable simulated inductor is shownin Fig. 2. Equivalent input impedance of the circuit in Fig. 2 is found

Fig. 2. Proposed tunable CMOS inductor simulator.

886 S. Minaei, E. Yuce / Int. J. Electron. Commun. (AEÜ) 66 (2012) 884– 891

w

L

G

FvVoi

Z

N

Z

w

Z

T

Z

Fig. 6. Negative impedance realization.

Fig. 3. Equivalent circuit of the proposed inductor simulator of Fig. 2.

here Leq and Gm (m = 3, 4) are, respectively, computed as follows:

eq = C

G3G4(8a)

m = kp(2m−3)(VA(m−2) − |VTP(2m−3)|) + kn(2m−2)(VB(m−2) − VTN(2m−2))

(8b)

rom (8a) and (8b) it can be seen that the equivalent inductancealue (Leq) can be tuned electronically by changing control voltagesA and VB. Considering the parasitic impedances, equivalent circuitf the proposed inductor simulator is demonstrated in Fig. 3. Thenput impedance of the equivalent circuit is computed as

in(s) = 1sCp

//Rp//(sLeq + rs) (9)

eglecting the effect of rs in Fig. 3, the impedance in (9) turns to

in(s) = s/Cp

s2 + s(1/RpCp) + (1/LeqCp)(10)

hich can be rewritten in jω domain as

in(ω) = jω/Cp

−ω2 + jω(1/RpCp) + (1/LeqCp)(11)

he input impedance of (11) can be expressed as

in(ω) = |Zin(ω)| exp(jϕ(ω)) (12)

Fig. 4. Negative tunable resistor for cancellation of unwanted series resistor.

Fig. 5. Electrical symbol of NIC.

Fig. 7. Parasitic impedance effect reduction technique for grounded inductor sim-ulators.

where the magnitude and phase responses are, respectively, foundto be

|Zin(ω)| = ω/Cp√((1/LeqCp) − ω2)2 + (ω/RpCp)2

(13a)

ϕ(ω) = �

2− Arc tan

(ω/RpCp

(1/LeqCp) − ω2

)(13b)

From (13), the following frequency restrictions should be met toobtain an ideal (lossless) inductor simulator

⎧⎨⎩

ω2 � 1LeqCp

⇒ f � 12�

ωo

ω1

RpCp� 1

LeqCp⇒ f � 1

2�

Rp

Leq

(14)

where ωo = 1/√

LeqCp is called as resonance frequency. From (14),the limit at high frequencies due to the parasitic impedances canbe defined as

1{

Rp

}

f � fH =

2�min ωo,

Leq(15)

Fig. 8. NIC implementation with CCII+.

S. Minaei, E. Yuce / Int. J. Electron. Commun. (AEÜ) 66 (2012) 884– 891 887

agni

URe

Z

wrt

R

G

Atbtra

Fig. 9. Ideal and simulation phase and m

sing two transconductance cells of Fig. 1a and a grounded resistor, a negative tunable resistor is obtained as shown in Fig. 4. Thequivalent input impedance of the circuit in Fig. 4 is found as

in(s) = − 1G1G2R

= Req (16)

hich can be used to eliminate or reduce unwanted parasitic seriesesistors (rs) of inductor simulators. Req and Gi (i = 1, 2) are, respec-ively, evaluated as

eq = − 1G1G2R

(17a)

i = kp(2i−1)(VAi − |VTP(2i−1)|) + kn(2i)(VBi − VTN(2i)) (17b)

s mentioned before, the circuit in Fig. 4 can be used for reduc-ion of the parasitic resistances of the inductor simulators. It can

e connected in parallel with capacitor C in the circuit of Fig. 2o reduce/cancel the effect of rs. On the other hand, if a capacitor iseplaced instead of R in the circuit of Fig. 4, a negative grounded tun-ble inductor (L = −C/(G1G2)) is realized. In addition, if the obtained

Magn

itu

de,

(oh

m)

P

hase

, (d

eg)

Fr

10KHz 30KHz 100KHz 300KHz 1.0MHz 3.

1.0

1.0K

100K

-200d

-160d

-120d

-80d

theoretical

simulation

Fig. 10. Ideal and simulation phase and magnitude responses of the negativ

tude responses of the positive inductor.

negative inductance is replaced instead of R in Fig. 4, a tunablecapacitance multiplier is obtained.

It should be mentioned that the gate-source, gate-drain anddrain-bulk parasitic capacitances of the transistors M1–M4 in Fig. 4affect the performance of the circuit at high frequencies. DenotingCin and Ct as the equivalent parasitic capacitances at the input nodeand the node in which the resistor R is connected, respectively,the equivalent circuit of Fig. 4 is composed of a parasitic capaci-tance Cin in parallel with series combination of a negative inductor−Ct/(G1G2) and a negative resistor −1/(G1G2R). Similarly if a capac-itor C � Ct is used instead of the resistor R in the circuit of Fig. 4to realize a negative inductor, we obtain a parasitic capacitance Cinin parallel with a negative inductor −C/(G1G2). However, the par-asitic capacitances can be reduced by selecting the dimensions ofthe transistors as low as possible.

3. Low and high frequency improvement methods

Negative impedance converters (NIC) can be used for elimi-nating the parasitic of simulated inductors and thus enhancing

equency

0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz

e inductor obtained from Fig. 4 using capacitor C instead of resistor R.

888 S. Minaei, E. Yuce / Int. J. Electron. Commun. (AEÜ) 66 (2012) 884– 891

Fig. 11. Magnitude and phase responses of the inductor in Fig. 2 in which Monte Carlo analysis is accomplished by changing capacitor value.

inductor in Fig. 2 where aspect ratios of transistors are changed.

tbwaVt

Z

Fig. 12. Impedance magnitude and phase responses of the

heir frequency performance. The NIC symbol shown in Fig. 5 cane divided into two categories, current inversion-type NIC (INIC)ith terminal current–voltage relationship as I2 = I1 and V2 = V1,

nd voltage inversion-type NIC (VNIC) with equations I2 = −I1 and

2 = −V1 [31]. From the NIC (INIC and VNIC) based circuit of Fig. 6,he following input impedance is calculated:

in(s) = −Z(s) (18)

Fig. 13. Second-order band-pass filter with simulated inductor.Fig. 14. Frequency response of the band-pass filter shown in Fig. 13.

S. Minaei, E. Yuce / Int. J. Electron. Commun. (AEÜ) 66 (2012) 884– 891 889

z, (b) 5

telLuihw

Z

Fig. 15. Time-domain responses of the band-pass filter in Fig. 13 at (a) 1 kH

As it can be seen from the equivalent circuit of the induc-or simulator shown in Fig. 7, reduction or elimination of rs

ffects is achieved by adding −rs in series connection, thus theow-frequency performance is improved considerably [20–23].ikewise, C/

p = Cp and R/p = Rp together with an additional NIC are

sed to improve high-frequency performance of the circuit. Thenput impedance of the equivalent circuit demonstrated in Fig. 7aving the properties of reduced parasitic impedance effects isritten as follows:

in(s) = 1sCp

//

(− 1

sC/p

)//Rp//(−R/

p)//(sLeq + rs − r/s ) (19)

.6 kHz and (c) 25 kHz. C1 = input signal channel, C2 = output signal channel.

If C/p = Cp, R/

p = Rp and r/s = rs are satisfied, the input impedance

given in (19) converts

Zin(s) = sLeq (20)

If NIC in Fig. 7 is obtained from a plus-type second-generation cur-rent conveyor (CCII+) as shown in Fig. 8, Eq. (19) turns to

Zin(s) = 1s(Cp + Czy)

//

(−Rx − sLx +

(− 1

sC/p

)//(−R/

p)

)

//Rp//Rzy//(sLeq + rs − r/s ) (21)

In (21), Czy = Cz + Cy, Rzy = Rz//Ry where Cz, Cy Rz and Ry are Z andY-terminal parasitic capacitors/resistors of the CCII+. Also, Rx and

890 S. Minaei, E. Yuce / Int. J. Electron. Com

Table 1THD variations of the positive inductor simulator in Fig. 2 at 1 MHz.

Magnitude of input current (�A) THD (%) of the produced voltage

10 3.4320 2.0940 1.7460 1.1480 1.53

100 1.13150 1.24200 1.8300 2.68

Lo

4

tpaaoGV±aioaVirtrrv1mrr6iai

spiS3itw

tatapaVt

[

[

[

400 4.04500 5.82

x are, respectively, the X-terminal parasitic resistor and inductorf the CCII+.

. Simulation and experimental results

SPICE simulations of the proposed positive inductor simula-or of Fig. 2 are carried out based on 0.13 �m CMOS technologyarameters given in [32]. The aspect ratios of all the NMOSnd PMOS transistors in Fig. 2 are chosen as 13 �m/1.04 �mnd 39 �m/1.04 �m, respectively. As an example, the capacitorf the simulated inductor in Fig. 2 is taken as C = 30 pF. G3 and4 of the positive inductor simulator with control voltages ofA1 = VA2 = 0.75 V, VB1 = VB2 = 0.55 V and power supply voltages of0.75 V are found as 3.4 mS (obtained from SPICE). Thus, the equiv-lent inductance is approximately found to be 2.6 �H. The positivenductor simulator with improved low-frequency performance isbtained employing negative tunable resistor of Fig. 4 in par-llel with the capacitor C of Fig. 2. In Fig. 4, VA1 = VA2 = 0.75 V,B1 = VB2 = 0.55 V, and R = 16.975 � are used. The circuit is connected

n parallel with capacitor C in the inductor simulator of Fig. 2 toeduce the effects of series resistance (rs). The total power dissipa-ion of the positive inductor in Fig. 2 is found to be 2.3 mW. It can beeduced by decreasing the magnitudes of the control voltages andedesign with smaller capacitance to obtain the same inductancealue. A time-domain analysis applying sinusoidal current input at

MHz with different magnitudes is performed and the total har-onic distortion (THD) of the produced voltage is measured. The

esults are given in Table 1. It can be seen that even for input cur-ent signals with magnitude of 500 �A the THD remain smaller than%. The negative inductor simulator obtained from Fig. 4 replac-

ng resistor R with capacitor C = 30 pF is also simulated. The phasend magnitude responses of the positive and negative simulatednductors are given in Figs. 9 and 10, respectively.

Monte Carlo analysis with 150 runs for the positive inductorimulator of Fig. 2 with 8% variations of C = 30 pF is performed. Thehase and magnitude responses of the impedance of the positive

nductor simulator with respect to frequency are drawn in Fig. 11.imilarly, aspect ratios of all the PMOS transistors are changed from4 �m to 44 �m by 1 �m increment and the impedance of positive

nductor simulator against frequency is given in Fig. 12. It is seenhat simulation results are a bit different from theoretical ones,hich can be attributed to non-idealities of CMOS transistors.

The positive simulated inductor of Fig. 2 is experimentallyested in a second-order band-pass filter as shown in Fig. 13. Thective inductor is implemented using CD4007 CMOS array transis-ors with power supply voltages of ±6 V and C = 100 nF to realizen inductance approximately equal to 9.6 mH. Some of the main

2

arameters of the CD4007 transistors are as follows: kn = 333 �A/Vnd VTN0 = 2 V for the NMOS transistors and kp = 330 �A/V2 andTP0 = −1.5 V for the PMOS transistors. Transconductance values forhe circuit of Fig. 2 are found as G3 = G4 = 3.22 mS (obtained from

[

[

mun. (AEÜ) 66 (2012) 884– 891

SPICE). Other passive elements in Fig. 13 are selected as R1 = 1 k�and C1 = 100 nF which results in a resonance frequency of 5.13 kHzand quality factor of Q = 3.2. A sinusoidal input signal with 1 V peakto peak magnitude and different frequencies ranging from 100 Hzto 100 kHz is applied to the input of the filter and its output voltageis measured. The experimental, simulation with CD4007 transistormodel and theoretical (Leq = 9.6 mH) results of the gain versus fre-quency are shown in Fig. 14. The resonance frequency of the filter isappeared at 5.6 kHz in practice. It is seen from Fig. 14 that the exper-imental result is a bit different from simulation and theoreticalones, which can be attributed to non-idealities of CMOS transistorsand parasitics of the board. The loss of the gain in both simulationand experimental results at resonance frequency is due to the para-sitic resistance which appears in parallel with Leq. The time-domaininput and output signals for the band-pass filter of Fig. 13 at differ-ent frequencies of 1 kHz, 5.6 kHz (resonance frequency) and 25 kHzare shown in Fig. 15a, b and c, respectively. It can be seen that whilethe input signal passes to the output at resonance frequency, it issuppressed at lower and higher frequencies.

5. Conclusion

In this paper, a simple CMOS inductor simulator is proposed.The suggested inductor simulator includes six MOS transistors anda grounded capacitor; accordingly, it is convenient for IC fabri-cation. Moreover simple CMOS structures for realizing negativeresistor and inductor are also driven. The proposed CMOS negativeresistor can be used for elimination of the series parasitic resis-tances of the inductor simulator and improving its low-frequencyperformance. A new technique for providing high-frequency per-formance improvement of simulated inductors is also developed.All the simulations and experimental results verify the workabilityperformance of the proposed inductor simulator.

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32] http://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/ibm-013/t97f 8hp 5lm-params.txt.