A pixel chip for tracking in ALICE and particle ... · 17th May 2000 FEE2000 Perugia, K.H.Wyllie 1...

17th May 2000 FEE2000 Perugia, K.H.Wyllie 1

A pixel chip for tracking in ALICE andA pixel chip for tracking in ALICE andparticle identification in particle identification in LHCbLHCb

•• (Pixels for tracking in ALICE)(Pixels for tracking in ALICE)

•• Pixels for particle ID in Pixels for particle ID in LHCbLHCb

•• General chip descriptionGeneral chip description

•• Pixel cell descriptionPixel cell description

•• ALICE operational modeALICE operational mode

•• LHCbLHCb operational mode operational mode

•• Periphery, configuration and I/O interfacePeriphery, configuration and I/O interface

•• Future plans and conclusionsFuture plans and conclusions

K.WyllieK.Wyllie1)1), M.Burns, M.Burns1)1), M.Campbell, M.Campbell1)1), E.Cantatore, E.Cantatore1)1), V.Cencelli, V.Cencelli2)2),,R.DinapoliR.Dinapoli3)3), F.Formenti, F.Formenti1)1), T.Grassi, T.Grassi1)1), E.Heijne, E.Heijne1)1), P.Jarron, P.Jarron1)1),,

K.KloukinasK.Kloukinas1)1), P.Lamanna, P.Lamanna3)3), M.Morel, M.Morel1)1), V.O’Shea, V.O’Shea4)4),,V.QuiquempoixV.Quiquempoix1)1), D.San , D.San SegundoSegundo Bello Bello5)5), W.Snoeys, W.Snoeys1), 1), L.Van-L.Van-

KoningsveldKoningsveld1)1)

1)1)CERN,CERN,2)2)INFN Rome,INFN Rome,

3)3)University and INFNUniversity and INFN Bari Bari,,4)4)University of Glasgow,University of Glasgow,5)5)NIKHEF, Amsterdam.NIKHEF, Amsterdam.

OUTLINEOUTLINE

See talk by Roberto Dinapoli “An Analogue Front-End forSilicon Pixel Detectors in ALICE and LHCb”


Pixels for tracking in ALICEPixels for tracking in ALICE

nn Minimal massMinimal mass

nn Spatial resolution of 12Spatial resolution of 12µµµµm in r-m in r-φφφφnn 1% average occupancy1% average occupancy

nn Level-1 trigger latency of 5.5Level-1 trigger latency of 5.5µµµµss

nn Level-1 trigger rate = few kHzLevel-1 trigger rate = few kHz

nn Readout after Level-2 triggerReadout after Level-2 trigger

nn Level-2 latency of 100Level-2 latency of 100µµµµs, rate = few kHzs, rate = few kHz

nn Full event readout in 400Full event readout in 400µµµµs (s (deadtimedeadtime ££ 10%)10%)

nn Radiation tolerant to ~ 500 Radiation tolerant to ~ 500 kradkrad

Requirements for the ALICE pixel detectorRequirements for the ALICE pixel detector


Pixels for tracking in ALICEPixels for tracking in ALICE

nn Thin sensors (12000 eThin sensors (12000 e-- signal)signal)

nn Precise time stamp and delay of hitsPrecise time stamp and delay of hits

nn Buffering of Level-1 triggered events inside chipBuffering of Level-1 triggered events inside chip

nn 10MHz readout clock10MHz readout clock

ImplementationImplementation

55 chips + chips + 11 sensor form a sensor form a ladderladder

44 laddersladders aligned in aligned in ZZ form form aa stave stave

6060 staves staves form the 2-layer barrel geometry around the interaction form the 2-layer barrel geometry around the interactionpointpoint

1010 chips of one chips of one half-stavehalf-stave read out sequentially in 400 read out sequentially in 400µµµµss

120120 half-staveshalf-staves read out in parallel read out in parallel

Half StaveHalf Stave

ladder2 ladder1


Pixels for particle ID in Pixels for particle ID in LHCbLHCb

nn Sensitivity to single photonsSensitivity to single photons

nn No false hits due to noise (pattern recognition)No false hits due to noise (pattern recognition)

nn 2.5mm 2.5mm ¥¥ 2.5mm channel size2.5mm channel size

nn 8% maximum occupancy8% maximum occupancy

nn 1MHz average Level 0 trigger rate1MHz average Level 0 trigger rate

nn Level-0 trigger latency of 4Level-0 trigger latency of 4µµµµss

nn DerandomisationDerandomisation of Level-0 triggered events of Level-0 triggered events

nn Readout of triggered event in 900ns (Readout of triggered event in 900ns (deadtimedeadtime ££ 1%) 1%)

Baseline Baseline photodetectorphotodetector for for CherenkovCherenkov photons in the photons in the LHCb LHCbRICH:RICH:

Encapsulation of pixel chip and sensor within aEncapsulation of pixel chip and sensor within a

Hybrid Photon Detector (HPD)Hybrid Photon Detector (HPD)

RequirementsRequirements



Implementation

•5000e- signal with 20kV accelerating potential•Low power consumption (vacuum)•Compatible with tube manufacturing•Precise time stamp and delay of multiple hits•40MHz readout clock•500µµm ¥ 500µµm (¥ 5 demagnification) granularity•Buffering of Level-0 triggered events•System of 500 HPDs



Full scale prototype


Chip DescriptionChip Description

uu Fabricated in a commercial Fabricated in a commercial 0.250.25µµµµm CMOSm CMOS process process

nn High component densityHigh component density

nn Thin gate oxide - small Thin gate oxide - small VVthth shifts after irradiation shifts after irradiation

uu Radiation-tolerant layoutRadiation-tolerant layout: Enclosed gates and guard: Enclosed gates and guardringsrings

uu SEU-hardenedSEU-hardened logic logic

uu ~ 13 million~ 13 million transistors transistors

uu 1.6V1.6V power supply power supply

uu Total static power consumption Total static power consumption 480mW480mW


Pixel CellPixel Cell

130130µµµµmm

uupre-amp (differential)pre-amp (differential)

uushaper (differential)shaper (differential)

uudiscriminator (+ fast-OR)discriminator (+ fast-OR)

uu6060µµµµW static consumptionW static consumption

see see Roberto’sRoberto’s talktalk

260260µµµµmm

uutwo digital delay unitstwo digital delay units

uutrigger coincidence logictrigger coincidence logic

uu4-event FIFO buffer4-event FIFO buffer

uureadout logicreadout logic

3535µµµµmm

5 5 unun--upsettableupsettable latches for configuration latches for configuration

n test input on/off

n pixel mask on/off

n 3 bits of threshold adjust


Pixel Cell : Digital CircuitryPixel Cell : Digital Circuitry

Delay unit:Delay unit: stores a hit for duration of trigger latencystores a hit for duration of trigger latency

latches the time-stamp of a hit from alatches the time-stamp of a hit from aperiodic Gray-encoded pattern (modulo n)periodic Gray-encoded pattern (modulo n)on an 8-bit buson an 8-bit bus

FIFO: FIFO: Read/write addressable by Gray encoded busRead/write addressable by Gray encoded bus

Risk of switching noise coupling into analog circuitry isRisk of switching noise coupling into analog circuitry isreduced by: reduced by:

n Gray encoding of patterns on busses

n Current starved logic cells

n Differential front end - Roberto


ALICE Operational ModeALICE Operational Mode

up to 2 hits per Level-1 latency per cellup to 2 hits per Level-1 latency per cellreadout time of 256 readout time of 256 ¥¥ 100ns = 25.6 100ns = 25.6µµµµss


LHCbLHCb Operational Mode Operational Mode

8 pixels configured as a 8 pixels configured as a ‘super-pixel’‘super-pixel’ of 400 of 400µµµµm m ¥¥ 425425µµµµmmreadout time of 32 readout time of 32 ¥¥ 25ns = 800ns 25ns = 800ns


The ‘super-pixel’The ‘super-pixel’

400400µµµµm m ¥¥ 425425µµµµmm


Periphery and ConfigurationPeriphery and Configuration

PeripheryPeriphery contains: contains: CountersCounters to generate timestamp to generate timestamp

CountersCounters to address FIFO buffers to address FIFO buffers

8-bit 8-bit DACsDACs to provide voltage and to provide voltage and current references for analog circuitrycurrent references for analog circuitryand current-starved logicand current-starved logic

ConfigurationConfiguration of peripheral logic and pixel cells by means of peripheral logic and pixel cells by meansof of JTAGJTAG serial interface - serial interface -

allows both allows both writewrite and and readread of of configuration settings (test,mask….)configuration settings (test,mask….)

reading backreading back of analog levels of analog levels (currents & voltages) generated by(currents & voltages) generated byDACsDACs

connectivity testsconnectivity tests of chips on stave of chips on staveusing boundary scanusing boundary scan

allows detection of allows detection of bad chipsbad chips on stave on stave


Configuration Memory CellsConfiguration Memory Cells

Threat of SEUThreat of SEU: not as bad as ATLAS and CMS but …...: not as bad as ATLAS and CMS but …...

Policy to protect memory cells against SEU (but not dataPolicy to protect memory cells against SEU (but not datalogic)logic)

Memory cellsMemory cells in pixels and in pixels and DACsDACs: SEU-hardened circuit : SEU-hardened circuit

Calin et al., IEEE Trans. Nucl. Sci. 43 No. 6,Dec 1996.


I/O InterfaceI/O Interface

I/O padsI/O pads: Single-ended: : Single-ended: Gunning Transceiver LogicGunning Transceiver Logic (GTL) (GTL)

••low swinglow swing

••slew rate controlslew rate control

Separate supplySeparate supply for output buffers for output buffers

Multiple bonding padsMultiple bonding pads for supply lines to reduce for supply lines to reduceinductance and limit on-chip power supply bounce duringinductance and limit on-chip power supply bounce duringswitchingswitching


Design ProblemsDesign Problems

‘Big’ Chip‘Big’ Chip: : Voltage drops: both X-direction (across chip)Voltage drops: both X-direction (across chip)and Y-direction (up columns)and Y-direction (up columns)

=> 6 metal layers needed to stay within=> 6 metal layers needed to stay withinspecs for chip sizespecs for chip size

=> sensitive biases sent individually to=> sensitive biases sent individually tocolumnscolumns

time-of-flight delays up columns (few time-of-flight delays up columns (few nsns))

simulation - required a complex simulation - required a complex VerilogVerilog descriptiondescription

checking (!) - DRC,extraction, LVSchecking (!) - DRC,extraction, LVS

Packaging for HPD encapsulationPackaging for HPD encapsulation::

Commercial PGA carriers bond-pad limited (butCommercial PGA carriers bond-pad limited (butplenty of pins!)plenty of pins!)

Possible custom carrier in futurePossible custom carrier in future


Future PlansFuture Plans

Design is with the foundryDesign is with the foundry

Chip back end of Chip back end of JuneJune

Sensors available in Sensors available in AugustAugust

=> bump-bonding=> bump-bonding

ALICEALICE: : testbeamstestbeams foreseen for end of foreseen for end of 20002000

LHCbLHCb: : plan encapsulation of chips in plan encapsulation of chips in HPDs HPDs by end of by end of20002000

Begin second iteration of chip to meet full specsBegin second iteration of chip to meet full specs


ConclusionsConclusions

Chip designed to meet requirements of both the Chip designed to meet requirements of both the ALICEALICEtracker and the tracker and the LHCbLHCb RICHRICH

Deep-Deep-submicronsubmicron technology has allowed the inclusion of technology has allowed the inclusion oflarge amount of functionality within each pixel cell large amount of functionality within each pixel cell BUTBUT

meeting the specs has been a challenging exercise!meeting the specs has been a challenging exercise!

Consideration to: Consideration to: reducing switching noisereducing switching noise

minimisingminimising power consumption power consumption

testability and system integrationtestability and system integration

radiation toleranceradiation tolerance

A pixel chip for tracking in ALICE and particle ... · 17th May 2000 FEE2000 Perugia, K.H.Wyllie 1...

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