Paper Lecture 2.3 INTERNATIONAL TEST CONFERENCE 978-1-4799-0859-2/13/$31.00©2013 IEEE

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A Novel Test Structure for Measuring the Threshold Voltage Variance in MOSFETs

Takahiro J. Yamaguchi*1, James S. Tandon1, Satoshi Komatsu1, Kunihiro Asada1

*Advantest Laboratories, Ltd., Sendai, Miyagi, Japan 1D2T, VDEC, The University of Tokyo, Tokyo, Japan

Abstract A new threshold voltage variation monitoring circuit is introduced which utilizes a stochastic comparator group. It occupies minimal area, only requires a DC input stimulus voltage, and performs digital DC measurement. Traditional methods have required the measurement of the variation in a ring oscillator frequency. Our method circumvents the need for AC measurements, and accelerates the accumulation of data by incorporating stochastic properties into the circuit. 1. Introduction

It is well known that the variation of the transistor threshold voltage VT in CMOS circuitry increases as the circuitry scales to smaller and smaller nodes. The push toward smaller transistor sizes tightens constraints on the fabrication process, and consequently circuit designers can expect transistors to have increased variability in their threshold voltages. Circuits must be designed to be robust against a certain amount of variation. During post-silicon verification, an individual integrated circuit is more likely to fail its performance specification if threshold voltage variation exceeds its limits.

Ring oscillator-based test structures are widely used for measuring circuit switching delays [1], [2], [3], [4], [5], [6]. They are also used for characterizing aging at the circuit level [7]. However, as supply voltage drops, AC measurements using ring oscillators become very sensitive to power-supply noise, and are also less accurate due to supply noise induced jitter.

Furthermore, measurement of statistical variations in MOSFET parameters typically require several hours of test time using an off-line test environment [1]. It is therefore advantageous to develop compact rapidly testable test structures to extract threshold voltage variations, which don’t require AC measurements.

A stochastic comparator group is a component of a stochastic flash analog-to-digital converter that takes advantage of process variation to convert an analog voltage to a digital value [8]. An individual clocked comparator has an offset voltage VOS that is usually regarded as a quantization error in an analog-to-digital

converter. However, if enough comparisons with random offset voltages are summed together in a comparator group, its output can be assumed to follow a Gaussian cumulative density function (CDF) [8]. This CDF can be used as a transfer function for the analog-to-digital conversion process. The linear range of the stochastic transfer function is dependent upon the probability density function (PDF) of the threshold voltages of the pMOSFETs or nMOSFETs.

The nature of a stochastic comparator group makes it a strong candidate for use in a test structure to characterize variations of the threshold voltage in MOSFETs. In this work, we propose a methodology for measuring the within-die process (WID) and die-to-die (D2D) variations using a new test structure, i.e. a stochastic comparator group.

The process variation of offset voltage in a clocked comparator follows a Gaussian-like distribution with

average OSV , and variance 2

OSV . We will show that

the offset voltage variance 2

OSV can be measured using

a stochastic comparator group, and furthermore, how the

threshold voltage variance 2

TV can be derived using this

approach. Generally speaking, random variability follows a

Gaussian distribution. However, in some cases [9], it can be shown to follow a non-Gaussian distribution. We will show from experiments that some random VT variations follow a non-Gaussian distribution.

Power voltage scaling makes it mandatory to use voltage with high resolution, such as 1 mV, in order to measure a high-accuracy PDF. In order to accurately

calculate the voltage variance 2

OSV , a procedure for

extracting high-accuracy PDF estimates from high-resolution non-Gaussian CDFs is required [10].

In this paper, the effectiveness of our new test structure combined with a procedure for estimating high-resolution PDFs [10] and the distribution model identification method [11] is demonstrated using experimental data from 65 nm CMOS stochastic comparator groups.

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In Section 2, conventional ring-oscillator based test structures are revisited. In Section 3, the theory of a stochastic comparator group structure and a procedure for calculating the variance of the MOSFET VT are developed. In Section 4, the proposed test structure and procedure for estimating high-accuracy PDFs is experimentally validated. Finally in Section 5, the advantages and limitations of the proposed methodology are discussed. 2. Statistical Terms & Ring-Oscillator Based Test Structures

In this section, some relevant statistical terms are defined first, followed by a brief review of the causes of threshold voltage variations. Conventional ring-oscillator based test structures are also discussed.

2.1 Terms

Cumulative Distribution Function (CDF) [12]. The CDF of the random variable t , denoted as RV t , is

a non-decreasing function tF defined on the whole

real line and satisfying the conditions (1) below:

ttF tP (1)

Probability Density Function (PDF). The PDF

tf is defined as the derivative of the CDF tF :

dt

tdFtf (2)

The mean of RV t depends only on the distribution of RV t . Therefore, if the CDF is known,

the mean tE can be expressed as an integral function

of tf [12].

tdFE t

dtttf (3)

The variance, tVar of RV t also depends on

its distribution, and can also be expressed as an integral

function of 2t and tf [12]:

tVar

dttfEt

2t (4)

Ergodicity [13]. Ergodicity is term which describes the relationship between statistical averages and

sample averages. A stochastic process tx is called

ergodic if its ensemble averages equal appropriate time averages.

Poisson Distribution [14]. Poisson experiments are experiments that yield numerical values of a random variable x quantifying the number of outcomes occurring in a specified region or during a given time interval.

The Poisson random variable x is the number of outcomes occurring during a Poisson experiment, and its probability distribution is called a Poisson distribution. The mean number of outcomes is computed from

t , where t is the specific “region” or “time” of

interest.

!k

tek

kt xPλ ,,2,1,0 k (5)

The Central Limit Theorem [13]. Let’s assume that we have N independent but identically distributed random variables, each with a finite mean and variance. Then, employing the central limit theorem, the distribution of the sum process of these random variables can be approximated by a Gaussian distribution.

The Variance of the Sum of Two Random Variables. If z = x + y, then z = x + y, hence

zz Var z2

yxVar yx

2yxE yx

]2

[ 22

yx

yxE

yx

yx

where xE is the mean of RV x and xVar is its

variance. From the above it follows that

yxyxz 2222 (6)

where is the correlation coefficient of the RVs x

and y [13]. For the case where 22xy , Eq. (6)

becomes

22xz (7)

Random Variations. Random variations in the

MOSFET voltage VT. can be caused by many sources, including random discrete doping (RDD), line-edge roughness (LER), line-width roughness (LWR), interface roughness, gate-oxide thickness (TOX) variation, and high-k dielectric morphology with metal gates. Systematic variability includes the variability caused by optical-proximity effect, phase-shift masking, layout induced strain, well-proximity effects and non-uniform temperature distribution during annealing.

Doping and Threshold Voltage Variation [15]. The uncertainty caused by atomistic doping gives rise to significant variation in VT. The source and drain doping is usually quite dense and does not cause variations in the voltage VT. However, channel doping near the surface and close to the actual channel has the largest effect on VT, and is therefore susceptible to statistical variation.

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The implant and annealing processes cause the placement of a random number of dopants in a channel. Moreover, quantum-mechanical effects in the channel

have been shown to cause an increase in 2

TV . In very

short FETs, statistical doping effects can cause significant variation in short-channel behavior. A random deficit of doping concentration in the wrong place can create near punch-through states. Dopant follows a Poisson distribution. The spread in VT can be approximately expressed as

effeff

AOXV

WL

NtT

4.081019.3 [V]

(8)

where AN , effL , and effW are the average channel

doping and the effective channel length and width, respectively.

Line-Edge Roughness & Threshold Voltage Variation [16]. LER, which stems from a variation in the critical dimension of the feature size due to sub-wavelength lithography, is the second major source of process variability. LFR is a major source of D2D statistical variability for shorter-length devices beyond 45 nm. The VT mismatch due to LER depends on the

variability in effW of MOSFETs and is approximated

by:

eff

VWT

1 (9)

2.2 Ring-Oscillator-Based Test Structure

Random variations in manufacturing processes will cause the actual values of circuit parameters to be different from their target or nominal values. For example, the channel length can be decomposed into a

nominal component 0L and a statistically varying

component L : LLL 0 [17]. Variation in the channel length is caused by fluctuations in the

manufacturing processes. L and TV are referred

to as internal noise parameters. On the other hand, VDD is an external noise parameter. The statistical distributions of the internal noise parameters can be obtained via test structure measurements and parameter extraction [17]. A compact model of circuit performance can be constructed in terms of these parameters and used to evaluate circuit performance.

Ring oscillators (ROs) are widely used for monitoring process variation [Fig. 1(a)]. The distribution in the oscillation frequency of similar pairs of ROs provides information on the random variations in

MOSFET parameters. RO-based circuits are typically used to provide an average over hundreds of devices. This means that the threshold voltages of nMOSFETs and pMOSFETs are averaged together [2]. Thus, it is impossible to perform independent measurement of nMOSFET and pMOSFET performance using simple RO-based test structures.

Reference [1] introduced an inverter structure with an nMOSFET passgate (NPG) at the inverter output [Fig. 1(b)]. The VDD dependence of the stage delay is dominated by the NPG. Since a change in VDD (VDD) of the gate voltage is equivalent to a negative change in VT of the same magnitude for the NPG, it follows that;

f/VDD ~ -f/ VT

(b) (c)

(a)

s 1 s 2ms 2

(b) (c)

(a)

s 1 s 2ms 2s 1 s 2ms 2

Fig. 1. Ring oscillator and ring oscillator stages. (a) Ring oscillator with (2m + 1) stages. (b) Inverter stage with an nFET passgate at the

output. (c) Inverter stage with an nFET passgate at the input.

VIN,DC

VLVL

VIN,DC

VLVL

Fig. 2. Stochastic comparator group. A DC voltage VIN,DC is swept around a reference voltage VLVL of the stochastic comparator group.

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Thus f/VDD can be directly measured and used to extract the VT statistics from the frequency data.

However, since the voltage drop across the passgate is non-zero, for the NPG structure in Fig. 1(b), the output voltage of the passgate does not go to VDD. Thus, the pMOSFET on the next stage causes additional delay due to its partially-on condition. This makes the inverter on the next stage more sensitive to pMOSFET variations [4].

Test structures have been studied to enable independent measurement of nMOSFET and pMOSFET performance [4], [5], [6]. For instance, to increase the sensitivity of either nMOSFET or pMOSFET passgates to random VT variations, reference [4] introduced new inverter structures, which are shown in Fig. 1(c).

However, since extracting the VT statistics from measured RO frequency data is model-dependent, measured RO frequencies are only valid if they are consistent with simulation models for the manufactured (slow, medium, fast) transistor data. Otherwise, no mapping is possible from measured frequency data to the VT statistics.

2.3 Limitations of the Existing RO Approaches

The limitations of the existing RO approaches can be summarized as follows: An RO-based test structure requires transistor models

to map the measured data to threshold voltage variations. Thus, if the range of transistor variations is too large, the measured RO variation cannot be mapped to a threshold voltage variation.

An RO-based test structure requires AC measurements, an on-chip frequency divider, and an off-chip counter to measure the oscillating period. Furthermore, the test time must be long enough to obtain the required high accuracy.

As supply voltage goes down, AC measurements using ring oscillators become more sensitive to external noise. Power-supply noise increases voltage drop and supply noise induced jitter degrades the measurement accuracy.

An RO-based test structure requires excessive and precise calibration [1].

3. A New Test Structure

The theory underlying our new approach to measuring the variance of the MOSFET VT utilizing a stochastic comparator group and a novel calculation procedure is now presented.

3.1 Stochastic Comparator Group

In order to obtain statistical characteristics of the offset voltage of both nMOSFETs and pMOSFETs, we use an array of rail-to-rail comparators [Fig. 3(c)]. Each sub-group of comparators consists of both nMOSFET and

pMOSFET differential amplifiers and a decision circuit. This comparator array is called a stochastic comparator group, and it is illustrated in Fig. 2. Offset voltage VOS variation in the Ncomp comparators can be estimated by measuring a random yield of the stochastic comparator group as a function of the input voltage difference:

[i] A DC voltage difference (VIN,DC – VLVL) is applied to the

stochastic comparator group, and outputs from the Ncomp clocked comparators are summed to provide the random yield. This is equal to the cumulative distribution function (CDF) of VOS.

[ii] Then the DC voltage difference is swept by changing the DC voltage VIN,DC.

[iii] Steps [i] and [ii] are repeated until the sum equals to Ncomp.

The CDF of VOS in terms of Ncomp MOSFETs for

analog signals is given by:

OSOS VVF vP (10)

For digital signals, this leads to,

compOS

OS

N

k

V

kV dttfD1

(11)

Since these distributions tfk are identical, Eq. (11)

becomes,

OS

OS

V

CompV dttfND (12)

If the distribution is Gaussian, it leads to,

OS

OSOSCompV

Verf

ND

OS

21

2

(13)

Note that if ergodicity is assumed to be true, the mean and variance of a single MOSFET can be determined from its

CDF, OSVF or OSVD . In Section 4, procedures for

extracting the PDF from a CDF are compared to determine an appropriate method for calculating accurate

variance estimates 2OS .

3.2 Variance of the MOSFET Offset Voltage VOS

For measuring the variance of the nMOSFET VT,N, we will assume that if both the VIN,DC and VLVL are set to voltages greater than VDD – |VT,P|, then the nMOSFET input stage transistors are in the saturation region and the pMOSFET input stage transistors are in the sub-threshold

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region [Fig. 3(c)]. Therefore, 2OS is dominated by the

variance of the nMOSFET VOS.

It is also assumed that two nMOSFETs N1 and N2 are of the same transistor size ( WL , where L is the channel length and W is the channel width of the MOSFET). Due to statistical doping effects, it is further assumed that the two nMOSFETs are uncorrelated with each other, i.e., their correlation coefficient is 0 , the

variance of the nMOSFET VOS can be obtained from Eq. (6)

22,

21,

2NVNVOS TT

(14)

Moreover, since nMOSFETs N1 and N2 are almost in the

same location, it is assumed that 22

21 tNtN . Hence,

the variance of the nMOSFET VT,N is calculated by:

2

22

,OS

NVT

( PTDDLVL VVV , ) (15)

For measuring the variance of the pMOSFET VT,P, if both the VIN,DC and VLVL are set to voltages less than VSS + |VT,N|, then the pMOSFET input stage transistors are in the saturation region and the nMOSFET input stage transistors are in the sub-threshold region. Therefore,

2OS is dominated by 2

,PVT and the variance of the

pMOSFET VT,P is calculated by:

2

22

,OS

PVT

( NTSSLVL VVV , ) (16)

4. Performance Validation and Comparison

In this section, the proposed test structure and the procedure for estimating high-resolution PDFs are experimentally validated. It will also be shown that some random VT variations follow a non-Gaussian distribution.

4.1 Experimental Results 4.1.1 Experimental Setup

We implemented the comparator group in a 65nm CMOS technology with 64 comparators in a single group. Their outputs were then fed to a summing encoder. Only 63 comparators were summed since together they provided an even, 6-bit output code. Fig. 3(a) shows the

die photo of the stochastic comparator group and summing encoder. The comparator group was laid out manually, while the encoder was implemented with a standard digital design flow. Its layout is shown in Fig. 3(b). The active area of the comparator group was 150m 35m, and the active area of the encoder was 170m 30m.

Fig. 4 shows our experimental setup for verifying the chips. LabVIEW (National Instruments) was used as the control program to acquire data through a logic analyzer (Agilent Technologies 16822A). The system was clocked at 5.32MHz by a bit error rate tester (Agilent Technologies ParBERT 81250).

We chose VLV L = 1000mV to isolate the nMOSFET differential amplifier offset voltages and VLV L = 200mV to isolate the pMOSFET differential amplifier offset voltages.

This allowed us to measure 2,NVT

and 2,PVT

respectively. The input VIN,DC was stepped in 1mV

ComparatorGroup

Encoder

(b)

(c)

(a)

decision circuit

ComparatorGroup

EncoderComparator

Group

Encoder

(b)

(c)

(a)

decision circuit

decision circuit

Fig. 3. Stochastic comparator group, which

consists of Ncomp comparators. A 65 nm CMOS. (a) Die photo. (b) Chip layout. (c) A single clocked comparator and its decision circuit.

BERTS

Agilent 81250

CLKCLKb

1.2 V

3.3 V Vlvl

Vin,dcoutput code

Logic AnalyzerAgilent 16800

BERTSAgilent 81250

CLKCLKb

1.2 V

3.3 V Vlvl

Vin,dcoutput code

Logic AnalyzerAgilent 16800

Fig. 4. Experimental setup for validating the stochastic comparator group.

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increments around VLVL for each setting of VLVL chosen. For each DC voltage difference (VIN,DC – VLVL), 32 768 summed values were collected. 4.1.2 Procedures for Measuring High-Resolution PDF

Two different procedures for calculating a PDF were compared with each other to determine an appropriate method for providing accurate variance estimates. Fig. 5(a) plots an nMOSFET CDF curve of the chip D. Note that, by applying the distribution identification method [11], this CDF was validated to follow the Gaussian distribution. However, the PDF obtained by performing a difference operation on the fine-resolution CDF results in significant random error, as shown in Fig. 5(b).

The PDF tf , also plotted in Fig. 5(c) was

measured by applying the procedure [10] for calculating high-accuracy PDF estimates from a CDF. The PDF

tf clearly exhibits a Gaussian distribution. The

PDF estimates obtained from this proposed procedure are random-error free and are also nearly bias-error free [10].

In the following subsection, this procedure for calculating high-accuracy PDF estimates [10] was used to calculate variances for both Gaussian and non-Gaussian distributions. 4.1.3 Variance of MOSFET VOS

Fig. 6 and Fig. 7 show the CDFs and PDFs tf

for VOS,N and VOS,P of chips D and A, respectively. Using the distribution identification method [11], the PDF,

shown in Fig. 6(b), follows a triangular distribution, while the PDF shown in Fig. 7(b) follows a Gaussian distribution. Note also that Fig. 6 compares measured distributions with synthesized triangular distributions. Since the two distributions are almost identical, this confirms the accuracy of the distribution identification method presented in [11] for calculating random VT variations that follow a non-Gaussian distribution. Table I lists the calculated threshold voltage standard deviations and the identified dominant distribution models. Fig. 8 compares the expected process variation data (extracted from I-V measurements provided by the

(c)

(a)

(b)0

f(Vin)

0.04

0.08

f+(Vin)

-20 0.0 Vin,DC – Vlvl [mV]0

100

0.02

20

0.04

30

0

60number of ones

(c)

(a)

(b)0

f(Vin)

0.04

0.08

0

f(Vin)

0.04

0.08

f+(Vin)

-20 0.0 Vin,DC – Vlvl [mV]0

100

0.02

20

0.04f+(Vin)

-20 0.0 Vin,DC – Vlvl [mV]0

100

0.02

20

0.04

-20 0.0 Vin,DC – Vlvl [mV]0

100

0.02

20

0.04

30

0

60number of ones

30

0

60number of ones

Fig. 5 (a) Yield CDF. (b) PDF measured by diff(CDF). (c) PDF measured by a procedure [10].

An nMOSFET yield (= number of ones) versus Vin,DC – Vlvl and its pdf.

(a)

(b)

30

60number of ones

0

1000 mV200 mV

0

f+(Vin)

0.02

0.04

-40 0.0 Vin,DC – Vlvl [mV] 100

(a)

(b)

30

60number of ones

0

1000 mV200 mV

30

60number of ones

0

1000 mV200 mV

0

1000 mV200 mV

1000 mV200 mV

1000 mV200 mV

0

f+(Vin)

0.02

0.04

-40 0.0 Vin,DC – Vlvl [mV] 1000

f+(Vin)

0.02

0.04

-40 0.0 Vin,DC – Vlvl [mV] 100Fig. 6 [chip D] Yield (= number of ones) versus Vin,DC – Vlvl and its pdf. The yield and the pdf

follow a triangular distribution. (a) Yield CDF. (b) PDF. For Vlvl = 1000 mV, OS = 14.0 mV. For

Vlvl = 200 mV, OS = 14.7 mV.

(a)

(b)0

f+(Vin)

0.02

0.04

-40 0.0 Vin,DC – Vlvl [mV] 100

30

0

60number of ones

1000 mV200 mV

(a)

(b)0

f+(Vin)

0.02

0.04

-40 0.0 Vin,DC – Vlvl [mV] 100

30

0

60number of ones

1000 mV200 mV

1000 mV200 mV

Fig. 7 [chip A] Yield (= number of ones) versus Vin,DC – Vlvl and its pdf. The yield and the pdf follow a Gaussian distribution. (a) Yield CDF. (b) PDF. For Vlvl = 1000 mV, OS = 18.0 mV. For Vlvl = 200 mV, OS = 14.8 mV.

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foundry), to the standard deviation in threshold voltages

calculated from data measured by our new process

monitoring structure. The detected 2,NVT

and

2,PVT

are within the expected range provided by the

foundry. This experimentally validates our new test structure and procedure for extracting a high-accuracy

PDF, tf , and hence validating its effectiveness for

monitoring the variance 2

TV in the threshold voltage.

Table II compares the results of our method with those of previous works. The proposed new test structure consumes a transistor count that is comparable to ring-oscillator based test structures.

5. Advantages and Limitations of the Proposed Test Structure

Following are the advantages and limitations our

new test structure and procedure for extracting high-accuracy PDFs.

Advantages Unlike an RO-based test structure, our proposed test

structure requires no transistor model. Even if transistor variation is large, it accurately measures the threshold voltage variations.

Its estimates of threshold voltage variance 2

TV are

comparable with the data extracted from I-V measurements: Fig. 8.

Since it performs ergodicity-based measurements using Ncomp rail-to-rail comparators, test times are shortened by at least Ncompx, compared to other methods. Measurement accuracy is enhanced by

compN x.

It can be applied to the D2D & WID characterizations of CMOS technology.

The test structure enables independent measurement of variations in both nMOSFET and pMOSFET performance without modifying the circuit.

Since it circumvents the need for AC measurements, it is easily implemented with on-chip circuitry.

The proposed test structure is not sensitive to the power-supply noise, supply noise induced jitter, or temperature change.

When calibration is necessary, it requires minimum effort.

Limitations This approach cannot be used to directly measure the

threshold voltage VT.

080 100 120

20

10

30VT standard deviation, stochastic comp. group

(1000 mV, 200 mV; low Vth CMOS)standard deviation, I-V characteristic(nMOS, pMOS; low Vth CMOS)

A0.5Asilicon [arb.]

080 100 120

20

10

30VT standard deviation, stochastic comp. group

(1000 mV, 200 mV; low Vth CMOS)standard deviation, I-V characteristic(nMOS, pMOS; low Vth CMOS)

standard deviation, stochastic comp. group(1000 mV, 200 mV; low Vth CMOS)standard deviation, stochastic comp. group(1000 mV, 200 mV; low Vth CMOS)standard deviation, I-V characteristic(nMOS, pMOS; low Vth CMOS)

A0.5Asilicon [arb.]A0.5Asilicon [arb.]

Fig. 8 Standard deviation of threshold voltage Vthresh,SC, Vthresh,IV as a function of silicon area A0.5.

Table I. Estimated standard deviation of threshold voltage with distribution model.

triangle-like

trapezoid

Gaussian

traiangulartriangular

triangle-like trapezoid

Gaussian

GaussianGaussian

GaussianGaussian

ChipnMOS pair pMOS pair

VT,N [mV] VT,P [mV]

A12.7 10.5

B13.9 11.6

C13.2 8.45

D9.89 10.4

E17.9 9.21

triangle-like

trapezoid

Gaussian

traiangulartriangular

triangle-like trapezoid

Gaussian

GaussianGaussian

GaussianGaussian

ChipnMOS pair pMOS pair

VT,N [mV] VT,P [mV]

A12.7 10.5

B13.9 11.6

C13.2 8.45

D9.89 10.4

E17.9 9.21

Table II. Comparison with previous circuits for monitoring threshold voltage VT or degradation in

threshold voltage.

No

Yes

Yes

Yes

Model based

?

--

1000 +

conter

nMOS

Var.

pMOS

Var.

ReferenceProcess

[nm]

Number of transistors

Minimum number of ROs

(Divider)

Sensitive to

Supply Nose

Kyoto Univ. [3]

65 1000 + counter 3

(64)

Yes

IBM

[2]

45 1000 +

conter

2 VCO

(1024)

Yes

Altera

[7]

28 1000 +

conter

1

(256)

Yes

This

work

65 1134 + encoder -- No No

Yes

Yes

Yes

Model based

?

--

1000 +

conter

nMOS

Var.

pMOS

Var.

ReferenceProcess

[nm]

Number of transistors

Minimum number of ROs

(Divider)

Sensitive to

Supply Nose

Kyoto Univ. [3]

65 1000 + counter 3

(64)

Yes

IBM

[2]

45 1000 +

conter

2 VCO

(1024)

Yes

Altera

[7]

28 1000 +

conter

1

(256)

Yes

This

work

65 1134 + encoder -- No

Paper Lecture 2.3 INTERNATIONAL TEST CONFERENCE

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6. Conclusion

We introduced a new threshold voltage variation monitoring circuit which utilizes a stochastic comparator group that performs digital measurement, only requires a DC input stimulus voltage, and utilizes a transistor count that is comparable to ring-oscillator based test structures. The effectiveness of the proposed test structure and the calculating procedure [10] and distribution identification method [11] was experimentally validated using 65 nm CMOS stochastic comparator groups.

This approach utilizes a new method for calculating

the offset voltage variance 2

OSV using a stochastic

comparator group. A derivation of the mathematics for

calculating the threshold voltage variance 2

TV was

provided. It was shown and experimentally verified that some random VT variations follow a non-Gaussian distribution.

Acknowledgements

We would like to thank Mr. S. Kuroe, vice president of Advantest Corp., Dr. T. Okayasu, executive vice president of the SoC test business group, Dr. M. Takikawa, director of Advantest Laboratories Ltd., and Mr. T. Tokuno, president of Advantest Laboratories Ltd. for their encouragement and support of this research.

The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC) at the University of Tokyo in collaboration with e-Shuttle, Inc. Fujitsu Semiconductor, Ltd., Synopsys, Inc., Cadence Design Systems, Inc. and Mentor Graphics, Inc. References [1] M. P. Ketchen, and M. Bhushan, “Product-representative

‘at-speed’ test structures for CMOS characterization,” IBM J. Res. & Dev., vol. 50, no. 4/5, pp. 451-468, 2006.

[2] R. Rao, K. A. Jenkins, and J.-J. Kim, “A local random variability detector with complete digital on-chip measurement circuitry,” IEEE J. Solid-State Circuits, vol. 44, no. 09, pp. 2616-2623, Sep. 2009.

[3] I. A.K.M. Mahfuzul, A. Tsuchiya, K. Kobayashi, and H. Onodera, “Variation-sensitive monitor circuits for estimation of die-to-die process variation,” in Proc. IEEE Int. Conf, Microelectronic Test Structures, Amsterdam, Netherlands, April 4-7, 2011, pp. 153-157.

[4] I. A.K.M. Mahfuzul, and H. Onodera, “On-chip detection of process shift and process spread for silicon debugging and model-hardware correlation,” in Proc. IEEE The 21st Asian Test Symp., Niigata, Japan, November 19-22, 2012, pp. 350-354.

[5] T. Iizuka, J. Jeong, T. Nakura, M. Ikeda, and K. Asada, “All-digital on-chip monitor for PMOS and NMOS process variability measurement using buffer ring with pulse counter,” in Proc. IEEE European Solid-State Circuits Conference, Seville, Spain, Sep. 14-16, 2010, pp. 182-185.

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