A NOVEL COMPENSATION METHOD FOR IMPROVING ERROR …€¦ · radio frequency complementary metal...

http://www.iaeme.com/IJARET/index.asp 11 [email protected]

International Journal of Advanced Research in Engineering and Technology (IJARET)

Volume 11, Issue 7, July 2020, pp. 11-20, Article ID: IJARET_11_07_002

Available online athttp://www.iaeme.com/IJARET/issues.asp?JType=IJARET&VType=11&IType=7

ISSN Print: 0976-6480 and ISSN Online: 0976-6499

DOI: 10.34218/IJARET.11.7.2020.002

© IAEME Publication Scopus Indexed

A NOVEL COMPENSATION METHOD FOR

IMPROVING ERROR AND SETTLING TIME OF

A 3rd ORDER PHASE-LOCKED LOOP FOR

COMMUNICATION SYSTEM

Munmee Borah*

Department of Electronics & Communication Technology,

Gauhati University, Guwahati, India

Tulshi Bezboruah

Department of Electronics & Communication Technology,

Gauhati University, Guwahati, India

*Corresponding author

ABSTRACT

To enhance the performance and to minimize the limited bandwidth error occurred

in phase - locked loop, we proposed a method for modelling and behavioural simulation

of a 3rd order phase - locked loop by considering two 2nd order active filter topologies,

namely: (i) ideal multiple feedback approach, and (ii) filter with compensated multiple

feedback approach in the loop. The s – domain transfer functions are simulated by using

MATLAB to study the stability and different design aspects of the system. In ideal

multiple feedback approach, the operational amplifier produces errors into the

magnitude and phase responses of the filter because of limited gain bandwidth. To

overcome this problem, we have proposed a filter with compensated multiple feedback

approach in the loop.

Keywords: Damping factor, overshoot, phase margin, settling time, stability.

Cite this Article: Munmee Borah and Tulshi Bezboruah, A Novel Compensation

Method for Improving Error and Settling Time of A 3rd Order Phase-Locked Loop for

Communication System, International Journal of Advanced Research in Engineering

and Technology (IJARET), 11(7), 2020, pp. 11-20.

http://www.iaeme.com/IJARET/issues.asp?JType=IJARET&VType=11&IType=7

1. INTRODUCTION

Phase - locked loops (PLLs) are most commonly used in wireless communications, clock data

recovery, frequency synthesizers and signal processing [1] because of its synchronization

property between the input and output signal. Highly stable, fast settling time and low noise

PLL design is a very challenging task for designers. In many literatures it is reported that this

Munmee Borah and Tulshi Bezboruah


kind of PLL can be designed by using different PLL locking method, from all – digital phase

locking method to an analog integrated phase locking method [1]. The phase margin (PM), gain

margin (GM), overshoot and damping factor (DF) are key parameters which determine the

stability of the system. Also, the loop gain and loop bandwidth (BW) are two significant

parameters which measures the locking performance of a PLL. During frequency hopping in

mobile system, it protects the data or call from any kind of interference which required faster

lock time of the system [2].

Many researchers have been studied on measurement of settling time, PM, DF and

overshoot of PLLs. Tang et al. reported a new technique where loop BW was increased by 16

times and settling time achieved up to 260μs [3]. Cheng and Rasavi have designed a 2.4-GHz

radio frequency complementary metal oxide semiconductor (RF CMOS) synthesizer to achieve

a settling time around 60μs with channel spacing of 1MHz [4]. Staszewski and Balsara in [5],

introduced a fully digital frequency synthesizer to obtain an acquisition time of less than 50µs.

Roche et. al. reported a fast - settling PLL model by using 0.15µm CMOS technology, where

lock time of 0.9µs is achieved [6]. Yan et al. designed a mixed signal voltage controlled

oscillator (VCO) and a digital processor to obtain settling time less than 3μs [7]. Authors in [8],

proposed a behavioural model of dual cascaded PLL based frequency synthesizer and obtained

PM value of 46.8˚ and 81.3˚ at gain crossover frequency (ωgc) of 113rad/sec and 5rad/sec

respectively. In [9], the settling time is achieved less than 3μs by a 2.4GHz low power PLL

frequency synthesizer. In 2012, Lee and Masui, introduced a dual – band fractional – N PLL

synthesizer and they had obtained a settling time of 5µs, start-up time of 15µs and power of

3.5mW [10]. Laithy et al. proposed three techniques for controlling the 2nd order PLL. They

had recorded the lock time of 1.4ms, 0.5ms and 0.5ms for respective design techniques during

experiment [11]. Kalita et al. introduced a 3rd order PLL by considering active lag-lead filter

(ALLF) and filter with standard feedback approach (SFA) in the loop where settling time

recorded is in µs range [12]. Authors in [13], developed a new temperature compensated all

digital phase - locked loop (ADPLL) for reduction of settling time in the order of 3μs at 25˚C.

In the year 2016, J. Xie et al. has obtained settling time of 15μs by using 180nm CMOS based

ADPLL [14]. A fast settling time of 1.5µs fractional N – digital PLL (DPLL) with PM value in

the range of 20˚ - 80˚ is obtained by Paliwal et al. in the year 2016 [15]. Sohn and Shin presented

a fractional – N PLL synthesizer where lock time for entire tuning range was recorded to be

12.8µs [16]. In [17], the settling time achieved within the range of 1μs where they had proposed

a DPLL by using Multiple Lyapunov Functions (MLFs).

In this paper we have designed a 3rd order PLL by using two filter section in the loop,

namely: (i) filter in ideal multiple feedback approach (IMFBA), and (ii) filter with compensated

multiple feedback approach (CMFBA), to study the stability, transient behaviour and other

design aspect of the system.

2. MATHEMATICAL MODELING OF THE PROPOSED SYSTEM

The functional block diagram of the proposed system with both the filter approaches is shown

in Figure 1. The PLL is a self-correcting control system where the VCO output signal tracks

the input reference signal. The forward path of the loop consists of phase detector (PD), loop

filter (LF), and VCO. The frequency divider (FD) is in the feedback path of the system. The

function of PD is to compare both the input reference signal and output signal and to produce

an output voltage which is the input of the LF. The LF in the loop eliminates the noise and high

frequency component and generates tuning voltage for VCO [18, 19, 20]. The FD multiply the

reference

A Novel Compensation Method for Improving Error and Settling Time of A 3rd Order Phase-

Locked Loop for Communication System


Figure 1 Functional block diagram of the proposed system

Frequency by a factor N, where N is the frequency division ratio [18]. When phase/

frequency error is detected by the PD, it will produce a control voltage for VCO and it tunes

the VCO until the phase/ frequency of the oscillator and input reference signal become equal

[2]. When there is no phase/ frequency difference between the output signal and input reference

signal, then the PLL will acquire its locked state.

2.1. Estimation for PD

For linear operation of the system, PLL must be in its lock range and PD output voltage (VPD)

is a linear function of phase error (Δφ) and mathematically it can be written as:

)1(=PD

KPD

V

Where, KPD is the PD gain constant in volt/radian.

2.2. Estimation for LF

The LF smoothes and removes the harmonic terms and noise of the PD output. The lock range,

capture range, BW, transient response and switching speed in lock are controlled by LF [2, 21].

In this work, we have used two 2nd order active filter topologies in the loop as depicted in Figure

2(a) and Figure 2(b).

2.2.1. The transfer function of IMFBA filter

The transfer function (TF) for IMFBA filter can be derived as [22]:

Figure 2(a) 2nd order active IMFBA LF Figure 2(b) 2nd order active CMFBA LF

𝑇(𝑠)𝐼𝑀𝐹𝐵𝐴 =𝑎

𝐷2𝑠2+𝐷1𝑠+𝐷0

(2)

Where,

𝑎 =𝑅3𝑅1



𝐷2 = 𝐶1𝐶2𝑅2𝑅3

𝐷1 = 𝐶2(𝑅2 + 𝑅3 +𝑅2𝑅3𝑅1

)

𝐷0 = 1

2.2.2. The transfer function of CMFBA filter

The TF for CMFBA filter can be evaluated as [22]:

𝑇(𝑠)𝐶𝑀𝐹𝐵𝐴 =𝑏2

𝑃2𝑠2+𝑃1𝑠+𝑃0

(3)

Where,

𝑃2 =𝐶𝑅𝑏2𝐺𝐵𝑊

+ 𝐶2𝑅2𝑏1𝑏2𝑏3

𝑃1 =𝑏2

𝐺𝐵𝑊+

1

𝐺𝐵𝑊+ 𝐶𝑅𝑏1𝑏3 + 𝐶𝑅𝑏2𝑏3 + 𝐶𝑅𝑏1𝑏2𝑏3

𝑃0 = 1

2.3. Estimation for VCO

For linear analysis of the system, the VCO TF can be derived as:

𝐹(𝑠)𝑉𝐶𝑂 =𝐾𝑉𝐶𝑂

𝑠 (4)

Where, KVCO is the VCO gain constant in Hz/volt.

2.4. Estimation for FD

The TF for FD can be derived under the assumption that the FD is purely digital, as:

)5(1

Ndiv

F =

2.5. Estimation for system TF

The estimation for TF of the proposed system can be done as:

𝐻(𝑠)𝑠𝑦𝑠𝑡𝑒𝑚 =𝐾𝑃𝐷𝑇(𝑠)

𝐾𝑣𝑐𝑜𝑠

1+𝐾𝑃𝐷𝑇(𝑠)𝐾𝑣𝑐𝑜𝑁𝑠

(6)

Where,

𝐹𝑜𝑟𝑤𝑎𝑟𝑑 𝐺𝑎𝑖𝑛 = 𝐾𝑃𝐷𝑇(𝑠)𝐾𝑣𝑐𝑜𝑠

𝐿𝑜𝑜𝑝 𝐺𝑎𝑖𝑛 = 𝐾𝑃𝐷𝑇(𝑠)𝐾𝑣𝑐𝑜𝑁𝑠

Now, putting the TF of filter with IMFBA given in equation (2), in equation (6), the system

TF can be derived as:

𝐻(𝑠)𝐼𝑀𝐹𝐵𝐴 =𝐾𝑃𝐷 (

𝑎


)𝐾𝑣𝑐𝑜

𝑠

1 + 𝐾𝑃𝐷 (𝑎


)𝐾𝑣𝑐𝑜

𝑁𝑠




𝐻(𝑠)𝐼𝑀𝐹𝐵𝐴 =𝐾𝑃𝐷𝐾𝑣𝑐𝑜𝑎

𝑠3𝐷2+𝑠2𝐷1+𝑠𝐷0+

𝐾𝑃𝐷𝐾𝑣𝑐𝑜𝑎

𝑁

(7)

Similarly, putting the TF of filter with CMFBA given in equation (3), in equation (6), the

system TF can be expressed as:

𝐻(𝑠)𝐼𝑀𝐹𝐵𝐴 =𝐾𝑃𝐷 (

𝑏2


)𝐾𝑣𝑐𝑜

𝑠

1 + 𝐾𝑃𝐷 (𝑏2


)𝐾𝑣𝑐𝑜

𝑁𝑠

𝐻(𝑠)𝐶𝑀𝐹𝐵𝐴 =𝐾𝑃𝐷𝐾𝑣𝑐𝑜𝑏2

𝑠3𝑃2+𝑠2𝑃1+𝑠𝑃0+

𝐾𝑃𝐷𝐾𝑣𝑐𝑜𝑏2𝑁

(8)

3. SIMULATIONS

The stability of the system can be studied by simulating the TFs in an open state. To improve

the transient response and stability in terms of PM, GM and DF, the s – domain system TFs for

both filter approaches given in equation (7) and (8), are simulated in MATLAB. The stability

is analysed through bode plot and root locus analysis. The step responses are used to study the

settling time and system overshoot.

3.1. Simulation for PM, GM and system BW

The PM of a system is determined as the amount of additional phase angle at the gain crossover

frequency needed to lead the system to the margin of stability and it can be expressed as:

𝑃𝑀 = 1800 +𝜑𝑔𝑐 (9)

The GM is the reciprocal of the magnitude of the bode plot at phase crossover frequency

and it can be expressed as:

𝐺𝑀 =1

𝑀𝑝𝑐 (10)

Both PM and GM are used to measure the stability of a system. For stable PLL system, both

PM and GM should be positive and GM˃1. Additionally, phase angle of -180° must be avoided.

The BW is another most important design aspect of PLL and it is determined by the 3dB corner

frequency. The BW is interrelated with the parameters lock time, phase error and spur level.

Therefore, it is important to select BW in order to trade – off between the lock time and spur

level [23]. Another consideration to get proper BW is size of the LF capacitor. To analysis PM,

GM and loop BW, we deploy bode function and Figure 3(a) and Figure 3(b) shows the bode

responses for few test cases recorded during simulation.

3.2. Simulation for settling time and system overshoot

The settling time is a prime factor for PLL design that describes how fast a system switches

frequency from one to another without data lost. To design a fast settling time PLL, the loop

BW of the system should be widened. In this work, the settling time is depended on the LF

components, KPD, KVCO and division ratio N. A large value of overshoot makes system unstable.

To evaluate the settling time and system overshoot, we deploy the step function and a few

simulated sample step responses are shown in Figure 4(a) and Figure 4(b).



Figure 3(a) Simulated bode responses for PM and GM of IMFBA LF in the loop

Figure 3(b) Simulated bode responses for PM and GM of CMFBA LF in the loop

Figure 4(a) Simulated step responses for Settling time and overshoot of IMFBA LF in the loop




Figure 4(b) Simulated step responses for Settling time and overshoot of CMFBA LF in the loop

3.3. Simulation for DF

By using a higher value of DF, the stability of a system can be improved. The Root Locus

analysis is used to study the behaviour of DF of the proposed system. Few simulated responses

of root locus analysis are given in Figure 5(a) and Figure 5(b) for both the filter approaches in

the loop.

Figure 5(a) Simulated responses for DF of IMFBA LF in the loop

Figure 5(b) Simulated responses for DF of CMFBA LF in the loop



4. RESULTS AND DISCUSSION

The Table 1 and Table 2 show the simulation results for different design aspects of the system.

A system is said to be stable if its PM value is within the range of 20° - 80°[12, 23]. The PM of

the system with IMFBA in the loop recorded during simulation between 52.1° at ωgc =

1.23*107rad/sec and 75.9° at ωgc = 4.6*106 rad/sec. The GM obtained between 8.37dB at phase

crossover frequency ωpc = 2.06*107rad/sec and 20.4dB at ωpc = 1.58*107rad/sec. For the system

with CMFBA in the loop, the PM recorded are between 59.6° at ωgc = 1.44*108rad/sec and

77.1° at ωgc = 7.13*107rad/sec. On the contrary, GM recorded are between 25.9dB at ωpc =

5.05*108rad/sec and 51.1dB at ωpc = 2.31*109rad/sec. The minimum overshoot for the proposed

system with IMFBA in the loop is obtained to be 0% and loop with CMFBA is obtained to be

0.9797%. From the root locus analysis, it is seen that all the poles of the system TFs lie on the

left-hand side of s – plane and hence the system is stable. The DF is within the limit of stability.

The minimum settling time for the system with IMFBA and CMFBA in the loop is 0.35µs and

0.038µs respectively. The maximum settling time for the system with IMFBA and CMFBA in

the loop is 1.28µs and 0.115µs respectively.

Table 1 Simulation results for different design parameters of the system with IMFBA filter in the loop

SL

NO.

PM

(Degree)

GM

(dB)

Settling time

(µs)

Overshoot

(%)

BW

(MHz) DF

1 72.3 20.4 1.11 1.0380 0.48 0.8

2 75.9 14.9 1.28 0 0.48 0.9

3 57.3 10.2 0.82 0.3889 0.69 0.8

4 60.5 9.67 0.92 0 0.68 0.7

5 66.2 9.67 1.05 0 0.65 0.7

6 54.8 9.54 0.76 0.4287 0.75 0.8

7 56.2 11.2 0.63 1.8220 0.86 0.7

8 57.1 8.71 0.53 1.9990 1.23 0.7

9 52.1 8.37 0.44 0 1.36 0.7

10 55.6 9.40 0.35 0.0538 1.65 0.8

Table 2 Simulation results for different design parameters of the system with CMFBA filter in the

loop

SL NO. PM (Degree) GM

(dB)

Settling

time (µs)

Overshoot

(%)

BW

(MHz) DF

1 73.9 29.1 0.115 1.6042 4.51 0.7

2 74.1 35 0.076 1.3676 6.74 0.7

3 74.9 41.2 0.090 1.7624 5.71 0.7

4 67.9 33.5 0.082 4.10 11.36 0.7

5 73.2 25.9 0.046 1.5515 11.37 0.7

6 69.2 51.1 0.068 3.9781 13.50 0.7

7 70.8 35.5 0.038 3.0197 2.260 0.7

8 77.1 33.2 0.064 0.9797 7.990 0.8

9 59.6 27.1 0.058 7.6924 1.820 1

10 64.8 32.7 0.091 5.5020 10.90 1




Table 3 Comparison table for different design parameters of the proposed system

SL

NO. Previous work

Settling time

(µs)

PM

(Degree) DF

Overshoot

(%)

1 REF [6] 0.9 - - -

2 REF [8] - 46.8 – 81.3 - -

3 REF [9] 3 - - -

4 REF [10] 5 - - -

5 REF [11] 0.5ms, 1.4ms - - -

6 REF [12] (ALLF LF) 0.139- 69.5 41.7 – 78.2 0.5 – 0.8 2.17 – 14.9

7 REF [12] (SFA LF) 0.11 – 4.47 45.1 – 72.2 0.6 3.41 – 9.25

8 REF [13] 3 - - -

9 REF [14] 15 - - -

10 REF [15] 1.5 20 – 80 - -

11 REF [16] 12.8

12 REF [24] (ALLF LF) 0.668- 1.02 60.3 – 77 0.5 – 0.6 6.01 – 11.8

13 REF [24] (SFA LF) 0.104- 484 57.1 – 67.2 0.5 – 0.7 6.30 – 9.91

14 Proposed

work

IMFBA LF 0.35– 1.28 52.1 – 75.9 0.7 – 0.8 0 – 1.999

CMFBA LF 0.038– 0.115 59.6 – 77.1 0.7 - 1 0.9797 –

7.9624

5. CONCLUSION

From the analysis of the proposed system carried out through evaluation of s – domain TFs, we

can conclude that the settling time metrics for the system by considering the loop with CMFBA

is faster than the filter with IMFBA in the loop and enhances the speed up to 0.038µs as

compared to the earlier work done by other researchers in the field. Additionally, the system

with CMFBA gives superior stability in terms of PM, GM and DF. The system for both the

filter approaches in the loop fulfilled the Root Locus stability criterion and hence the system is

stable. Based on this investigation it can be concluded that the system developers may use it for

their own high frequency and fast settling time communication systems as trade – off where

required.

ACKNOWLEDGMENTS

This publication is an outcome of the research and development work undertaken through a

project under the Visvesvaraya PhD Scheme of Ministry of Electronics & Information

Technology, Government of India, being implemented by the Digital India Corporation (Grant

no: MLA/MUM/GA/10(39) dated 12-03-2018).

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