A Normally-on MOSFET Compact Model based on Surface Potential Description

D. Navarro, T. Iizuka, T. Umeda, Y. Hirano,

H. Kikuchihara, M. Miura-Mattausch and H. J. Mattausch

HiSIM Research Center, Hiroshima University

MOS-AK

Dec. 6, 2017

Normally-on MOSFET

Vds

Vgs

Vbs

Tn

0V

gs(V)

Dra

in c

urr

ent

(A)

• Normally-on (depletion-type) MOSFET is one descendant

of MOSFET used for low-power analog circuits.

• A prominent feature is the large leakage current at Vbs= 0

that creates the normally-on condition.

-Vbs

2

Cu

rren

t (1

0-5A

)

10

5

0

Vgs

(V)

Vds

= 0.1 (V)

-1-2-3 3210

280

230

Tn=180nm

Ires

Iacc

Ids

Vgs

(V)

0

10

Cu

rren

t (1

0-4A

)

Vds

= 5 (V)

-1-2-3 3210

280

230

Tn=180nm

Ires

Iacc

Ids

• Accumulation-mode current (Iacc)

at the surface

• Resistor current (Ires) within the

neutral region beneath the surface

Vds

Vgs

Vbs

Tn

Composite description of current.

Normally-on MOSFET Characteristics

3

Vgs=-1V

Vds=0.1V, Vbs=0

Ws

Wb Wres

Ires

Vgs=2V

Wb

Ires

Iacc

Buried Layer Dynamics at Low Vds

Neutral region has a complex bias dependency. 4

V bs V th

0 -0.592

-1V -0.532

-2V -0.471

-3V -0.410

-4V -0.351

V bs V th

0 -0.626

-1V -0.630

-2V -0.638

-3V -0.651

-4V -0.656

Low Vds

High Vds

No dependence on

Vbs at accumulation.

Iacc and Ires can be

separated.

With Vbs

dependence.

Iacc and Ires cannot

be separated.

切片

Threshold Voltage Characteristics

5

Vds=5V, Vbs=0

Vgs=-1V

Ws

Wb

Vgs=-1V

Vds=0.1V, Vbs=0

Ws

Wb Wres

Ires

High Vds

Low Vds

Short-channel Effects

Pinch-off occurs.

6

• Composite currents:

Accumulation-mode current(Iacc) and Resistor current (Ires)

• Bias-dependence of the neutral region within the buried

layer

Surface-potential-based modeling

Modeling of Normally-on MOSFET

7

Gate DrainSource

x

y

Gate Drain

Gradual-Channel

Qi

Wd

𝜙S0 𝜙SL𝜙S0

𝜙SL𝜙S(Δ𝐿)

𝜙S0+𝑉ds∆𝐿

HiSIM

Potentials at important locations are solved.

• Hiroshima University STARC IGFET Model

(HiSIM. HiSIM_HV, HiSIM_SOI, HiSIM_SOTB)

• Surface-Potential-Based Compact Model

Compact Model: HiSIM

8

SOI-MOSFET

MG-MOSFET

TFTSOTB-MOSFET

MOS-Varactor

MOSFET HV-MOSFET

IGBT

(CMC Standard 2011) (CMC Standard 2009)(CMC Standard 2012)

(CMC Standard 2014)

Organic FET

P-i-N Diode

HiSIM Family of Models

9

j?sQ bQ

subQ

𝑑2𝜙

𝑑𝑥2= −

𝜌

𝜀s

𝜌 = 𝑄s + 𝑄b + 𝑄sub

𝑄𝑠 = ±𝑐𝑛𝑠𝑡0 𝑒𝑥𝑝 𝛷 − 1 − 𝛷 + 𝐶𝑁𝑇

𝛷 = 𝜙s − 𝜙b 𝐶𝑁𝑇 = 𝑐𝑛𝑠𝑡1 𝑒𝑥𝑝 −𝛽𝜙s − 𝑒𝑥𝑝 −𝛽𝜙b

𝑄𝑏 = 𝑞𝑁dep2𝜀s

𝑞𝑁dep𝜙b − 𝜙j 𝑄sub = 𝑞𝑁dep

2𝜀s𝑞𝑁sub

𝜙j − 𝑉bs + 𝑉bi

𝑐𝑛𝑠𝑡0 = Τ2𝜀s ∙ 𝑞 ∙ 𝑁dep 𝛽 𝑐𝑛𝑠𝑡1 = ൗ𝑛i2 𝑁𝑑𝑒𝑝

2

Modeling of Potential Distribution

fj

10

source drain

Modeling Results

Potential Distribution

HiSIM

Device Sim.

fb

fs

fj

Potential distribution is verified using 2D device simulation.

11

𝐼ds = 𝐼acc + 𝐼res

𝐼acc =𝑊eff,nf

𝐿ch∙1

𝛽𝜇 ∙ 𝐼dd 𝐼𝑑𝑑 = −𝛽

𝑄n0 + 𝑄nl2

∙ 𝜙ds − 𝑄n0 + 𝑄nl

0

CB PH SR

1 1 1

uesurfaceSR

eff

MUESR1M

E

uephonon

PH MUEPH0

eff

M

E

n0

CB 11MUECB0 MUECB1

10

Q

q

n0

Si

eff

SL S0 invde

NINV

1

Q

EN

f f

0

1BB BB

0 y

max

1E

V

Current Components

Accumulation Current (Iacc)

Universal Mobility High-field mobility

- governed by conventional MOSFET physics.

12

Short-Channel Effect

S SL S0 ds( ) 1 CLM1 CLM1L Vf f f

2 2dd subS SL 0

eff i Si

2

2 2 2 2dd sub subS SL 0 S SL 02

eff i Si Si

12 2

1

2 12 2 4 2

I Nz L z E z

L QL

I N Nz L z E z L z E z

L Q

f f

f f f f

Gate Drain

Gradual-Channel

Qi

Wd

𝜙S0

𝜙SL𝜙S(Δ𝐿)

𝜙S0+𝑉ds∆𝐿

CLM56

gate1 CLM6 10L L L

Effect of lateral field is considered. 13

res eff

res res res ds

eff

W WI q N V

L

res n s bW T W W

Si 0 sub

b bi bs

n n sub

2 NW V

qN N N

f

Si 0s res

n

2W

q N

f

0leak,res

leak,res 1DEPBB DEPBB

0leak,res y

vmax

1E

DEP

ds,res

y

ch DEPRDRDL2

VE

L

0leak,res mue0DEP

Resistive Current (Ires)- governed by potential difference between source and drain.

Vgs=-1V

Vds=0.1V, Vbs=0

Ws

Wb Wres

Ires

14

Resistive Current (Ires) at High Vds

2

n Si oxf max gp gp2

ox n Si

1 1 2qN C

V VC qN

f

Potential at the pinch-off point

15

0

1

2

3

4

5

6

-6 -4 -2 0 2 4 6

Ids (10 µA)

Vgs (V)

Measurement

Compact model

Vbs

=0,-1,-2,-3,-4 V

10-16

10-14

10-12

10-10

10-8

10-6

10-4

10-2

-6 -4 -2 0 2 4 6

Ids (A)

Vgs (V)

0

0.2

0.4

0.6

0.8

1

-6 -4 -2 0 2 4 6

gm (10-5A/V)

Vgs (V)

Low Vds

I ds

(μA

)

I ds

(A)

gm (

10

-5 A

/V)

Vgs (V) Vgs (V) Vgs (V)

gm

Ids-Vgs characteristics at low Vds

Good agreement with measurements is verified.

16

0

0.2

0.4

0.6

0.8

1

1.2

-6 -4 -2 0 2 4 6

Ids (10-3A)

Vgs (V)

Measurement

Compact model

Vbs

=0,-1,-2,-3,-4 V

10-16

10-14

10-12

10-10

10-8

10-6

10-4

10-2

-6 -4 -2 0 2 4 6

Ids (A)

Vgs (V)

0

1

2

3

-6 -4 -2 0 2 4 6

gm (10-4 A/V)

Vgs (V)

High Vds

Vgs (V) Vgs (V) Vgs (V)

gm (

10

-4 A

/V)

I ds

(μA

)

I ds

(A)

gm

Ids-Vgs characteristics at high Vds

Good agreement with measurements is verified.

17

Thick surface layer Thin surface layer

0

5

10

15

-6 -4 -2 0 2 4 6

Tn=180n100n

50n

0

5

10

15

-6 -4 -2 0 2 4 6

Tn=180n100n

50n

Compact model

Vgs (V)

Vgs (V)

Cgg

(fF

)C

gg

(fF

)

Partial depletion in the

surface layer.

Capacitive coupling

between gate and surface

layer (n-type).

Full depletion in the

surface layer.

Capacitive coupling

between gate and

substrate (p-type).

Capacitance Characteristics

18

• A compact model for normally-on MOSFET is developed.

• Surface-potential-based approach to model the device

captures device behavior consistently. The current and

capacitance characteristics are verified against

measurements and device simulation.

• The modeling approach is a viable solution for all

technology generations.

Summary

19