IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 1, JANUARY 2012 241

A New Charge-Pumping Technique for aDouble-Gated SOI MOSFET Using

Pulsed Drain Current TransientsSungho Kim, Sung-Jin Choi, Dong-Il Moon, and Yang-Kyu Choi

Abstract—A novel interface characterization technique is pro-posed to extract interface trap density Nit in fully depletedsilicon-on-insulator MOSFETs. The proposed technique utilizesthe temporal variation of the drain current, which is caused bythe application of a single pulse to the gate in order to triggercharge pumping (CP). Vacant interface traps created as a resultof recombination through the CP effect are gradually filled by car-riers generated from a floating body (FB). By the characterizationof this transient phenomenon, the interface trap density is directlyextracted from FB devices without extra body contacts.

Index Terms—Charge pumping (CP), drain current transient,floating body (FB), interface trap, silicon-on-insulator (SOI)MOSFET.

I. INTRODUCTION

INTENSIVE studies of floating-body (FB) devices, suchas nanowire FETs, thin-film transistors, vertical channel

FETs, and silicon-on-insulator (SOI) MOSFETs, have beenmotivated by their superiority over bulk devices in terms ofthe performance and the prospect of 3-D integration. Theperformance and the reliability of these FB devices are stronglydependent on their interface states due to the increased surface-to-volume ratio as device scaling-down advances. Traditionally,the charge-pumping (CP) technique has been widely appliedto analyze the interface states in bulk MOSFETs [1], [2].Unfortunately, the conventional CP technique cannot be usedfor the characterization of FB devices due to the lack of bodycontacts. Therefore, demand is strong for a new CP techniquedirectly applicable to FB devices.

So far, specially designed device structures, which includean extra body contact [3] or gated-diode-like devices [4], haveinstead been used for CP measurements in FB devices. In addi-tion, measured CP current ICP is proportional to the channel

Manuscript received April 24, 2011; revised September 7, 2011; acceptedOctober 4, 2011. Date of publication October 31, 2011; date of current versionDecember 23, 2011. This work was supported in part by the Center forNanoscale Mechatronics and Manufacturing, one of the 21st Century FrontierResearch Programs supported by the Korean Ministry of Education, Scienceand Technology (MEST), under Grant 08K1401-00210; by the Nano R&Dprogram through the National Research Foundation of Korea funded by MESTunder Grant 2010-0018931; by the IT R&D program of Ministry of KnowledgeEconomy/Korea Evaluation Institute of Industrial Technology (10029953, Ter-abit Nonvolatile Memory Development); and by Samsung Electronics Co., Ltd.The review of this paper was arranged by Editor J. S. Suehle.

The authors are with the Department of Electrical Engineering, KoreaAdvanced Institute of Science and Technology (KAIST), Daejeon 305-701,Korea (e-mail: ykchoi@ee.kaist.ac.kr).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2011.2171489

area, which is typically too small to measure in nanoscaledevices. Thus, a multifin structure has been required to enlargethe channel area in the case of FinFETs [5]. However, thesetypes of approaches require additional fabrication processesand are associated with several geometric problems. To over-come the limitations of the use of conventional CP, Okhoninet al. proposed a specific CP technique known as transient CP[6]. Transient CP introduces an impact ionization process tosupply majority carriers into the FB without the body contact.However, due to the impact ionization process, unnecessaryinterface traps can be generated during the CP measurement,which may result in inaccuracies. In addition, the surfacepotential of the back interface between the buried oxide of theSOI and the FB is also affected by the CP pulses applied tothe gate. Consequently, interface traps not only in the frontinterface but also in the back interface contribute to the CPeffect, thus increasing the level of uncertainty during the dataextraction procedures.

In this study, a refined CP technique is proposed, whichovercomes weaknesses of the conventional and transient CPtechniques. The proposed technique uses the established CPprinciple to extract interface trap density Nit from fully de-pleted FB MOSFETs directly. In contrast with the conventionalCP technique, in the proposed technique, a continuous supplyof majority carriers is not required for the CP effect, whichallows the extraction of Nit even in FB devices without a bodycontact. In detail, one side of the FB (the front interface) isaccumulated, and the other side of the FB (the back interface)is strongly inverted. Majority carriers that accumulate at thefront interface are removed by a single CP pulse. In addition,the interface traps tend to be vacant through a recombinationprocess during the application of the CP pulse. Thereafter, thesudden depletion of majority carriers induces a nonequilibriumcharge imbalance state inside the FB, which results in variationof the temporal drain current. Due to the lack of a bodycontact, majority carriers are gradually generated from the FBand fill the interface traps again. Consequently, the temporarilychanged drain current tends to return to its initial value, i.e.,an equilibrium state. An analysis of this temporal drain currentvariation is conducted to determine Nit with the aid of a derivedanalytical model.

Section II describes the analysis of the transient drain currentcharacteristics and the derivation of the analytical model forthe extraction of Nit. Experimental results from independentdouble-gate SOI MOSFETs are shown in Section III.

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242 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 1, JANUARY 2012

Fig. 1. (a) Cross-sectional view of the device for an explanation of the measurement setup. (b) Condition of the accumulated holes and trapped carriers insidethe interface trap according to the applied single CP pulse. (c) Resulting drain current transient. (d) Simulated drain current transient characteristics for differentNit values. Here, in all of the simulation results, the assigned energy level of interface traps is such that the distribution of the acceptor-type interface states iscentered 0.2 eV above the valence band maximum (Ev + 0.2 eV). In addition, the donor-like distribution is centered 0.2 eV below the conduction band minimum(Ec − 0.2 eV). These traps are distributed across the bandgap in a delta-function-like manner, which is consistent with the double-peak response near the bandedge [13], [14].

II. ANALYSIS OF THE TRANSIENT CHARACTERISTICS

As shown in Fig. 1(a), an explanation of the operation prin-ciples is provided with the case of an n-channel FB MOSFETas an example. The device is biased with positive voltage VG2

that exceeds threshold voltage VT so that the back interfaceis strongly inverted and the back surface potential is approxi-mately pinned at 2φF (φF = kT/q · ln(NA/ni), where NA isthe doping concentration of the FB. A negative voltage at thefront gate (VG1(t < 0)) accumulates holes at the front inter-face, and the front surface potential is approximately pinned atzero. A small drain bias (VD = 50 mV) is applied to monitorthe resulting transient drain current. Nit at the front interfaceis characterized using this technique; however, the roles ofthe two electrodes, namely, gate 1 (front gate) and gate 2(back gate) electrodes, are interchangeable. Hence, this setupis also applicable to analyze Nit at the back interface, e.g., theSi/buried oxide interface of the SOI substrate. In the case ofa p-channel device, the bias polarities of the aforementionedvoltages are reversed.

The system maintains an equilibrium state until t < 0. Then,a single CP pulse is applied to the gate at time t = 0, as shownin Fig. 1(b). The low level of the pulse should be lower thanthe flatband voltage (VL < VFB), and the high level of thepulse should be higher than the threshold voltage (VH > VT )to enable the CP effect, as is common in the conventionalCP technique. While VG1 = VH , holes that accumulate at thefront interface are depleted due to the inverted channel, and

trapped holes are recombined due to the CP effect. At thesame time, inversion electrons are trapped at the interface traps.After VG1 returns to VL, trapped electrons are swept out to thesource/drain electrode, and interface traps are vacant. Simulta-neously, this disturbance (VG1 returns to VL) creates a demandfor holes at the front interface to sustain the charge balanceaccording to the negative gate bias. However, holes cannot bepromptly supplied due to the absence of a body contact; thus,the system enters a nonequilibrium state. For this reason, imme-diately after the pulse is applied (t ∼ 0), the demand for holesis temporarily offset by the removal of electrons from the backinversion channel, resulting in a decrease of the drain current,as shown in Fig. 1(c). In other words, the body potential dropsin deep depletion and suppresses the back inversion channel[7], [8]. This temporal drain current variation phenomenon hasbeen observed and used to estimate the carrier lifetime in aSOI MOSFET [9]–[12]. As electron-hole pairs are graduallygenerated from the FB after t > 0, the holes drift toward thefront interface, whereas the electrons make up for carriers inthe back inversion channel. Subsequently, the temporal draincurrent variation (ID(t)) recovers to its initial equilibrium state(ID,sat).

The holes generated from the FB accumulate again at thefront interface. Thereafter, these holes fill the empty interfacetraps. Thus, generation rate G of a hole is the sum of: 1) therate of change of the concentration of holes (Nhole) at the frontinterface and 2) the rate of hole trapping (Ntrapping) in the

KIM et al.: CP TECHNIQUE FOR A DOUBLE-GATED SOI MOSFET USING DRAIN CURRENT TRANSIENTS 243

Fig. 2. (a) Schematic of the midgap and quasi-Fermi-level distribution acrossthe FB in an equilibrium state, in a nonequilibrium state following the ap-plication of the CP pulse, and a definition of the effective generation width.(b) Simulation of energy bands across the FB for different times during therelaxation transient.

interface traps. Fig. 1(d) shows the simulated transient draincurrent characteristics with different Nit values. Here, moreholes are needed to fill the interface traps as Nit increases,resulting in a delayed drain current recovery time (ttrap). It isassumed for simplicity of the model that the hole trapping lin-early occurs within ttrap; hence, Ntrapping can be expressed as

Ntrapping(t) =Nit

ttrapt.

Generation rate G can be determined from the continuity equa-tion [15]

G =ni

τgWg + nisg ≈ ni

τgWg

=dNhole

dt+

dNtrapping

dt

=dNhole

dt+

Nit

ttrap(1)

where τg is the generation lifetime, ni is the intrinsic carrierconcentration in the silicon film, and Wg is the effective gener-ation width, as depicted in Fig. 2(a). Surface generation rate sg

is neglected here as the back interface remains strongly invertedand because the hole trapping process occurs mainly at the frontinterface throughout the transient.

To calculate Wg analytically, the energy band shift of the FBshould be considered when the system is in a nonequilibriumstate. Due to the sudden hole depletion at the front interfaceby the single CP pulse, the systems enter into a nonequilibriumstate, which leads to an upward shift of the electrostatic poten-tial, as shown in Fig. 2(a). This nonequilibrium state leads toa net generation of carriers in an attempt to restore equilibriumwhile 0 < t < ttrap (the subscript “sat” denotes the equilibriumstate after t ≥ ttrap). For an analysis of this potential shift, thelinear potential approximation is adapted. This was also verifiedby simulations [16], as shown in Fig. 2(b).

Essentially, the analytical derivation procedure of Wg is veryclose to that in [11]. Therefore, detailed derivation steps of

analytical model are not described, and only the differencebetween [11] and this work is discussed here. In [11], a negativestep voltage (−6 to −20 V) is applied to the front gate at timet = 0, which leads to variation in the temporal drain current.In this case, the interface traps at the front interface are notvacant due to the CP effect because the interface is continuouslyaccumulated after t ≥ 0. Therefore, generation rate G canbe described without consideration of Nit, G = (ni/τg)Wg =dNhole/dt. On the other hand, in the proposed technique, asingle CP pulse is applied to the front gate. This pulse inducesan inversion layer at the front interface and consequently theCP effect. Because the interface traps are vacant due to thisCP effect, generation rate G should include the effect of Nit,as given in (1). As a result, using generation rate G given in(1) and derivation steps described in [11], we can obtain theanalytical model of the transient drain current. Thus

(Coxf + CSi)2qniC2

Si

d

dt[KID(t) − Coxb(VG2 − 2φF )]2

=tSiK

τgCSi(ID(t) − ID,sat) −

Nit

nittrap(2)

where K = L/(µWVD), tSi is the FB thickness, µ denotes mo-bility, W is the channel width, and L is the gate length. Plottingthe left-hand side (LHS) of (2) as a function of (ID(t) − ID,sat)results in a straight line, after which τg can be evaluated fromthe slope, and Nit can be extracted from the y-axis intersect.Here, it should be noted that the derived model given by (2) isonly valid in a fully depleted case.

III. SIMULATION AND EXPERIMENT

An independent double-gate FinFET (IG-FinFET) was usedto demonstrate the proposed CP technique as an analysis toolfor the extraction of Nit. The process flow and the structure areequal to that of an earlier IG-FinFET reported in the literature[17]. In brief, as a starting material, a SOI wafer whose channeldoping was adjusted by boron at a concentration of 1018 cm−3

was used. The fin height (here, this refers to channel widthW ) was 100 nm, and the fin width (referring to FB thicknesstSi) was 40 nm. A chemical-mechanical polishing process wasutilized to form the independently controllable gate 1 and gate2. Tetraethyl orthosilicate oxide with a thickness of 20 nm (toxf

and toxb) and n+ in situ doped polycrystalline silicon wereused as a gate dielectric and a gate electrode (LG = 700 nm),respectively. Here, it should be noted that the technique pro-posed is also feasible for use with a planar SOI MOSFETstructure comprised of a front gate and a controllable back gateunderneath the buried oxide.

In an effort to verify the validity of the analysis, severalsimulations were carried out. Fig. 3(a) shows the simulatedtransient drain current characteristics with different Nit and τg

values. It can be clearly seen that the initial slope of ID(t) isseverely affected by the change in τg . As τg is increased, theinitial slope of ID(t) curve is decreased due to the reduction inthe generation rate (a generation rate is inversely proportionalto τg). On the other hand, the slope of ID(t) is rarely affectedby the change in Nit. It can be understood from (2) that the

244 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 1, JANUARY 2012

Fig. 3. (a) Simulated transient drain current curves according to the different τg and Nit. (b) Temporal variation of effective generation width Wg as predictedby the derived model and from the simulation.

slope of ID(t) (LHS of the equation) is dominantly determinedby τg , whereas the change in Nit leads to a parallel shift ofID(t) curve. This characteristic implies that the proposed tech-nique can monitor changes in τg and Nit independently. Theexperimental investigation of the relationship among ID(t),Nit, and τg will be discussed later (see Fig. 5). Fig. 3(b) showsa comparison of generation width Wg as a function of timedirectly obtained from the simulation and via the derived model.It is clear that the value of Wg calculated from the derivedmodel is inconsistent compared with that from the simulation.This is caused by the linear potential approximation, in whichthe real potential is not perfectly linear inside the FB. However,for devices with moderate doping and the types of thin filmstypically used as a channel, the linear potential approximationhas been shown to be valid [18]. Therefore, the discrepancyassociated with Wg can be considered as negligible whenextracting Nit.

Fig. 4(a) shows the measured drain current transient and sim-ulation results for different values of τg . The front interface isaccumulated by VG1 = −3 V, and the back interface is stronglyinverted by VG2 = 5 V. Small drain bias (VD = 50 mV) isapplied to monitor transient drain current ID(t). After a singleCP pulse (1 µs, ±3 V) is applied to gate 1, ID(t) is measured asa function of time by using an oscilloscope. Next, plotting theLHS of (2) as a function of (ID(t) − ID,sat) using the measureddata produces a fairly straight line, as shown in Fig. 4(b). Fromthe slope and y-axis intersect, the extracted value of τg is 0.23µs and that of Nit is 1.57 × 1011 cm−2, both of which are wellmatched to the expected values in the simulation; the simulationdata demonstrate that the case in which τg = 0.2 µs has the bestfit to the measured data. Therefore, it can be concluded that theproposed technique is valid for extracting Nit values.

To check the validity of the proposed technique, measure-ments were carried out before and after a forming gas annealingprocess. Fig. 5 exhibits the measured drain current transientresults obtained after the annealing process. After the annealingprocess, ttrap is reduced, whereas the initial slope of ID(t)is not changed. It can be understood from the aforementionedanalysis discussed in Fig. 3(a). This arises because the interfacequality is improved by the annealing process; however, trapsor defects are neither alleviated nor cured inside the FB bulk

Fig. 4. (a) Measured drain current transient and simulated data for differentτg values. (b) Plot of the measured data to extract τg and Nit according to (2).

region. Accordingly, Nit is reduced by the annealing process,but τg maintains its value. The extracted value shows that Nit isreduced to 6.11 × 1010 cm−2, whereas the extracted value of τg

is nearly unchanged, which is consistent with our expectations.This result reveals the feasibility of the proposed method in thatthe technique can monitor changes in bulk defects inside the FBas well as in the interface traps separately from the extractedτg and Nit values. This would be an attractive benefit wheninvestigating FB devices that are composed of a polycrystallineor an amorphous channel material.

KIM et al.: CP TECHNIQUE FOR A DOUBLE-GATED SOI MOSFET USING DRAIN CURRENT TRANSIENTS 245

Fig. 5. Measured drain current transient results obtained after the forming gasannealing process.

IV. CONCLUSION

In summary, a novel CP technique was demonstrated toquantify the interface trap density in FB devices. This techniqueovercomes a limitation associated with conventional CP in thatinterface trap density Nit can be directly extracted without extrabody contact structures. An analytical model was also devel-oped for the extractions, and numerical simulations supportedits validity. Moreover, the proposed technique has the potentialto provide information pertaining to bulk defects inside theFB through extracted generation lifetime τg . This can be abenefit when investigating FB devices that are composed of apolycrystalline or an amorphous channel material.

However, it should be noted that the derived model forthe proposed technique in this time did not consider short-channel or any parasitic effects. This simple model may includesome errors, particularly in sub-100 nm devices. This needsfurther consideration including the corrected device model withcomprehensive physical analyses, which will be discussed in alater study. In addition, the coexistence of a front accumulationcharge and a back inversion charge cannot be accommodatedin an extremely thin FB film (e.g., <10 nm), which has beenknown as super-coupling effect [19]. Accordingly, the applica-tion of the proposed technique can be restricted by the bodythickness, which should be considered.

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[4] T. Ouisse, S. Cristoloveanu, T. Eleva, H. Haddara, G. Borel, andD. E. Ioannou, “Adaptation of the charge pumping technique to gated p-i-ndiodes fabricated on silicon on insulator,” IEEE Trans. Electron Devices,vol. 38, no. 6, pp. 1432–1444, Jun. 1991.

[5] G. Kapila, B. Kaczer, A. Nackaerts, N. Collaert, and G. V. Groeseneken,“Direct measurement of top and sidewall interface trap density in SOIFinFETs,” IEEE Electron Device Lett., vol. 28, no. 3, pp. 232–234,Mar. 2007.

[6] S. Okhonin, M. Nagoga, and P. Fazan, “Principles of transient chargepumping on partially depleted SOI MOSFETs,” IEEE Electron DeviceLett., vol. 23, no. 5, pp. 279–281, May 2002.

[7] M. Bawedin, S. Cristoloveanu, D. Flandre, and F. Udrea, “Dynamicbody potential variation in FD SOI MOSFETs operated in deep non-equilibrium regime: Model and applications,” Solid State Electron.,vol. 54, no. 2, pp. 104–114, Feb. 2010.

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[12] D. Munteanu, D. A. Weiser, S. Cristoloveanu, O. Faynot, J.-L. Pelloie,and J. G. Fossum, “Generation-recombination transient effects in partiallydepleted SOI transistors: Systematic experiments and simulations,” IEEETrans. Electron Devices, vol. 45, no. 8, pp. 1678–1683, Aug. 1998.

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Sungho Kim received the B.S. and M.S. degreesfrom Korea Advanced Institute of Science and Tech-nology (KAIST), Daejeon, Korea, in 2006 and 2008,respectively. He is currently working toward thePh.D. degree in electrical engineering at KAIST.

His current research interest is in trap characteri-zation using charge-pumping technique.

Sung-Jin Choi received the B.S. degree in elec-tronics and electrical engineering from Chung-AngUniversity, Seoul, Korea, in 2007 and the M.S. de-gree from Korea Advanced Institute of Science andTechnology (KAIST), Daejeon, Korea, in 2008. Heis currently working toward the Ph.D. degree inelectrical engineering at KAIST.

His current research interests include Schottkybarrier devices, capacitorless dynamic random ac-cess memory, biosensors, and nanowire electronics.

246 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 1, JANUARY 2012

Dong-Il Moon received the B.S. degree fromKyungpook National University, Daegu, Korea, in2008. He is currently working toward the M.S. de-gree in electrical engineering at Korea AdvancedInstitute of Science and Technology, Daejeon, Korea.

His current research interests include silicon pho-tonic device and capacitorless 1T-DRAM rangingfrom device design to process development, simula-tion, and characterization.

Yang-Kyu Choi received the B.S. and M.S. degreesfrom Seoul National University, Seoul, Korea, in1989 and 1991, respectively, and the Ph.D. degreefrom the University of California, Berkeley, in 2001.

From January 1991 to July 1997, he was a ProcessIntegration Engineer with Hynix Semiconductor,Inc., Kyungki, Korea, where he developed 4-, 16-,64-, and 256-M dynamic random-access memorydevices. He is currently a Professor with the Divisionof Electrical Engineering, School of Electrical En-gineering and Computer Science, Korea Advanced

Institute of Science and Technology, Daejeon, Korea. His research interests aremultiple-gate metal–oxide–semiconductor (MOS) ?eld-effect transistors, ex-ploratory devices, novel and uni?ed memory devices, nanofabrication technolo-gies for bioelectronics, and nanobiosensors. He has also worked on reliabilityphysics and quantum phenomena for nanoscale complementary MOS. He hasauthored or coauthored over 130 papers and is the holder of seven U.S. patentsand 100 Korea patents.

Dr. Choi was the recipient of the Sakrison Award for the Best Dissertationfrom the Department of Electrical Engineering and Computer Sciences, Uni-versity of California, in 2002. He was also the recipient of “The Scientist ofthe Month for July 2006” from the Ministry of Science and Technology inKorea. His biographic pro?le was published in the 57th Marquis Who’s Who inAmerica.