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A Method to Accelerate SoCImplementation Cycle by Automatically
Generating CDC constraints
Ashish Hari, Sulabh Kumar Khare
© Accellera Systems Initiative 1
Agenda SOC implementation challenge with CDC paths Typical Design flow in presence of CDC paths Limitations of traditional methods Proposed automatic CDC constraints generation
method Interpreting SDC constraints from CDC infromation Results Conclusions
© Accellera Systems Initiative 2
SOC implementation challenge with CDC pathsIncreasing
System Integration
Increasing Peripherals and
External Interfaces
Complex Power Management
for Low Power
More clocks More number of
Domain crossing paths
Increased effort forSOC implementation
Time to MarketCompromised
Incorrect constraints Causing Chip failures
Typical Design flow in presence of CDC paths
4
Setup
Synthesis
RTL
SDCnetlist
STA
SDCnetlist
Place and Route
SDCnetlist
Maximum delay requirement of CDC paths violated
False Negative slack for CDC paths
Synchronizer flops placements issues
Limitations of Traditional methods
• Rely on manual work to define constraints for CDC paths– Error prone– Iterative and time consuming
• No single place to capture CDC intent in constraints– CDC paths generate false errors
• Constraints added to ignore these paths
– Some CDC paths may never be captured• May escape unconstrained
© Accellera Systems Initiative 5
Proposed flow: Automatic generation of CDC constraints
• SDC (Synopsys Design constraints) is standard for capturing design constraints
• Extend CDC tool to generate CDC constraints for Implementation tools in SDC format
• Avoid multiple iterations due to manual constraints• Ensures CDC paths are handled correctly in synthesis,
STA and place & Route
© Accellera Systems Initiative 6
Inputs and Outputs of CDC tools
© Accellera Systems Initiative 7
• Takes RTL and Constraints as input• Once CDC verification is complete:
• Complete CDC constraints are available
RTL Constraints
CDC Verification
DB Reports SDC
Proposed automatic CDC constraints generation flow
© Accellera Systems Initiative 8
Setup
Synthesis
RTL
SDCnetlist
STA
SDCnetlist
Place and Route
SDCnetlist
CDC
SDCStart with CDC constraints as part of SDC
CDC Paths constraints:Correct by construction
Interpreting SDC from CDC information
• Components of CDC to capture:1. Clock and clock groups2. Port constraints3. False path (CDC crossing)4. Constants5. Maximum delay for synchronizer flops
• Each component can be specified using SDC commands
© Accellera Systems Initiative 9
SDC for CDC constraints: Clocks
• Defining clocks• Defining asynchronous clock domains
© Accellera Systems Initiative 10
create_clock : Specifies primary Clockscreate_generated_clock : Specifies derived clocks
Infer all clocks as synchronous by default.
Asynchronous domain categorization -set_clock_groups -asynchronous –group <clocks>
create_clock -name CLK_11 -period 90 -waveform { 0 45 } { CLK_11 }create_clock -name PHY_rx_clk -period 90 -waveform { 0 45 } { PHY_rx_clk }
set_clock_groups -asynchronous -group { CLK_11 } –group { CLK_12 }set_clock_groups -asynchronous -group { PHY_rx_clk }
SDC for CDC constraints: Primary ports
• Constraining primary ports in correct clock domains– May need to edit for actual delay
© Accellera Systems Initiative 11
Primary port constraints –set_input_delayset_output_delay
set_input_delay 0 -clock [get_clocks { PCLK_I }] [get_ports { DBG_rd_data }]set_input_delay 0 -clock [get_clocks { PCLK_I }] [get_ports { EE_addr_in_hw }]set_output_delay 0 -clock [get_clocks { PCLK_I }] [get_ports { HIF_tx_rx }]set_output_delay 0 -clock [get_clocks { PCLK_I }] [get_ports { HIF_tx_stat_vec_en }]
SDC for CDC constraints: Constants
• Constraining constants– Netlist constant– Mode signals
© Accellera Systems Initiative 12
Constant Port Information (Mode Signals)
set_case_analysisset_logic_zeroset_logic_one
CLK1
CLK2
Select
set_case_analysis 0 { TEST_EN }set_case_analysis 0 { SCAN_EN }
SDC for CDC constraints: False Paths
• Specify False Paths for Clock domain crossing paths
© Accellera Systems Initiative 13
Clock Domain Crossing paths
set_false_path –from TX –to RX
CLK Tx
CLK Rx
Tx Rx Rx1
set_false_path -from { HIF.HIF_OPI.MIB.MIB_bssid_5_2[15:8] } -to { MAC_CORE.MSCAN.MSCAN_CTRL.PS_bg_preauth_sleep_int_mode } -through { HIF.HIF_OPI.MIB.MIB_bssid[31:24] HIF.HIF_OPI.MIB_bssid[31:24]
HIF.MIB_bssid[31:24] MAC_CORE.MIB_bssid[31:24] }
SDC for CDC constraints: Maximum delay
• Constraining synchronizer for max delay requirement
© Accellera Systems Initiative 14
Clock Domain Crossing pathsset_max_delay
Tx
Rx Rx1
Rx
set_max_delay -from { HIF.MIB.MIB_bssid_5_2[15:8] } -to { MAC_CORE.MSCAN.sleep_int_mode } [get_attribute CLK_11 period]
delay < 1 RX clk cycle
Results
© Accellera Systems Initiative 15
Run Clocks False paths (CDC)
Timing Number of negative slack paths
1 12 0 Not met 34
2 12 240 Not met 9
2 12 730 216.357 MHz 0
Run Clocks False paths (CDC) Timing Number of negative slack paths
1 12 3574 346.141 MHz 0
Traditional Method of CDC constraints identification
Proposed Method to automatically generate CDC constraints
Conclusion• Easy and Reliable Setup with SDC• Iterative nature of traditional methods is eliminated
– Acceptable constraints in initial run itself
• Automatic generations of constraints in standard format – Avoid mistakes due to manual work
• Experiments with proposed methodology highlight all these benefits on customer designs.
© Accellera Systems Initiative 16
Questions
© Accellera Systems Initiative 17