A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan,...

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A Memory Model for RISC-V Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind RISC-V Workshop, November 29, 2016

Transcript of A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan,...

Page 1: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

AMemoryModelforRISC-V

Sizhuo Zhang,Muralidaran Vijayaraghavan,Arvind

RISC-VWorkshop,November29,2016

Page 2: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

WhynotSC/TSO?

Theybothhavesimplespecifications,bothaxiomaticallyandoperationallyButsimpleimplementationshavelowperformancen Strictorderingrequirementsformemory

instructionsn Toimproveperformance,onemust

w speculativelyexecutememoryinstructionsw monitorcoherenceinvalidationtraffic,andw keepcheckpointsandrollbackoninvalidation

Page 3: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

WhynotPOWER/ARM?

Theiroperationalmodelsexposetoomuchmicroarchitectural detailsn Branchspeculation,OOOexecution,etc is

exposedinthememorymodelspecification!Theiraxiomaticmodelsaretoocomplexwithnowell-understoodrelationtomicroarchitecturen Onecannotsaywithconfidenceifaparticular

microarchitectural implementationobeysthemodel

Page 4: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

Propertiesforanewmemorymodel

Simplespecificationwithoutmicroarchitectural detailslikeBranchspeculationButwellestablishedcorrespondencetomicroarchitectureimplementationsInclusionofsufficientfencestoforceSC-likebehaviorwhennecessary

Page 5: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

OurproposalforRISC-Vmemorymodel:WMM

SimpleoperationalspecificationlikeSCandTSOProcessor …

InstantaneousMemory

SC:• Storesupdatememoryinstantly• Loadreadsmemoryinstantly

ProcessorInstantaneousInorderExecution

Page 6: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

OurproposalforRISC-Vmemorymodel:WMM

SimpleoperationalspecificationlikeSCandTSOProcessor …

InstantaneousMemory

TSO:• Storesaredequeued inorder• Whenstoresaredequeued fromstorebuffer,itupdatesmemory

instantly• Loadreadstheyoungeststorefromstorebuffer,or(ifnotpresent)

memoryinstantly

StoreBuffer

Processor

StoreBuffer

InstantaneousInorderExecution

Page 7: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

OurproposalforRISC-Vmemorymodel:WMM

SimpleoperationalspecificationlikeSCandTSOProcessor …

InstantaneousMemory

WMM:• Storesaredequeued inorderonlyforsameaddress• Whenstoresaredequeued fromstorebuffer,itupdatesmemory

instantlyandenterseveryotherinvalidationbufferinstantly• Loadreadstheyoungeststorefromstorebuffer,or(ifnotpresent)

oldestentryininvalidationbuffer,or(ifnotpresent)memoryinstantly• Oldestinvalidationbufferentrycanbethrownoutanytime

StoreBuffer

Processor

StoreBuffer

InvalidationBuffer

InvalidationBuffer

InstantaneousInorderExecution

Page 8: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

FencesinWMM

ReconcileFence:ClearsInvalidationbufferCommitFence:FlushesStorebuffer,i.e.waittillstorebufferisemptybeforeexecuting

Page 9: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

AxiomaticDefinitionofWMMPreservedprogramorderaxiom

𝑋 <#$ 𝑌 ∧ 𝑜𝑟𝑑𝑒𝑟 𝑋, 𝑌 ⇒ 𝑋 <.$ 𝑌

Loadvalueaxiom𝐿𝑑𝑎𝑣 ⇒ 𝑣 = 𝑚𝑎𝑥𝑚𝑜 𝑣5 𝑆𝑡𝑎𝑣5 <#$ 𝐿𝑑𝑎 ∨ 𝑆𝑡𝑎𝑣5 <.$ 𝐿𝑑𝑎

𝑜𝑟𝑑𝑒𝑟 𝑋, 𝑌 𝑌Ld b Stbv’ Reconcile Commit

𝑋

Ld a a=b True True True

Stav False a=b False True

Reconcile True True True True

Commit False True True True

St-StFence:CommitLd-Ld Fence:Reconcile

St-Ld Fence:Commit+ReconcileLd-StFence:Notneeded

Page 10: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

ImplementingWMM– ProcessorsideAtypicalOOOimplementationobeysWMM

Aloadcanexecuteasearlyasitwantswithoutbeingsquashedaslongasitdoesn’tovertakeareconcileorloadorstoretosameaddressn Localchecks,nomonitoringofcoherence

invalidationsn Loadaddressspeculationallowed– squashedonlyif

predictedaddressiswrongAllinstructionsarecommittedinordern Storesvisibletootherthreads/coresonlyafter

commitw Storescannotovertakeloads

n Prevents“out-of-thin-air”generationofvalues

Page 11: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

Out-of-thin-airissue

Noprocessorcanproducevaluesoutofthinairn ButincompletesetofaxiomsseeminglyallowsthisInsistingonin-ordercommitsandadvertisingstoresonlyaftercommittootherthreads/processorstakescareofthisissue

Thread1 Thread2Ld R1=x Ld R2=ySty=R1 Stx=42

Initiallyx=y=R1=R2=0Finallyx=y=R1=R2=42

Page 12: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

ImplementingWMM– Memoryside

Typicalcache-coherentmemorywithwriteback cachesattachedtotypicalOOOprocessorsimplementsWMMIfL1iswrite-through,itstillimplementsWMMunlessthecoreisSMTSMTcoreswithL1write-throughcachesimplementa“non-multicopy-atomic”memory,whichisnotcoveredbyWMM

Don’tdoit

Page 13: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

MappingC++11toWMMC++11 WMM

Non-atomic Load Load

Load Relaxed Load

LoadConsume Load;Reconcile

LoadAcquire Load;Reconcile

LoadSC Commit;Reconcile;Load;Reconcile

Non-atomicStore Store

StoreRelaxed Store

StoreRelease Commit;Store

StoreSC Commit;Store

UsingoperationalspecificationofWMMmakesitstraightforward

Page 14: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

Conclusion

WMMisamemorymodelwithsimplespecificationandhighperformantimplementationn BlendswellwithRISC-Vphilosophyandshould

beusedasthememorymodelforRISC-V

Thankyou!

[email protected]@csail.mit.edu

Page 15: A Memory Model for RISC-V€¦ · A Memory Model for RISC-V SizhuoZhang, MuralidaranVijayaraghavan, Arvind RISC-V Workshop, November 29, 2016. Why not SC/TSO? They both have simple

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