Journal of Electronic Testing (2017) 33:709–720https://doi.org/10.1007/s10836-017-5696-3

A Low-cost Dithering Method for Improving ADC Linearity TestApplied in uSMILE Algorithm

Yan Duan1 · Tao Chen1 ·Degang Chen1

Received: 21 May 2017 / Accepted: 15 November 2017 / Published online: 20 December 2017© Springer Science+Business Media, LLC, part of Springer Nature 2017

AbstractAnalog-to-digital converters (ADCs) are an important component in electronics design. One of the difficulties being facedis to be able to accurately and cost-effectively test the continually higher performance of ADCs under budget constraints.Test time for static linearity is a major portion of the total test cost. Our group proposed an ultrafast segmented modelidentification of linearity error (uSMILE) algorithm for estimating linearity, which reduces test time dramatically comparedto the conventional method. However, this algorithm produces large estimation errors in low resolution ADCs (10-12 bits)when the input is a ramp signal, for which the quantization noise of ADC becomes a dominant part in the total noise. Inthis study, we propose three types of distribution dithering methods added to the ramp input signal to reduce the estimationerror when uSMILE was applied to low resolution ADCs. Fixed pattern was proved to be the most efficient and cost-effective method by comparing with the Gaussian, uniform, and fixed-pattern distributions. The simulation results indicatethat the estimation error can be significantly reduced in a 12-bit SAR ADC with effective dithering. Furthermore, a hardwareevaluation board with commercial ADC products was used to validate the effectiveness of the fixed-pattern ditheringmethods, and our measurement shows the INL estimation error can be reduced to less than 0.1 LSB. Such dithering methodrelaxes the input requirement of uSMILE algorithm which dramatically reduces the test setup cost.

Keywords Analog-to-digital converter · Integral nonlinearity · Ultrafast segmented model identification of linearity error(uSMILE) · Quantization error · Dithering

1 Introduction

The analog-to-digital converter (ADC) is one of the mostcommonly used, mixed-signal products [11]. Testing high-performance ADCs under cost/budget constraints remains ahuge challenge for decades in the semiconductor industry.As manufacturing costs drop gradually, the ADC testingcost becomes a major portion of the overall cost. ADClinearity test including integral and differential nonlinearity(INL and DNL) test is cost-sensitive and time-consuming.

Responsible Editor: S. Sunter

� Degang Chendjchen@iastate.edu

Yan Duanyanduan@iastate.edu

1 Iowa State University Ames, Ames, IA 50011, USA

The linearity test is conventionally conducted by a histogrammethod [4, 6, 27] using either a pure sine wave, or a verylinear ramp or triangle wave as stimulus.

There are two key challenges in ADC linearity test: linearstimulus generation [5, 10, 16] and data acquisition. Forthe linear stimulus generation, it is difficult to generatelinear stimulus for high resolution ADCs (higher than16-bit). Meanwhile, the histogram method requires moresamples than the number of transitions in the ADC for dataacquisition. It uses several tens even hundreds of hits percode to accurately test the ADC nonlinearity, and results ina long data acquisition time. For high resolution ADCs, itis not practical to fully test the ADC linearity due to theextremely long test time.

Researchers have proposed various methods to reducethe stringent requirements on the linearity of stimulus anddata acquisition. A stimulus error identification and removal(SEIR) algorithm using nonlinear stimulus was introducedpreviously by our group [12, 14, 15]. It demonstrated thata 7-bit linear ramp signal can be used to test a highresolution ADC and achieved more than 16-bit accuracy.

710 J Electron Test (2017) 33:709–720

However, the SEIR method was based on the histogrammethod, which means its data acquisition time is still verylong. Our group also attempted a system identificationapproach to identify the parameters in a pipeline ADC andthen reconstruct the full code linearity information [17]. Inaddition, another test method was also proposed to estimatethe ADC′s INL based on fast Fourier transform (FFT) [1,3]. Some researchers also combined Kalman filtering inthe standard histogram method and presented new ADClinearity test algorithms [13, 26] that can reduce the dataacquisition time dramatically. Goyal et al. [22] developed aselective code measurement method to reduce the test timeof SAR ADCs. In [8], the author exploited pipeline ADCproperties for a reduced-code linearity test technique. Allthe methods in the literature attempt to reduce linearity testtime by sacrificing some aspects of test accuracy comparedto histogram method.

Yu, et al. [25] in our group proposed an ultrafastsegmented model identification of linearity error algorithm(uSMILE) for accurate linearity test in a high resolutionADC with dramatically reduced data acquisitions. With thesegmented non-parametric model, the total number of datasamples in the algorithm is reduced by a factor of up to 100sand it can achieve a test accuracy superior to the histogrammethod.

However, the uSMILE algorithm caused large estimationINL error when the input is ramp signals applied to lowand middle resolution ADC (e.g 10–14 bit) because thequantization noise is the dominant part of the ADC noisein this case. In the ADC production test, large testingerrors cause yield loss. A quarter LSB estimation erroris difficult to achieve under limited samples. Since lowand mid resolution ADCs are widely used and the productvolume is in billions each year, there is a great potential toreduce the test cost by diminishing the estimation INL errorof uSMILE for low and mid resolution ADCs.

This paper proposes different dithering methods toidentify the most effective and easy-to-implement way toreduce the estimation error. The dithering includes theGaussian, uniform, and fixed-pattern distributions. Thefixed-pattern dithering method was verified to be themost efficient due to its easiness of implementation andeffectiveness in averaging the quantization noise. Theestimation error can be reduced to less than 0.1 LSB.

The rest of this paper is organized as follows. InSection 2, a brief overview of uSMILE algorithm willbe presented and quantization noise causing the INLestimation error will be also addressed. In Section 3,we will analyze different dithering techniques to averagethe quantization error and a low-cost dithering generatingcircuit will be introduced. In Section 4, the simulationresults for different dithering approaches are presented. InSection 5, measurement results will show the validation

of our proposed methods and Section 6 will present theconclusions of this study.

2 Problem Statement

In this section, the noise in ADCs is first discussed.We investigated many commercial ADCs with differentresolutions. For some low resolution ADCs, the noise isdominated by the quantization error. Then, the uSMILEalgorithm is reviewed and the INL estimation error causedby quantization noise in uSMILE is addressed.

2.1 Noise in ADC

The noise in ADCs is composed of two components: truenoise Nr and quantization noise Nq . The quantization noise(or quantization error) is due to the finite resolution of theADC. The true noise is from external sources such as inputsignal noise and random clock jitter, and the ADC systemnoise such as aperture jitter, KT/C in sampling capacitors,comparator noise and residue amplifier. One specificationof ADC performance is signal (S) to noise (N ) ratio (SNR),which is caculated by Eq. 1.

SNR = 20log(S/N) (1)

For ADCs with different resolutions, the noise contributionsare different. This paper focuses on Nyquist rate ADCs. Thecomparison of various industry ADC products from 12-bitto 20-bit is shown in Table 1. Only the quantization noiseis considered in the noise term N of ideal SNR calculation.The actual measured SNR is obtained from the datasheetfor comparison. For fair comparison, only low frequencymeasurement is used. The comparison shows that the noisein high resolution ADCs (16–20 bits) is dominated by thetrue noise. However, the noise in low and mid resolutionADCs (12–14 bits) is dominated by quantization noise.

For example, the theoretical calculation of SNR in 20-bitADC is about 122 dB while the measurement result is about104 dB, where the SNR is mainly limited by the true noise.The calculated SNR in 12-bit ADC is about 74 dB but some12-bit ADCs can achieve SNR close to 74 dB SNR.

Table 1 SNR comparison in selected industrial ADCs

ADC SNR(Ideal) SNR(Measured)

20bit (LTC-2378) 122 104

18bit (LTC-2379) 110 101.2

18bit (TI ADS8881) 110 100

16bit(TI ADS8353) 98 89

14bit(TI ADS7853) 86 82

12bit(TI ADS7253) 74 73.5

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2.2 uSMILE Algorithm

The uSMILE algorithm was developed to reduce thetest time for high resolution ADCs. It takes a systemidentification approach with a segmented non-parametricINL model. It assumes that for an N-bit ADC, all theINL/DNL errors are highly correlated and are deterministicfunctions of a much smaller number of independent errors(component size error, parasitic, voltage coefficients, etc.),which is true for most ADC architectures except flash ADCsand Sigma-Delta ADCs.

In this model, the INL is first broken into multiple-most-significant-bit (MSB) segments. Each MSB segmenthas an error term EM(CMSB) corresponding to the MSBcode CMSB . Then, for each MSB segment, the small INLcurve can be further divided into smaller segments forintermediate significant bits (ISB). Each ISB segment has anerror term EI (CISB) corresponding to the ISB code CISB .Similarly, each ISB segment can be further divided intosmaller segments for all the less significant bits (LSB). Forexample, an INL curve of 18-bit ADC can be broken into64 MSB segments, 64 ISB segments,64 LSB segments if 6-bit MSBs, 6-bit ISBs and 6-bit LSBs are used. There are 64MSB error terms that are denoted as EM(0), EM(1), · · · ,EM(63) and 64 ISB error terms EI (0), EI (1), · · · , EI (63).Similarly, EL has 64 EL. The actual output of ADC is C.The estimated INL for code C can be expressed by

INLest (C) = EM(CMSB) + EI (CISB) + EL(CLSB) (2)

For instance, if the code of ADC output C is 110011011110000111, then CMSB = 110011, CISB = 011110 andCLSB = 000111. With the above model, we first identifiedall the independent error terms and then used the model tocompute the full code of INL/DNL. The implementationof this method is shown in Fig. 1. The converted actualoutput code C from the ADC under test is compared withthe expected linear code Cexp to generate error signal(EM(CMSB) + EI (CISB) + EL(CLSB)). The error signalreflects the total error made by the ADC due to nonlinearity

Fig. 1 uSMILE algorithm implementation

(C − Cexp) and the noise (Nnoise). Therefore, the input andoutput relationships can be expressed as:

Cexp −C +Nnoise = EM(CMSB)+EI (CISB)+EL(CLSB)

(3)

If the average value of the Nnoise term in each segmentis zero, the estimated INL can be accurately computed asthe true INL. In order to obtain the estimated INL withthe segmented non-parametric model, the linear input signalinformation is used. The input signal can be either anaccurate sine wave or a linear ramp signal. The estimatedINL using sine wave as input is accurate with stringentcoherent sampling which causes the test cost very high.With ramp as input signal, the cost is very low. However, itbrings a large INL estimation error in low resolution ADC.Since the test cost reduced by using ramp signal is attractive,we will further discuss how to reduce the INL estimationerror with ramp input signal in the next part.

2.3 Problem Statement

In the uSMILE algorithm, the estimated MSB segmenterror for code i (MSB code) is shown in Eq. 4. Theexact derivation is in the Appendix. In this equation, theestimation error is equal to the average value of Cexp −C +Nnoise of i-th MSB segment.

EM(i) ≈ 1

#CMSB == i

∑

CMSB==i

(Cexp − C)

+ 1

#CMSB == i

∑

CMSB==i

(Nnoise) (4)

These similar equations can be derived for ISB and LSBerror terms respectively. For Eq. 4, if the mean value of thenoise in each segment is not zero, the estimation will not beaccurate.

Unlike the ramp histogram test, uSMILE algorithm canuse a ramp signal close to or less than 1 hit/code toeffectively test the ADCs INL/DNL. If the ramp signal with1 hit/code is used, each increment is 1 LSB in voltage. Itis unknown the position where each input signal hits in thetransfer curve of the ADC as shown in Fig. 2. It is a zoomed-in part of the transfer curve of a MSB segment. The bluedots represent the actual input signals and the green dots arethe middle points for each code bin. The difference betweengreen and blue dots in each LSB is the quantization error,ranging from −0.5 LSB to 0.5 LSB. The quantization errorfor ADCs with non-trivial INL/DNL is defined in the same

712 J Electron Test (2017) 33:709–720

Vin

DoutInput SignalMiddle of codeTransfer Curve

Quantization Error

Fig. 2 One MSB segment of ADC transfer curve and quantizationerror definition

way. Each input signal may have the same quantization errorin this segment if the LSB segments have good linearityand the increment of the voltage is exactly 1 LSB. Asdiscussed previously in part A, the noise in the low andmiddle resolution ADC is dominated by the quantizationand the true noise could be ignored. Therefore, the averagequantization noise in each MSB segment is not zero and theestimated EM is not accurate based on Eq. 4.

We use an example to illustrate this. For a randomlygenerated 12-bit SAR ADC in Matlab, a linear ramp inputsignal with 1 hit/code without extra noise was used in thesimulation. We used 4-bit MSB, 4-bit ISB and 4-bit LSB asthe segmentation in the uSMILE algorithm. The estimatedINL and true INL are plotted in top plot of Fig. 3. TheINL estimation error is as large as 0.5 LSB shown in thebottom plot of Fig. 3. In Fig. 4, it shows the quantizationnoise of each sample and there is a clear pattern shown

500 1000 1500 2000 2500 3000 3500 4000−2

−1

0

1

2

Code

Code

INL

(L

SB

)

INL Comparison

Est INL(no dither)

True INL

500 1000 1500 2000 2500 3000 3500 4000−1

−0.5

0

0.5

Est

Erro

r(L

SB

)

INL Estimation Error

Fig. 3 Comparison of true INL and estimation INL for uSMILEwithout input noises

500 1000 1500 2000 2500 3000 3500 4000−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

Code

Qu

an

tiza

tio

n E

rro

r(L

SB

)

Fig. 4 Quantization Error for each sample (averaged value in eachMSB is marked as red)

in the quantization noise distribution. Multiple red linesplotted in Fig. 4 show the averaged quantization noise ofeach MSB segment. The averaged quantization noise rangeis very wide and the distribution matches the shape ofthe estimation error plotted in Fig. 3 bottom. As manyADCs with similar resolution have a very good SNR, theapplication of uSMILE in these ADCs will be an issue withthe dominated quantization error. To reduce the estimationerror, a dither signal has to be added to the input signal toaverage the quantization noise.

3 Proposed DitheringMethod

In this section, three commonly-used dithering formswere investigated, including uniform noise, fixed patterndithering and Gaussian noise to reduce the INL estimationerrors [9, 20, 21, 23]. The implementation is to add extradither to the ramp input to test the ADC, shown in Fig. 5.

3.1 Dithering Amplitude

From Eq. 4, the INL estimation error is approximately equalto the averaged quantization noise in each MSB segment.

Ramp input

ADC

Added Dither

Fig. 5 Dithering Implementation

J Electron Test (2017) 33:709–720 713

The aim of adding the dither is to make the averagedquantization noise value to be zero in every segment.

Assume that every code bin width in each MSB segmentis exactly 1 LSB for the simplicity in the rest of thepaper. Define Vin as the input of an n-bit ADC, Vq as thequantization noise for each sample. For ADC output codeC, the relation among Vin and quantization noise for k-thsample can be expressed as:

Vin(k) = C · LSB + Vq(k) + 0.5 · LSB

Vq(k) ∈ [−0.5 0.5]LSB (5)

where LSB is ideal LSB voltage.Define that Vd(k) is the dithering signal added to k-th

sample, Vind(k) is the actual input of ADC after adding thedither. The Vind(k) is then expressed as:

Vind(k) = C · LSB + Vq(k) + 0.5 · LSB + Vd(k) (6)

With added dither, the ADC’s output code may not be thesame. If the dither is too large, the output code will increase.Then, the quantization error will change according to theactual output code. No matter how the code changes, thequantization error is alway within +/ − 0.5 LSB. The newquantization noise Vdq(k) can be expressed as:

Vdq(k) = Vq(k) + Vd(k) − n · LSB

Vdq(k) ∈ [−0.5 0.5]LSB (7)

where n is an integer to make Vdq within +/ − 0.5 LSB.For many samples in each segment, if the dithering signal

Vd(k) is too small (much smaller than 1 LSB), the voltageVind(k) after adding the dither is still close to the originalsignal Vin(k) and the quantization noise Vdq(k) hardlychanges (at this case n = 0). Thus, the ADC code remainsas the same code k even after adding dither signal under thiscircumstance.

If the term of Vq(CMSB) + Vd(k) is beyond +/ − 0.5LSB (larger than 0.5 LSB or smaller than −0.5 LSB), thesampled voltage Vind(k) will result in a different code (C −n) compared to Vin. Therefore, the new quantization errorVdq(k) will be shifted back to +/−0.5 LSB. The amount ofnew quantization noise Vdq(k) becomes Vq + Vd − nLSB

and n is an integer. In this case, the probability densityfunction (pdf ) fdq of new quantization noise Vdq is theconvolution of the original quantization noise distributionpdf function fq(vq) and the pdf of the dither signal fd .The excessive parts of 0.5 LSB and −0.5 LSB are needed tobe folded back within the +/ − 0.5 LSB range.

-0.5 0.5Vq Vq0

f(Vq)

Fig. 6 Quantization Noise Function

We analyze different dithering distributions to change thecode and make the average new quantization noise Vdq(k)

within MSB segment to be zero based on the discussionabove. We assume the initial quantization error Vq falls in [-0.5, 0] LSB and the probability distribution function (PDF)f (Vq) is shown in Fig. 6.

3.2 Uniform Noise Requirement

In order to average the quantization noise to zero, theuniform distribution dithering amplitude should satisfy withcondition of a + b = 0, b − a <= 1. The derivation is asfollows.

The uniform dithering follows a continuous uniformdistribution fq(Vd) given by Eq. 8 with the assumption thatVq < 0

fd(Vd) ={ 1

b−aa ≤ Vd ≤ b

0 otherwise(8)

Figure 7 shows the convolution of the quantization errorand PDF of the uniform distribution before folding. Theupper bound is Vq + b and the lower bound is Vq + a.

The quantization noise Vq > 0.5 LSB and Vq <

−0.5 LSB is folded back to [−0.5 0.5] LSB for the newquantization noise PDF fq(Vdq) , thus the range betweenVq + a and −0.5 LSB is moved to Vq + a + 1 and 0.5 LSBas shown in Fig. 8.

Fig. 7 Convolution of quantization error function with uniformdistribution PDF

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Fig. 8 PDF of quantization error after adding uniform noise

The expected value in the new quantization noisedistribution E(Vdq) is given by Eq. 9

E(Vdq) =∫ ∞

−∞fdq(vdq) · (vdq)dvdq

= 1

b − a

[∫ vq+b

−0.5vdqdvdq +

∫ 0.5

Vq+a+1vdqdvdq

]

= (vq + 1

2) · (1 − 1

b − a) (9)

From Eq. 9, the expected value E(Vdq) depends on theinitial quantization noise Vq with a range [−0.5 0.5] LSB.To minimize the expected value close to zero, choosing1/(b − a) can be made close to one. When 1/(b − a) isexactly equal to one, Vq + a + 1 is equal to Vq + b. Theexpected value E(Vdq) is exactly zero in this case no matterwhat Vq initial value is as shown in Eq. 10 and Fig. 9.

E(Vdq)=∫ ∞

−∞fdq(vdq)·(vdq)dvdq = 1

b − a

∫ 0.5

−0.5vdqdvdq =0

(10)

3.3 Fixed-Pattern Dithering

A fixed-pattern dithering refers to a series of m kinds ofdithering signal data and their values are repeated witha period of m. Each value has a probability equal to1/m. The fixed dithering pattern follows a discrete uniform

-0.5 0.5Vq 0 Vdq

fdq(Vdq)

Fig. 9 PDF of quantization error after adding uniform noise withexactly 1 LSB width

a 0 Vdb

1/m

(b-a)/(m-1)

fd(Vd)

Fig. 10 PDF of fixed pattern dithering (discrete uniform distribution)

distribution and we use probability mass function (PMF)for the discrete random variables. For the dithering signalVd with m bins from a to b follows a discrete uniformdistribution shown in Fig. 10. The lower bound is a andthe upper bound is b. Assume the initial quantization noiseVq falls in [−0.5 0] LSB, the convolution of ditheringdistribution function fd and the quantization function fq isshown in Fig. 11. The values after dithering lower than -0.5LSB are folded back to the (−0.5, 0.5) LSB range in Fig. 12.

Define that there are L values lower than −0.5 LSB andthe first value greater than −0.5 LSB is Vx . V ′

q is defined asthe distance between the−0.5 and Vx so that V ′

q = Vx +0.5.The expected value is:

E(Vdq) =L−1∑

k=0

1

m(Vq + a + 1 + k · b − a

m − 1)

+m−1∑

k=L

1

m(Vq + a + k · b − a

m − 1)

=L∑

k=1

1

m(V ′

q + 0.5 − k · b − a

m − 1)

+m−L−1∑

k=0

1

m(V ′

q − 0.5 + k · b − a

m − 1)

= −0.5 + b − a

2+ L

m

[1 − m(b − a)

m − 1

]+V ′

q (11)

Fig. 11 Convolution of quantization error function with PDF of fixedpattern dithering

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Fig. 12 PDF of quantization error after adding fixed-pattern dithering

In this equation, −0.5 + b−a2 is constant once a and b are

defined. V ′q is between 0 and b−a

m−1 which can be minimized

by using small value of b − a and large value of m. Lm

[1 −m(b−a)m−1 ] will depend on the value of L. However, L can be

any value between 0 and m2 . To make the second term small,

the value of 1 − m(b−a)m−1 should be minimized which will

result in b − a = m−1m

to make it be 0. In this case, theexpected value becomes

E(Vdq) = V ′q − 1

2m(12)

Since V ′q is between 0 and 1

m, the expected value will be

between − 12m and 1

2m , thus the maximum INL estimationerror (absolute value) caused by quantization error is 1

2m .

3.4 Gaussian Noise

Gaussian noise following N(0, σ 2) is added to an inputramp signal. The convolution of the quantization error withthe Gaussian noise is shown in Fig. 13. The beyond -0.5LSB part is folded back to [0 −0.5] LSB interval. Aftersummation, the new quantization error PDF fdq(Vdq) isshown in Fig. 14 and depends on the value of Vq and thevariance of the noise. Whatever the variance is, the PDFhave non-zero values from −∞ to +∞. For other values

Fig. 13 Convolution of quantization error with normal distributionprobability function

-0.5 0.5Vq 0 Vdq

fdq(Vdq)

Fig. 14 Probability density function of the quantization error afteradding Gaussian noise

beyond +/ − 3 σ , we can treat them as zero since theywill hardly change the PDF of the quantization error. Whenthe noise variance is small, the average quantization noiseremains close to the original value. When the noise varianceis large, the average quantization is close to 0 since the PDFof quantization error is more flat. However, the large noisevariance, in turn, will affect the uncertainty of the uSMILEestimation.

3.5 Hardware Implementation Comparision

Regarding the implementation, many researchers haveproposed efficient and compact design for Gaussian noisegenerators [2, 18, 19]. However, the circuit implementationproposed by these methods is very complex and and areaoverhead is large, thus the cost is very high. The uniformdithering generator provides the best quantization noiseaveraging capability but requires the probability densityfunction in a continuous form which is also difficult toimplement [24]. The fixed-pattern dithering generator alsoprovides excellent average capability. The implementationis much easier compared with the other two methods sinceit is easily achieved to generate a finite number of ditheringsignal. A low cost dithering hardware implementation forthe ADC linearity test is previously proposed [7] by ourgroup.

Fig. 15 Original SAR ADC structure

716 J Electron Test (2017) 33:709–720

Fig. 16 The linearity testoperation of the modified SARADC structure

The basic idea is shown in Fig. 15 that shows aconventional binary-weight N-bit SAR ADC. There are N

capacitors and one dummy capacitor Ct in a SAR ADC. Inthe proposed circuit, the dummy capacitor Ct is modifiedinto a small capacitor array in Fig16. Ct1 to Ct3 is a 3-bit small capacitor DAC and Ct0 is a dummy capacitorwith a value equal to Ct1. Note that the total capacitanceof the capacitor array remains the same as in original SARADC structure. More switches are added to control eachcapacitor in the small CDAC array. Ct1, Ct2 and Ct3 arecontrolled by a pseudorandom binary sequence (PRBS)pattern generator to generate the fixed pattern ditheringas shown in Fig. 17. The PRBS generator consists of aXOR gate, and 3-bit shift register. The PRBS generatorwill update the pattern for every new ADC sample. Usingthis simple implementation,the fixed dithering pattern canbe easily generated on chip and we can fully take advantageof the dummy capacitor in the CADC array. Therefore, thereis zero area overhead for the analog component.

4 Simulation

To demonstrate the validity of the proposed methodfor uSMILE algorithm in ADC linearity test, extensivesimulation has been carried out. A 12-bit SAR ADCis modeled with random capacitor mismatches. For the

Fig. 17 The implementation of PRBS pattern generator

segmentation, 4-bit MSB, 4-bit ISB and 4-bit LSB areused. Three linear ramp signals with Gaussian noise,uniform noise and fixed-pattern dithering are used as theinput of the same ADC. The ramp signal is 1 hit/code with1 LSB increment each time.

Gaussian noise with 0 mean and 0.5 LSB sigma is addedin the simulation. There are 48 variables in uSMILE methodand there are around 4,000 samples in the simulation.The test uncertainty has a variance of σ 248/4000 ≈0.01σ 2, where σ 2 is the Gaussian noise variance. The INLcomparison is shown in Fig. 18. The estimated INL matcheswith the true INL but with noticeable estimation error. Italso shows the difference between the estimated and thetrue INL. The maximum INL error is around 0.22 LSB. The3 sigma for estimation uncertainty is 0.3 LSB as analyzedearlier. The simulation matches the theoretical analysis.

For the uniformly distributed noise, the interval onlyneeds to be 1 LSB to effectively average the quantizationerror. In the simulation, 1 LSB wide uniform noise is used.The INL comparison and the estimation error difference areshown in Fig. 19. The maximum estimation error is less than

Fig. 18 INL comparison after adding Gussian dithering

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Fig. 19 INL comparison after adding uniform dithering

0.1 LSB, showing better performance than the Gaussiannoise effect.

The fixed-pattern dithering is implemented using theproposed architecture in Section 3. In Fig. 3, the input signalhas no noise and the INL estimation produces as large as0.5 LSB error. Then, a 7-value fixed-pattern dithering wasadded to the input signal with 7/8 LSB difference betweenthe smallest and largest dithering signal. The estimation isshown in Fig. 20, which shows less than 0.1 LSB estimationerror. In the previous analysis, the estimation error can bereduced to 1/2m when m is equals to 8 which is 0.0625LSB.

Compared among the Gaussian, Uniform and Fixedpattern dithering, both uniform noise and fixed pattern have

Fig. 20 INL comparison and uSMILE estimation error after addingfixed dithering

very good estimation. Considering the implementation, thefixed pattern dithering is feasible and low cost.

5Measurement Result

The proposed method of adding dither to uSMILE algorithmhas been validated by MATLAB simulation. However,in real testing, there are more unpredictable factors thatcannot be simulated and the ultimate application of thisalgorithm is experimental testing. The proposed fixedpattern dithering method is validated by measurementresults using a commercial 12-bit SAR ADC.

A hardware test board with commerical DAC and ADCwas designed shown in Fig. 21. The test stimulus isgenerated from a 20-bit DAC AD8756. The ADC undertest is ADS7253 (a 12-bit commercial ADC with 73.5dBSNR). The 20-bit DAC has a very good linearity, whichcan be used in the histogram test to obtain a relativelyaccurate INL results. Since the resolution of the DAC ishigh, the DAC code can be programmed to generate a fixedpattern corresponding to the fixed pattern dithering. Thefixed-pattern added to the DAC code is a PRBS-3 code. Thedither voltage range corresponds to −3/8 LSB to 3/8 LSBof ADC. An FPGA board (Altera DE2 board) is used tocontrol the timing, control signal, and data storage. The testsetup is show in Fig. 22.

Applying the stimulus to the SAR ADC, the outputof the ADC was collected by the FPGA board and sentto the uSMILE with 4 bit MSB, 4 bit ISB and 4 bitLSB segmentation. The INL of ADC is also tested by 64hits/code histogram ramp test as true INL for comparison.The DNL/INL comparison of uSMILE before and afteradding dithering with histogram test is shown in Fig. 23.For the INL comparison, the blue curve is the result of 64hits/code histogram ramp which is treated as a standard.The red curve is the result of 1 hit/code uSMILE beforeadding dithering. The green curve is the one with 1 hit/codeuSMILE after adding dithering. Figure 24 shows the INLestimation error in the uSMILE before and after addingdithering. In the test results, the two-end comparison isnot shown due to saturation near top and bottom for thehistogram. From the result, it shows that the INL estimationerror is as large as 0.6 LSBwithout dithering technique. Andthe INL estimation error is less than 0.1 LSB with the fixed-pattern dithering which was validated the accuracy of fixedpattern dithering method.

In the measurement results, there are clearly somesegmented errors in the INL estimation before ditheringwhich are caused by the unwhitened quantization noise.After applying the fixed pattern dithering, the segmentederror shape is significantly reduced and the INL estimationerror is reduced from 0.6 LSB to 0.1 LSB.

718 J Electron Test (2017) 33:709–720

Fig. 21 Test Board withCommercial ADC and DAC

Fig. 22 Hardware MeasurementSetup

Fig. 23 Measurement result: INL comparison before and after addingdithering

0 500 1000 1500 2000 2500 3000 3500 4000

Code

-0.8

-0.6

-0.4

-0.2

0

0.2

Estim

ation E

rror (

LS

B)

Estimation Error

w/o dithering

w/ dithering

Fig. 24 Measurement result:Estimation Error Comparison of addeddithering and without dithering

J Electron Test (2017) 33:709–720 719

6 Conclusion

Various dithering methods that reduce the ADC linearitytest error applied in uSMILE are compared and evaluated.uSMILE algorithm was developed by our group before foraccurately estimating ADC linearity test with significantlyreduced data acquisition time. However, in a low noise test-ing environment, the quantization error causes up to +/ −0.5 LSB INL estimation error. Different dithering methodsincluding Gaussian, uniform and fixed-pattern dithering areproposed to overcome this issue. Simulation results havevalidated that proper dithering can significantly improve theestimation accuracy. The fixed-pattern dithering method isproven to be the most-efficient and cost-effective method. Inaddition, measurement results from commercial ADC showthat the INL estimation error can be reduced to 0.1 LSBwith fixed pattern dithering. Therefore, using the proposedfixed pattern dithering, the uSMILE algorithm can be effec-tively used in the low resolution ADC with reduced numberof sampling. Considering the high volume in around 12-bitADCs, the cost reduction becomes significant. The pro-posed fixed pattern hardware implementation method canbe implemented for future on-chip BIST solution.

Appendix : Derivation of Eq. 4 in Section 2

Let NMSB , NISB and NLSB be the numbers of bits in MSB,ISB and LSB bits. Then, the numbers of segments are2NMSB , 2NISB and 2NLSB for MSB, ISB and LSB segmentsrespectively. Define EM in Eq. 13 is a column matrix of allthe error terms of MSB EM terms. EI and EL are definedsimilarly.

EM =⎡

⎢⎣EM(0)

...EM(2NMSB − 1)

⎤

⎥⎦ (13)

Define three matrices HM, HI and HL. HM in Eq. 14 is ak∗2MLSB matrix with each term being a boolean value eitherone or zero. k is the total sample number of input data. Eachrow represents each sample falling in MSB error term EM .If the MSB error term of the jth sample data corresponds toEM(X), then the Xth column of the HM is one in jth row.It is the only one in each row and all the others are zeros incorresponding row. HI and HL are defined in the same wayfor ISBand LSB bits.

HM =⎡

⎢⎣

CMSB(1) == 0 CMSB(1) == 1 · · · CMSB(1) == 2NMSB − 1....... . .

...CMSB(k) == 0 CMSB(k) == 1 · · · CMSB(k) == 2NMSB − 1

⎤

⎥⎦

(14)

Then, the estimated INL for the whole sample can beexpressed as Eq. 15.

[Cexp − C + Nnoise

] = [HM HI HL

]⎡

⎣EM

EI

EL

⎤

⎦ (15)

In the (i + 1)th column in the matrix, we multiplied bothsides by the transpose of this column matrix.

[CMSB(1)== i · · ·CMSB(k)== i

] [Cexp − C + noise

]

= [CMSB(1)== i · · ·CMSB(k)== i

] [HM HI HL

][

EM

EI

EL

]

(16)

In this matrix[CMSB(1) == i · · · CMSB(k) == i

],

only the location where the corresponding MSB bit beingi will be 1s and all the other all 0s. Therefore, 17 can beobtained.

[ ∑CMSB==i (Cexp − C) + ∑

CMSB==i (Nnoise)]

=∑

CMSB==i

EM(i)+2NISB −1∑

j=0

[ ∑CMSB==i&&CISB==jEI (j)

]

2NLSB −1∑

j=0

[ ∑CMSB==i&&CLSB==j EL(j)

]

(17)

If the total number of samples is k, within each MSBsegment, the number of samples is approximately equalto k/2NMSB . Within each MSB segment, the number ofsamples for each ISB segment is approximately equal tok/2(NMSB+NISB) . Within each MSB segment, the numberof samples for each LSB segment is approximately equalto k/2(NMSB+NISB) . Then, Eq. 17 can be approximated byEq. 18.[ ∑

CMSB==i (Cexp − C) + ∑CMSB==i (Nnoise)

]

≈∑

CMSB==i

EM(i)

+ k

2NMSB+NISB

[ ∑NISB−1j=0 (EI (j))

]

+ k

2NMSB+NISB

[ ∑NLSB−1j=0 (EL(j))

](18)

In this equation,∑NISB−1

j=0 (EI (j)) and∑NLSB−1

j=0 (EL(j))

are close to 0 and their coefficients are also much smallercompared with the number of CMSB equal to i so that thelast two terms are almost 0 and can be discarded shown inEq. 19.[ ∑

CMSB==i (Cexp − C) + ∑CMSB==i (Nnoise)

]

≈∑

CMSB==i

(EM(i)) (19)

720 J Electron Test (2017) 33:709–720

Dividing both sides by the number of MSB bits being(#CMSB == i), we obtained the Eq. 20

EM(i) ≈ 1

#CMSB == i

∑

CMSB==i

(Cexp − C)

+ 1

#CMSB == i

∑

CMSB==i

(Nnoise) (20)

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Yan Duan received the B.S. and the M.S. degree in ElectricalEngineering from Hunan University, Changsha, China, and the Ph.D.degree in Electrical Engineering from Iowa State University, Ames,IA, USA, in 2017. Since 2016, she has been a Design Engineer withIntel, San Jose, CA, USA. Her current research interests include analogand mixed signal design and testing.

Tao Chen received the B.S. degree in electrical engineering from IowaState University, Ames, United States in 2013. He is currently pursuingthe Ph.D. degree in electrical engineering at Iowa State University,Ames, United State.

From January 2014 to December 2014, he was an intern working onADC built-in self-test in Freescale Semiconductor. In summer 2015, hewas a analog design intern working on Cyclic ADC design in FreescaleSemicondcutor. In summer 2016, he was an design intern in NXPSemiconductors working on precision amplifier design. Currently, heis an analog design engineer in NXP Semiconductors.

His current research interests include data converter design,modeling, built-in self-test and calibration.

Degang Chen received the B.S. degree in instrumentation andautomation from Tsinghua University, Beijing, China, in 1984, andthe Ph.D. degree in electrical and computer engineering from theUniversity of California, Santa Barbara, CA, USA, in 1992. He was theJohn R. Pierce Instructor of Electrical Engineering with the CaliforniaInstitute of Technology, Pasadena, CA, in 1992. Since then, he hasbeen with Iowa State University, Ames, IA, USA, where he is currentlya Professor and the Jerry Junkins Chair of Electrical and ComputerEngineering. He was a Faculty Fellow with Boeing, Chicago, IL,USA, in 1999, Maxim Integrated, San Jose, CA, in 2001, andTexas Instruments (TI), Dallas, TX, USA, in 2011, 2012, and 2014.Within the last year, he has delivered technical seminars at CarnegieMellon University, Pittsburgh, PA, USA, Columbia University, NewYork, NY, USA, South Methodist University, Dallas, the Universityof Minnesota, Minneapolis, MN, USA, the University of Texas atDallas, Dallas, Broadcom, CA, Cypress Semiconductor, WA/MN,USA, Global Foundries, VT, USA, IBM Watson, NY, Infineon,Germany, Intel, CA/OR, USA, NXP, TX, TI Dallas/India/Santa Clara,and Xilinx, CA. He has authored over 230 refereed journal andconference publications. His current research interests include analogand mixed-signal integrated circuit design and testing, integratedcircuit sensor design, and high-accuracy test without requiring high-accuracy instrumentation. Dr. Chen received 13 Best Paper Awards andother honors, including the IEEE Ned Kornfield Best Paper Award in2013 and 2014.