A leap Gruppe und die Arbeiten der Welcome to ahead die Arbeiten der Process & Device...
Transcript of A leap Gruppe und die Arbeiten der Welcome to ahead die Arbeiten der Process & Device...
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Welcome to austriamicrosystems
A leap ahead in mixed signal
Vorstellung der AMS und die Arbeiten der Process & Device CharacterisierungsGruppe
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To provide the most competitiveintegrated mixed signal solutionsfocused on speed, value, andquality.
austriamicrosystems’ experiencedteam empowers customers topursue the ideal path in combininganalog and digital processingthrough proven and perfectedproduct and process IP.
Corporate Mission
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Our Success Is Based On...
Know HowKnow How
ProductsProducts
TechnologTechnology
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– 1981 Austria Micro Systems founded byAmerican Microsystems Inc. (AMI)/Voest Alpine Joint Venture
– 1993 June AMS goes public
– 2000 July groundbreaking new Fabin Graz
– 2000 August AMS returns to privatestatus (Permira Private Equity Fund)
– 2002 March new 200 mm Fabgoes on-line
– Multinational presence:800+ employees, 12 offices worldwide
Company Profile
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Worldwide Locations
Headquarters & Fabs Design Center Sales Office Distributor & Representative
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Value Chain
ProductDefinition
Design
Mask Generation
Wafer Sort Assembly
Test
ASSPsASSPsASICsASICs
COTCOT
Wafer Production
Delivery to Customer
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INDUSTRY& MEDICAL
Solid State MeteringSensors
Healthcare
FULL SERVICEFOUNDRY
Design SupportProcess Characterization
Wafer ProductionBackend Services
COMMUNICATIONS
Power Management Mobile Audio
RF TransceiversWireline Communications
AUTOMOTIVE
Access Control & MobilizingSensor & Micro Systems
Motor & Power ManagementBus Systems
Business Segments
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DESIGN SUPPORTCAD tools (HIT- Kit), analog and digital IP
PROCESS CHARACTERIZATIONSpice modeling for mixed signal, RF, HV
WAFER PRODUCTION(100/200 mm FAB)Mixed Signal RF andHigh-Voltage Processes
BACKEND SERVICESTest, Assembly
Full Service Foundry
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*) Source: Future Horizons 2002 (European Chipless & IC Design House Report)
BiCMOSCMOS SiGe Bipolar GaAs
TSMC amsams
ams
ST Micro.
Chartered
Atmel
ST Micro. Atmel
IBMPhilips
Alcatel
Atmel
Zetex
Mitel TriQuint
Rank
1
2
3
4
5
6 UMC
Philips
UMS
Philips
Respected Number 1 Foundry *)
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Available Technologies 2003 2004 2005 2006
BiCMOS
Mixed Signal / RF Technology Roadmap
SiGeBiCMOS
BYQ0.8µm 2P2M13/14GHz 6V
BYS0.8µm 3P2M35/40GHz;4.5V
Left edge of each box represents start of production
austriamicrosystems
FoundryPartnership
Eng.
RunsEng.
Runs
S35x0.35µm 2P4M MIM60/70GHz/2.8V35/45GHz;5V
S18x0.18µm 1P6M MIM150GHz
MS/RF CMOS
C35x0.35µm 2P4M3.3V/5.0V
CXx0.8µm 2P2M3.3V/5.0V
C25x0.25µm 2P5M2.5V/3.3V,5V
C18x0.18µm 1P6M MIM1.8V/3.3V
Eng.
Runs
C18x0.18µm 1P6M MIM1.8V/3.3V
C25xxEx0.25µm eNVM EEPROM/FLASH
Eng.
Runs
C18xxEx0.18µm emb.EEPROM/FLASH
Eng.
Runs
C35xxEx0.35µm emb.EEPROM/FLASH
emb. NVM
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High Voltage & Sensor Technology Roadmap
CXZ0.8µm 2P2M5V- 50V
70V/90V HV
Eng.
Runs
H35xxxx0.35µm 2P4M 3.3V, 5- 50V
Eng.
Runs
H18xxxx0.18µm 1P6M MIM1.8V - 50V
Eng.
Runs
H35xxyy0.35µm 2P4M 3.3V, 5-70V
Available Technologies 2003 2004 2005 2006
CXQ0.8µm 2P2M300mA/W
Eng.
Runs
C35xxOx0.35µm 2P4M>300mA/W
Eng.
Runs
C18xxOx0.18µm 1P6M MIM>300mA/W
50V/70V HV
CMOS Opto
CXS/SME0.8µm
Eng.
Runs
H35xxEx0.35µm emb.EEPROM/FLASH
Eng.
Runs
H18xxEx0.18µm emb.EEPROM/FLASH
Emb. NVM
MEMS
Left edge of each box represents start of production
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Net Sales
87,9121,9
147,5 131,5153,8
0
20406080
100120
140160180
1999 2000 2001 2002 2003EYear
EUR Mio
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Revenue By Regions 2002
Asia-Pacific7%
Americas
19%
Europe74%
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Revenue By Business Units 2002
Automotive21%
Full Service Foundry17%
Communications23%
Industry & Medical39%
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Our Products used at ...
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Process & Device Characterization
Process Characterisation at
austriamicrosystems
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Local Modelling activities
CMOS
BiCMOSSiGe
HV CMOS
EEPROM
Opto
Design DocumentsSPICE ModellingSimulator SupportVerification
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Capabilities under one Roof A Link between Design and Manufacturing
DesignDesignMask ShopMask Shop TestTest
AssemblyAssembly
WaferfabWaferfab200mm200mm
100mm100mmWaferfabWaferfabWaferfab
ProcessCharacterization
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Design Documents
Basic Design & Process InformationProcess Parameters Documents
Operating conditionsStructural & geometricalparametersElectrical parametersSPICE ModelsFigures of merit (e.g. FT ,FMAX)
Design Rule DocumentsRules, Guidelines, RecommendedLayout Structures
RF-Design DocumentsRF-DevicesRF ModelingFigures of merit (e.g.Qmax)
Noise DocumentsNoise MeasurementsNoise Modeling
Matching DocumentsMatching MeasurementsMatching Modeling
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SimulatorIntegration
Spectre, Eldo, ..
Testchips,SLM
DESIGNHIT-Kit, Customer
Process Characterisation
Simulator Integration Flow
Device ModelsMeasurement
Parameter ExtractionStatistical Modelling
StatisticalProcess Data
MAP-ParametersProcess
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Simulator Model Generation Flow
Parameter Databasemodn,modp,rpoly1,cpoly...
Generation Program
Spectre
Typical Worst Case Monte Carlo Stat. Corners
Eldo ADS
30 processes
20 000 model files
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Circuit Simulators and Models
Simulator MOS-Transistor Monte Carlo& Matching
Bip-Transistor
BSIM3v3 Level 53
AMS MOS15 level15
SGP VBIC
Eldo 4.4.1 4.3.5 4.4.1 4.4.1 -
Accusim I B.3 A.3 B.3 B.3 -
Spectre Direct 4.4.3 4.4.3 4.4.3 4.4.3
Spectre 4.4.1 4.3.4 4.4.1 4.4.1 4.4.3
Hspice 97.2(level 49) - 97.2 97.2 -
Saber 4.3 3.2 - 4.3 4.3.2
Smash 3.53(level 8) 3.4 - 3.53 -
Pspice A/D v. 8.0 - - A/D v. 8.0 -
Agilent-ADS 1.01 - - 1.01 1.01
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Process & Device Characterization
CMOS Characterisation
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Compact Modeling for the CMOS Process
• BSIM3v3 for std. MOS transistor
• High voltage transistor modeled assub-circuits
• JFET models for all diffusion resistors
• SGP model for all pnp (Vert,Lat)
• Subcircuit for the zener diodemodeling
• Voltage and Temp. dependentCapacitance modeling
• Matching Parameter
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The Parasitic Bipolar Transistor Modeling
Vertical PNP Transistor• Standard Gummel Poon
ModelLateral PNP Transistor
• Sub-circuit lateral and verticalpnp Transistor
• Parameter extraction- Optimizer linked to Eldo
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Analog modeling for capacitances
−10 −8 −6 −4 −2 0 2 4 6 8 1032.95
33
33.05
33.1
33.15
33.2
< 0 deg C
< 25 deg C
< 50 deg C
< 75 deg C
< 100 deg C
< 125 deg C
< 150 deg C
< 175 deg C
V [V]
Cap
[pF
]
−8 −6 −4 −2 0 2 4 6 825.98
26
26.02
26.04
26.06
26.08
26.1
26.12
26.14
26.16
26.18
< 0 deg C
< 25 deg C
< 50 deg C
< 75 deg C
< 100 deg C
< 125 deg C
< 150 deg C
< 175 deg C
V [V]
Cap
[pF
]
Voltage and temp. dependent modeling of the PIP and MIM capacitances
CMIM=1.25fF/µm²CPIP=0.86fF/µm²
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Process & Device Characterization
1/f Noise Characterisation
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Noise Plots
SPICE Model BSIM3v3
fI
LCS D
effOXiF
AFKF ⋅⋅⋅
= 21
−⋅
⋅⋅⋅⋅
= =
,...,),(;,,
1
,
)1(2
effDSTHGSD
effEFD
effOXi
VVVVIfkt
fI
LCS
F
ΝΟΙCNOIBNOIA
µ
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Process & Device Characterization
Device Mismatch
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Device Matching, Mismatch Simulation
Steps to the mismatch simulation:
• Suitable testchip (preventMeasurements from systematicMismatch Influences)
• Accurate measurements (on wafer)
• Parameter extraction (non linear fits)
– Applying Pelgroms Law– Simulation models (suitable for
Monte Carlo)
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Process & Device Characterization
HV CMOS Characterisation
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Compact Modeling HV CMOS 50V & 90V Process
•Special sub-circuits for high voltage transistormodel•BSIM3v3 for std. MOS transistor•VBIC for npn & SGP model for all pnp bipolartransistors•JFET models for all diffusion resistors•Subcircuit for the junction FET•Parasitic diode modeling for all HV transistorsand isolated transistors.•SOAC - “Safe Operating Area Check” checksthe allowed DC operating conditions••Temp. modeling for -30-125degCTemp. modeling for -30-125degC
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Process & Device Characterization
BiCMOS & SiGeCharacterisation
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0.35 BiCMOS
Devices & Simulation Models
CORE PROCESS
Device Device Name Model Name Model Rev.
3.3 Volt NMOS NMOS modn 2.0
3.3 Volt PMOS PMOS modp 2.0
high voltage NMOS (gate oxide) NMOSH modnh 2.0
vertical NPN bipolar transistors:single base, single collector NPN111 npn111 2.0
vertical NPN bipolar transistors:multiple base, single collector
NPN121NPN132NPN143
npn121npn132npn143
2.02.02.0
vertical NPN bipolar transistors:multiple base, double collector
NPN232NPN243NPN254
npn232npn243npn254
2.02.02.0
Vertical PNP bipolar transistor VERT10 vert10 2.0
Lateral PNP bipolar transistor LAT2 lat2 2.0
Lateral PNP bipolar with buried layer LAT2B lat2b tbd
Diode NDIFF / PSUB SUBDIODE nd 2.0
Diode PDIFF / NWELL WELLDIODE pd 2.0
Diode NWELL / PSUB NWD nwd 2.0
Diode BNWELL / PSUB BNWD bnwd tbd
Zener diode ZD2SM24 zd2sm24 2.0
POLY1-DIFF capacitor NGATECAP ngatecap 2.0
POLY1-SINKER capacitor CSINK csink tbd
POLY1-SINKERM capacitor CSINKM csinkm 2.0
MOS Varactor CVAR cvar 2.0
PDIFF resistor RDIFFP, RDIFFP3 rdiffp (model R)rdiffp3 (model JFET)
2.0
NDIFF resistor RDIFFN, RDIFFN3 rdiffn (model R)rdiffn3 (model JFET)
2.0
NWELL resistor RNWELL rnwell 2.0
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0.35um BiCMOS
Devices & Simulation Models
CPOLY MODULE
Device Device Name Model Name Model Rev.
POLY2 resistor RPOLY2 rpoly2 2.0
CPOLY capacitor CPOLY cpoly 2.0
RPOLYH MODULE
Device Device Name Model Name Model Rev.
POLYH resistor RPOLYH rpolyh 2.0
5 VOLT MODULE
Device Device Name Model Name Model Rev.
5 Volt NMOS NMOSM modnm 2.0
5 Volt PMOS PMOSM modpm 2.0
high voltage NMOS (mid-oxide) NMOSMH modnmh 2.0
CMIM MODULE
Device Device Name Model Name Model Rev.
METAL2-METALC capacitor CMIM cmim 2.0
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0.8um HBT BiCMOS
Device DeviceName
Model name ModelRev.
vertical npnbipolar tr.
NPN#C#B#E npn#C#B#E 2.0
mos varactor CVAR cvar 2.0inductors SPXXXAY spxxxay 2.0
poly1-polybcapacitor
CPOLYBRF cpolybrf 1.0
poly1 resistor RPOLY1RF rpoly1rf 1.0polyb resistor RPOLYBRF rpolybrf 1.0
RF Simulation Models
Simulator Simulator CAD IntegrationSpectre Spectre 4.4.6 Cadence IC446
Gemini/ADS HPEESOFSIMv.170 rev. 200
Agilent ADSv2001
Simulator Models and Design Kit Integration
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Vertical NPN bipolar transistorNPN121,NPN2xy,(cbe), W=0.8um
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Bipolar-Transistor Compact Model Capability
Scalable VBIC bip. transistor models
• state of the art model- HP-ADS, Spectre, Saber, (ELDO)
Scalable SGP bip. transistor models
• improved SGP model- compatible for all simulators
10−15
10−10
10−5
100
0
50
100
150
Ic/area [A/mu]
Ic/Ib
DCBETA: H12102 (VBIC model)
Measurements: solid lines
o......Ucb=0V
*......Ucb=1.5V
+......Ucb=3V
Temperature modeling from -50 - 125(200)degC
Parameter Extraction from DC-, S-Parameter and Noise measurements
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HF-Characterization of Bipolar Transistors
15
S-Parameter measurements up to40GHzExtraction of cutoff frequency FTand maximum oscillation frequencyFMAX as figures of merit
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RF MOS Transistor Modeling
BSIM3v3.2 & Sub-circuit
• gate res, substrate netwerk
fixed gate length (0.35um)
• different with
• number of fingers
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Varactor Sub-circuit & C-V Characteristics
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Inductor Modelling
Subcircuit:
There is a library with 15 different square inductors with values ranging from 1.4 nH up to 20 nH. The layout of the inductors is fixed. All inductors are modeled with a lumped RLC equivalent circuit.
0 1 2 3 4 5 6
x 109
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7x 10
−9
frequency [Hz]
L [H
]
0 1 2 3 4 5 6
x 109
0
1
2
3
4
5
6
7
8
frequency [Hz]
QMeasured (x) and simulated (-) effective series inductance and quality factor of spiral SP025C2 as a function of frequency.
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Poly1-Poly2 Capacitor (cpolyrf)
Subcircuit:
The poly1-polyb capacitor is built up of: polyb (top-plate) - insulator (thin oxide) - poly1 (bottom-plate). 20 capacitors with values ranging from 0.2 pF – 10 pF and different W/L-ratios were measured and fitted. A scaleable model was generated based on these measurements.
0 1 2 3 4 5 6
x 109
0.5
1
1.5
2
2.5
3x 10
−12
frequency [Hz]
C (
F)
Measured (x) and simulated (-) series capacitance (W=33.4 µm, L=33.4 µm ) as a function of frequency.
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Process & Device Characterization
Software & MeasurementEquipment
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S-Parameter Measurement capabilities
Measurement Equipment• Cascade Summit Probe Station
• Parameter - Analyzer
• Network - Analyzer
• Cap-Meters
Extraction Tools• UTMOST
IC-CapWinCal 2.3
• MatlabLabView
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Measurement Software
UTMOSTfor active devices
IC-Capfor active and passive devices,
interface to ADS
WinCal 2.3for passive devices, runs on PC
Matlabparams optimizer
LabView dc measurements (resistor,jfet, bip transistor models)
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Corporations
MOS AK
Infineon, Philips, EPFL, Agilent, Motorola
Bip-AKInfineon, Philips, Alcatel, Atmel, Bosch, Motorola, IHP
TU-Graz, TU-WienSupervision of dissertation and diplom thesis
CODESTAR(Compact moDEling of on-chip passive Structures At high fRequencies)
Partner:IMEC,Gent University,Philips,Tech. Uni Eindhoven, Polytech. Univ. Bucharest
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Outlook
CMOS:
• BSIM3v3, BSIM4, EKV3
BiCMOS:
• VBIC, HICUM/Mextram, HF - Noise
HV-CMOS:
• BSIM3v3 Sub-circuit, AMS HV-CMOS
Opto
• Photo Diode model