A High Power Inverter for Remote Applications

i

A High Power Inverter for Remote Applications

By

CLIFTON CUNNINGHAM

Department of Computer Science and Electrical Engineering,

University of Queensland.

Submitted for the degree of

Bachelor of Engineering (Honours)

In the division of Electrical and Computer Engineering

October 1999

iii

Clifton Cunningham

4 Bligh Court

Mackay, QLD, 4740

Ph: 0417 007 572

October 14, 1999

The Dean

School of Engineering

University of Queensland

St Lucia, Q 4072

Dear Professor,

In accordance with the requirements of the degree of Bachelor of Engineering

(Honours) in the division of Electrical and Electronic Engineering, I present the

following thesis entitled “A High Power Inverter for Remote Applications”. This work

was performed under the supervision of Mr Geoff Walker.

I declare that the work submitted in this thesis is my own, except as

acknowledged in the text and footnotes, and has not been previously submitted for a

degree at the University of Queensland or any other institution.

Yours Sincerely,

Clifton Cunningham.

v

Acknowledgements

The author wishes to acknowledge the guidance and assistance of all those who aided in

the development and implementation of this thesis.

I must express my gratitude and thanks to Mr Geoff Walker for his help and guidance

throughout the year – which somehow always seemed to happen just when I needed it.

I would also like to thank my fellow students for their assistance when it was required

and all of those involved in my life outside my thesis for putting up with me. I finally

would like to thank my parents for always being there.

vii

Abstract

This thesis document outlines the research, design and implementation of a high power

direct current (DC) to alternating current (AC) inverter with particular focus on remote

applications. The final design consisted of a two-stage converter consisting of a DC-DC

Step Up stage and a DC-AC Inverter stage. The DC-DC Step up converter was based on

a Push-Pull design and steps 12Vdc to 400Vdc. The inverter stage was based on a full-

bridge configuration that generates a 240Vac output from 400Vdc. The Microprocessor

was a Hitachi SH1 used simple voltage mode control to implement a PI control system.

The system that was tested and implemented was designed to generate 240Vac at 100W

but developed the potential to operate at considerably higher power with far more

advanced control algorithms.

ix

Contents Acknowledgements ..........................................................................................................v

Abstract ......................................................................................................................... vii

List of Figures ................................................................................................................xi

List of Tables.................................................................................................................xii

1 Introduction ................................................................................................................13

1.1 Background to the research...................................................................................13

1.2 Research problem and hypotheses ........................................................................13

1.3 Justification ...........................................................................................................14

1.4 Outline of the report ..............................................................................................15

1.5 Conclusion ............................................................................................................15

2 Review of Literature...................................................................................................17

2.1 DC-DC Conversion...............................................................................................17

2.2 DC-AC Inversion ..................................................................................................18

2.3 Power Switching ...................................................................................................19

2.4 Soft Switching Techniques ...................................................................................21

2.5 Control ..................................................................................................................23

2.7 Summary ...............................................................................................................26

3 Theory..........................................................................................................................27

3.1 Analysis of the Power MOSFET ..........................................................................27

3.2 The Push-Pull DC-DC Converter .........................................................................29

3.3 Transformer Selection...........................................................................................31

3.5 The Full-Bridge DC-AC Inverter..........................................................................32

3.4 Pulse Width Modulation .......................................................................................33

3.6 Digital Control Algorithms ...................................................................................36

4 Design and Implementation.......................................................................................39

4.1 DC-DC Converter .................................................................................................39

4.2 DC-AC Inverter.....................................................................................................41

4.3 Digital Control System..........................................................................................44

5 Review of Results........................................................................................................51

5.1 DC-DC Converter Performance............................................................................51

x

5.2 DC-AC Inverter .................................................................................................... 54

5.3 Control System ..................................................................................................... 54

5.4 Conclusions........................................................................................................... 56

6 Conclusions and Discussion.......................................................................................57

6.1 Thesis Summary ................................................................................................... 57

6.2 Conclusions........................................................................................................... 58

6.3 Future Work......................................................................................................... 59

Appendix 1 – Hardware Specification ........................................................................61

Appendix II – Software.................................................................................................65

References ......................................................................................................................75

Datasheets ......................................................................................................................77

xi

List of Figures Figure 1: System Schematic ...........................................................................................14

Figure 2: Half Bridge, Push-Pull, and Full Bridge DC-DC Converter (Clockwise).....18

Figure 3: Switching and Conduction Power Loss ..........................................................19

Figure 4: Zero-Voltage and Zero-Current Switching.....................................................22

Figure 5: Switching Waveforms with Stray Circuit Inductance ....................................23

Figure 5: SG3825 Based Current Mode Control............................................................25

Figure 6: Digital Control Schema...................................................................................26

Figure 7: Parasitic Capacitance in the Power MOSFET ................................................28

Figure 8: Push-Pull DC-DC Converter...........................................................................29

Figure 9: Switching Waveforms for Isolated DC-DC Converter...................................29

Figure 10: Push-Pull Converter Inductor Voltage and Current......................................30

Figure 11: Full-Bridge Inverter ......................................................................................32

Figure 12: Sinusoidal Uni-Polar PWM ..........................................................................35

Figure 13: Push-Pull Converter Using Voltage Mode Control ......................................40

Figure 16: Feedback Circuitry (Note V6 is the simulated 240V Output) ......................43

Figure 17: Feedback Circuitry Simulation .....................................................................43

Figure 19: Main Service Routine ...................................................................................45

Figure 20: Complementary PWM with the SH-1...........................................................46

Figure 21: Channel 3 and Channel 4 of ITU Initialisation.............................................48

Figure 22: Channel 1 Interrupt Service Routine.............................................................49

Figure 23: Channel 3 Interrupt Service Routine.............................................................50

Figure 24: Switching DC-DC Waveforms .....................................................................52

Figure 25: Gate Drive waveforms and PWM Generation (10:1 Probe). ........................52

Figure 26: Switching Transients on Output (12V input, 10:1 Probe) ............................53

Figure 27: Uni-Polar PWM (not at 50hz).......................................................................55

Figure 28: Errors in Complementary PWM ...................................................................55

xii

List of Tables Table 1: PWM Terminology ...........................................................................................33

Table 2: SH-1 Terminology ...........................................................................................45

Chapter 1: Introduction

13

Chapter 1

1 Introduction

1.1 Background to the research

An inverter is a device that takes a DC (Direct Current) input and produces a sinusoidal

AC (Alternating Current) output. A high power converter is one that can be used to

power an entire home or workshop, from a battery bank - charged from a renewable

energy source or supply grid in UPS applications. An inverter needs to be designed to

handle the requirements of an energy hungry household yet remain efficient during

periods of low demand. Inverters can be designed in a number of topologies depending

on the situation and its requirements. The efficiency of the inverter is highly dependent

on the switching device, topology and switching frequency of the inverter. The aim of

this thesis is to produce an efficient DC to Single Phase 240 Volt AC inverter.

1.2 Research problem and hypotheses

The research problem can be split up into two major components - a step-up DC-DC

converter and a DC-AC Inverter. The overall system schematic can be seen in Figure 1.


14

Figure 1: System Schematic

The step-up DC-DC converter will step up 12V to 400V, using an isolated switch-mode

push-pull DC-DC step up converter. The switching device is a high power MOSFET

that was particularly attractive due to its high switching speeds and high power handling

capabilities at low voltages. The control for this stage was chosen to be a single IC

based analogue solution to allow the focus of this thesis to remain on the inverter stage.

The second stage of the converter inverts the 400V DC to a usable 240V 50hz AC

supply. By defining the output as usable implies that it must be within accepted

tolerance limits for total harmonic distortion and voltage regulation under a wide range

of predicted loads. This second stage will be designed using a standard full-bridge

configuration.

The central research problem is the implementation of this inverter with a

microprocessor based digital control system with some focus on ensuring maximum

system efficiency.

1.3 Justification

There are still a significant number of remote locations in Australia that are not

connected to a supply grid. Often, the cost of connecting these locations to the grid far

outweighs the initial expenditure required to set up some form of renewable energy

source on location. This proposition is made more attractive with the introduction of

high efficiency inverters. This is due to the fact that an inefficient inverter leads to

higher rating requirements on all preceding devices - often expensive solar panels and

12VDC – 400VDC

Push-Pull Converter

400VDC – 240VAC Full Bridge Inverter

Hitachi SH-1 32bit

RISC Microprocessor

12VDC 240VAC


15

battery banks. The cost of higher ratings on these preceding devices far outweighs the

cost of researching and designing an efficient high power inverter. Recent advances in

microprocessor technology has led to ‘single-chip’ solutions for the control of inverters

which makes complicated control systems cheap and efficient. This thesis hopes to

utilise these advances to create a high efficiency inverter capable of dealing with

varying supply and load conditions.

1.4 Outline of the report

Chapter 2 will begin with a literature review on all relevant recent articles written on the

subject of both high power inverters and their control.

Chapter 3 will give a theoretical outline to all concepts behind the design and

implementation of the entire system.

Chapter 4 will explain the implementation of both stages of the inverter and the control

system, detailing both hardware and software design.

Chapter 5 will list the results of testing on both stages of the inverter implementation,

with particular focus on stability and efficiency.

Chapter 6 will be include an analysis of data and attempt to draw appropriate

conclusions based on the experimentation. It will also look into future implications of

this research.

1.5 Conclusion

Clearly then, this thesis hopes to outline the research, design and implementation of a

high power inverter - specifically aimed at remote industrial or residential applications.

This will be carried out in a number of stages as outlined above, and all results will be

compared and contrasted, allowing conclusions to be drawn on the overall success of

the thesis.

Chapter 2: Review of Literature

17

Chapter 2

2 Review of Literature

There have been a large number of articles written concerning power conversion in

recent years. This can be attributed in part to the rise in popularity of high voltage DC

transmission systems - and their integration with existing AC supply grids. There is also

a consistent demand for high efficiency inverter devices for lower power applications -

like houses, boats, caravans, UPS and remote areas of the world. This chapter will

discuss and contrast recent literature concerning high power inverters and their control.

2.1 DC-DC Conversion

DC-DC conversion revolves around the conversion of a voltage source Vd to an

acceptably ideal output voltage Vo. This can be performed in a number of both isolated

and non-isolated topologies and in this case the DC-DC converter was chosen to be of

the isolated variety.

Various DC-DC Converter topologies exist – each with their own particular advantages.

Some simple circuit diagrams of the basic types of high power isolated DC-DC

Converters are shown below and have been taken from [2]:


18

Figure 2: Half Bridge, Push-Pull, and Full Bridge DC-DC Converter (Clockwise)

DC-DC Converter design tends to be a process of making tradeoffs between converter

size, cost and performance and it is this procedure that tends to push the designer

towards choosing a particular type of converter [11]. Recent literature on DC-DC

Converters of particular interest to this thesis, such as [9], outline complicated triple-

conversion control strategies that provide considerable opportunity for future

advancement of this device but are not included in the scope of this thesis.

2.2 DC-AC Inversion

In the scope of this thesis, the DC-AC inversion stage will be the most critical. With

quality design of the DC-DC stage it should have a stable DC supply to work with, but

it will have to cope with other issues such as reactive power correction and maintain a

good level of voltage regulation in the most efficient manner possible.

The circuitry used in the standard DC-DC Converter is re-used in AC-DC Converters –

with the exception of the isolating step-up/step-down transformer. In the same manner,

the choice of topology depends entirely on the situation and tradeoffs need to be made

with regards to limitations on power, efficiency and cost.


19

The most important part of the DC-AC Conversion process is in the generation of the

sinusoidal input signals to the gates of the MOSFETs. This will be covered in a later

section (2.5) on microprocessor control systems and PWM.

2.3 Power Switching

Designing power converters or inverters can be summarised into attempting to meet two

primary objectives:

• Supply harmonic free electrical power at a constant voltage for a variety of

loads, and have the ability to cope with a non-ideal supply.

• Supply this power as efficiently as possible with negligible electro-magnetic

interference.

Mohan, Underland and Robbins [2] describe the two main sources of loss as switching

power loss and conduction loss. These losses can be simply explained from the

following standard switching waveform taken from [2]:

Figure 3: Switching and Conduction Power Loss


20

From this figure, the following equations relating to power loss can be obtained:

Switching Losses: )(2

1coffconssss ttfIVP +=

Conduction Losses: s

ononons T

tIVP =

Several important conclusions can be drawn from these two equations:

• Switching Loss varies linearly with switching frequency and rise/fall times.

Hence switching frequency can be increased provided devices with small rise

and fall times are used.

• Conduction loss is directly proportional to the on-state voltage. Clearly, a

device needs to be chosen that minimizes the on-state voltage (directly due to

the MOSFET ‘On-Resistance’) to reduce conduction loss.

Clearly then, the switching device chosen should meet the above criteria as closely as

possible so as to maximise total efficiency of the device. The application of this theory

to the choice of switching device will be explained in chapter 4.

2.3.1 Ideal Characteristics of a Gate Drive

The ideal gate drive is one that:

• Provides sufficient drive power to keep the power switch in the on-state over the

complete range of operating voltages and currents.

• Ensure that the switch remains in its off-state and is not triggered by noise from

other switching devices.


21

• Drive circuitry should be directly coupled between the switching device and the

Microprocessor.

• Ensure that the switch turn on and turn off times are kept to a minimum.

In a standard MOSFET, the switching speed is directly related to the rate of supply of

charge to the gate-input capacitance [1]. The resulting drive circuitry, while remaining

as simple as possible, should attempt to use this fact to maximise the switching speed of

the MOSFET's.

2.3.2 Circuit Topologies

Various topologies are available to switch a standard power MOSFET - including

specialised driver IC’s. They range from a simple totem-pole or integrated circuit drive

to complicated drive circuitry as outlined in [1].

2.4 Soft Switching Techniques

With recent advances in converter and inverter design, engineers have begun pushing

developers to produce switching devices that will meet their needs. This however, is not

the only alternative. By ensuring that all switching occurs with zero-voltage or zero-

current in the switch many of the limitations inherent in the switching device can be

overcome - or perhaps even utilised - to improve converter performance. This type of

circuit design is called `soft-switching', and is easy to contrast to `hard-switching'.

2.4.1 Zero-Voltage and Zero-Current Switching

Looking back on figure 3 in Section 2.1.1 it becomes clear what is implied by zero-

voltage or zero-current switching. It is a means by which additional circuitry is added

external to the switch to either speed up or delay voltage or current rise/fall times to

ensure that they cross at, ideally, zero voltage and current. An idealised zero-voltage

zero-current switching pattern is shown in the following figure:


22

Figure 4: Zero-Voltage and Zero-Current Switching

This thesis mainly focuses on the control system and standard circuitry and as such will

not be utilising any circuitry to enable ZV-ZCS.

2.4.2 Snubbers

A snubber is typically introduced in a situation where there are high stresses on a

switching component. It provides a simple, though often inefficient, method of reducing

switching stresses by limiting not only transient voltages and currents - but also the rate

of change of these transient voltages and currents [2]. The typical choice that a design

engineer must make revolves around the trade off between using devices with the

required ratings and the cost and complexity of adding snubber circuitry.

In the context of this thesis, there are three main types of snubber circuitry protection

for transistor based switches [2]:

• Turn-Off: Provide zero-voltage across the transistor while the current turns off.

• Turn-On: Reduce the voltage across the transistor while the current turns on.

• Overvoltage: Reduce voltage spikes due to stray circuit inductance.

The following figure shows a typical switching waveform and switching loci taking into

account the effects of stray inductance:


23

Figure 5: Switching Waveforms with Stray Circuit Inductance

The actual circuit diagrams for each type of snubber, and in particular their application

to bridge inverters will not be covered in this section. Articles such as [7], introduce the

concept of `Active' snubbers – ‘Active’ in that they contain a controllable switching

element.

2.5.3 Resonant Approaches

Resonant approaches to soft switching attempt to use simple LC resonant tanks that

oscillate in response to the switch frequency to force the switches to zero-voltage or

current during the switching interval. As stated in [8], there are drawbacks to the

resonant approach of soft switching. These include the requirement of wide switching

frequency to respond to varying loads and the consequent difficulties associated with

filtering this wide frequency range. The circulating currents generated by the resonant

tank also contribute to higher conduction losses.

2.5 Control

Many of modern power applications involve multiple conversion stages – such as a

triple-conversion UPS system – that include complicated features such as battery

charging schemes, power factor correction, load protection, peak power tracking and

much more. Consequently, they tend to be the most complex and expensive type of

system to implement. Shamim Choudhury however, correctly states that, “Today’s low-

cost, high-performance digital signal processor (DSP) controllers … provide an

improved and cost-effective solution …” [9]. This thesis explores the use of a cheap

32bit RISC Microprocessor rather than a DSP chip to implement a similar style of

control scheme to the one outlined in the DC-AC Inverter segment of [9].


24

This section looks into microprocessor based PWM algorithms, options for feedback

loops and the advantages or disadvantages of each type.

2.6.2 Microprocessor PWM algorithms

There are a large number of approaches to generating sinusoidal PWM with a

microprocessor (or DSP). The simplest and most common method is to mimic analogue

comparator based PWM generation by comparing the value from a sinusoidal lookup

table with a triangular chopping wave (typically just an up/down counter) and thus

generate a sinusoidal PWM output directly. The beauty of this method is that the

amplitude of the chopping wave or sinusoid (and hence PWM width) can be easily

varied by changing registers in the microprocessor and thus a simple adaptive control

system can be implemented.

Another method researched is the use of a random number comparison with the control

sinusoid [3]. In this case, the control sinusoid is compared with a random number

generated by the microprocessor instead of the switching triangular wave. The reason

for this is that in standard sinusoidal PWM, the output is made up of a fundamental

component and a significant high frequency component [3]. This limits the converters

effectiveness in terms of interference and EMI. By using random number generation,

the high frequency component is spread out over a wider spectrum so that no

component has significant magnitude [3]. This solution however is limited by

complicated coding and high speed switching requirements.

2.6.3 Current Mode vs Voltage Mode Control Current mode control is a means of controlling switching inverters through the use of an

inner current control loop to directly control peak current – rather than controlling the

duty ratio of the pulse width modulator as in conventional voltage mode control. The

advantages of this type of control schema (described in [11]) are numerous:

• Improved transient response.

• Simpler control loops.


25

• Improved line regulation.

• Automatic flux balancing (ideal for push-pull configurations).

• Allows simple paralleling of multiple stages while maintaining equal current

sharing.

A simple schematic outlining the control mechanism for a simple IC based current

mode controller is shown below: (obtained from [11]):

Figure 5: SG3825 Based Current Mode Control

2.6.4 Control Systems

The load (or even the supply) on the final converter is never well defined – and the

designing engineer faces the dilemma of creating a system that will cope with an

‘expected’ range of operating conditions. This is done classically by implementing a

feedback PID (Proportional-Integral-Differential) control system as shown in the

following diagram [9]:


26

Figure 6: Digital Control Schema

In this case, the device is to be used as a simple and isolated AC source – as it contains

no circuitry to synchronise it to another AC supply. With this in mind, the control

algorithm used needs only to ensure that the output follows the control sinusoid over as

wide a range of loads as possible – and responds to step variations in the load quickly.

2.7 Summary

This chapter has given an insight into some of the fundamental concepts circulating

with regards to inverter design. The next chapter will provide an in depth coverage of

the particular components used in the design of this thesis.

Digital Controller

PWM Output Stage

Sensors A/D

Reference Input

- +

+ Output

Chapter 3: Theory

27

Chapter 3

3 Theory

This chapter will give a concise and complete coverage of all the theory relevant to the

design of this high power inverter. It will begin with a theoretical overview of MOSFET

switches, focusing on their switching characteristics. Following that will be a look into

the Push-Pull DC-DC converter and Full-Bridge inverter. An examination of sinusoidal

PWM followed by an overview of digital control algorithms and feedback circuitry will

complete the chapter.

3.1 Analysis of the Power MOSFET

The power MOSFET combines solid power handling capabilities – at low voltages -

with high switching speeds. This section will cover the operation of the power

MOSFET, its operating characteristics and its limitations.

3.1.1 Switching the Power MOSFET

MOSFETS are an intrinsically fast switching device because their operation does not

require the injection and removal of excess minority carriers like the BJT. The limiting

factors for the MOSFET are stray capacitances that effect the switching transients. In

particular, the gate-drain and gate-source parasitic capacitance have a severe effect on

Chapter 3: Theory

28

switching speed. The equivalent circuit of the MOSFET including these capacitance's is

shown below:

Figure 7: Parasitic Capacitance in the Power MOSFET

According to [4], there are three non-ideal commutation phenomena when MOSFET's

are used as power switches.

• A surge current flows through the MOSFET caused by the reverse-recovery

component of the freewheeling drain-source diode during turn-on. This surge

current dominates switching losses and dtdi / EMI noise.

• During turn on, the parasitic drain-source capacitor discharges adding to the

surge current. This can typically only be reduced by using resonant converter

techniques or active snubbers.

• The drain-source voltage increases rapidly during turn-off. This rapid voltage

increase is the prime source of turn-off switching loss and dtdi / EMI noise.

Chapter 3: Theory

29

These non-ideal properties can be reduced, or even eliminated, using external circuitry

to force zero-voltage or zero-current switching or designing drive circuitry in a way to

minimize these effects as outlined in articles [1], [4], [5], [6], [7], and [8].

3.2 The Push-Pull DC-DC Converter

This section will give an in-depth coverage of the Push-Pull DC-DC converter, with

particular focus on component selection limitations for the requirements of this thesis.

The push-pull DC-DC converter can be shown as follows:

Figure 8: Push-Pull DC-DC Converter

The Push-Pull converter uses a centre-tapped transformer and two switching devices to

achieve bi-directional core excitation. Due to the isolating transformer in the Push-Pull

DC-DC converters, `dead’ time needs to be inserted into the switching waveforms (to

ensure the primary winding is never short circuited). An example of the generation of

switching signals for an isolated DC-DC converter is given in the following figure:

Figure 9: Switching Waveforms for Isolated DC-DC Converter

Chapter 3: Theory

30

By analysing the circuit in figure 8, the following equation for inductor voltage (when

T1 is on) can be obtained:

odL VVN

Nv −=

1

2

From this circuit analysis the following waveforms for inductor voltage and current can

be obtained:

Figure 10: Push-Pull Converter Inductor Voltage and Current

By assuming that the circuit is in steady state, and equating the integral of inductor

voltage over one period to zero, the following relationship between input and output

voltage is calculated:

DN

N

V

V

d

o

1

22= %50<D

The limitation on duty cycle is clear given the restriction on both switches being on

simultaneously. In practice the duty cycle is restricted to slightly less than 50% to

ensure that the switches are not on simultaneously under any situation.

Chapter 3: Theory

31

By analysing this circuit when T1is on, it is clear that the voltage appearing across T2

would be equal to:

2

12 )(

N

NVvVV oLdT −+=

dT VV 2(max) =

Now using the equation for inductor voltage it is clear that the peak voltage across the

switch in its off-state is 2Vd. The peak output current flowing through a switch in its on-

state can be determined by noting that the peak output current will be constantly flowing

in the secondary of the transformer (from the assumption). This means that the peak

current across the switch is just this current shifted to the primary of the transformer:

peakoT iN

NI ,

1

2(max) =

Clearly then, these equations define the ratings required for both switching devices in

the DC-DC stage of this thesis. From this theory, a design including specific turn ratios

and predicted duty-cycles can also be created. Specifications on output ripple current

and voltage will determine the value of the output filter inductor and capacitor.

3.3 Transformer Selection

Transformer selection is influenced by the following factors – switching speed, power

loss and size. As switching frequencies are increased, generally a reduction of core size

or minimum number of turns can be realised [11]. A point exists however, where

increasing frequency increases core losses to the point that there can be no further

reduction in either core size or minimum number of turns [11]. This point is dependent

on the type of material chosen for the transformer core.

The other factor in a transformers efficiency – particularly at high frequency – is eddy

current losses in the transformer windings. This can be reduced by using bundles of

Chapter 3: Theory

32

numerous conductors or copper foil in higher current windings. From this optimisation

the ideal transformer for the situation can be constructed and utilised to increase overall

system efficiency.

3.5 The Full-Bridge DC-AC Inverter

This section will focus on the characteristics of the full-bridge inverter and give the

background required to read the following sections on the digital control system

designed to switch the full-bridge switches.

The full-bridge inverter was chosen as the inverting output stage for a number of

reasons. It is preferred over a half-bridge inverter because for an equivalent input

voltage, the full-bridge inverter can provide twice the ouput voltage. As [2] states, this

implies that for equivalent power output, the output current is halved. The full-bridge

inverter is also significantly more controllable - with the choice between bi-polar and

uni-polar switching giving the designer choice between ease of operation or a reduction

in EMI.

The following figure shows a standard full-bridge inverter:

Figure 11: Full-Bridge Inverter

Analysis of the full-bridge inverter to determine limitations on the switching devices

provides the following switch ratings:

dT VV =(max)

peakoT iI ,(max) =

Chapter 3: Theory

33

These relationships are easily obtainable from figure 11, by placing one set of switches

in the on state and examining the remaining two switches. These limitations allow the

designer to choose effective switching devices, and their appropriate drive circuitry, for

use in the final circuit.

3.4 Pulse Width Modulation

Pulse width modulation (PWM) describes, very generally, a method of varying the

width of an input pulse to a converter in an effort to control the output voltage or current

of that converter. Before examining PWM in detail, it is best to define some of the

terminology used:

Symbol Description Equation

Vtri Triangular Switching Waveform (standard PWM)

Vcontrol DC or Sinusoidal Control Waveform

ma Amplitude Modulation Ratio (Peak Voltage Ratio) tri

controla

V

Vm

ˆ

ˆ=

mf Frequency Modulation Ratio s

controlf f

fm =

Ts Period of one switching cycle (with reference to Vtri) s

s fT

1=

fs Switching frequency s

s Tf

1=

ton Time in one switching cycle that the switch is in the on-state son DTt =

D Duty Cycle - Ratio of `on-time' to switching period s

on

T

tD =

Table 1: PWM Terminology

Chapter 3: Theory

34

The reference to peak voltage in the calculation of the amplitude modulation ratio is due

to the assumption that the control signal is not a perfect sinusoid (if it is a sinusoid), and

as such would have harmonic components. Thus the amplitude modulation ratio

becomes more universal by defining it as the ratio of peak voltages.

3.4.1 Bi-Polar PWM

Bi-polar PWM refers to the technique of switching a full-bridge inverter in

complementary pairs (A+,B- and A-,B+) so that only two possible output voltages are

available: Vd and –Vd. This method produces an output from a full bridge inverter that

is the same as the waveform expected from a half bridge inverter – but with the power

handling advantages listed previously.

3.4.2 Uni-Polar PWM

This method of PWM allows transitions in the output between Vo and zero and –Vo and

zero. The following figure (obtained from [2]), clearly shows how a uni-polar PWM

signal is generated. The voltages specified on this diagram are with reference to the full-

bridge circuit shown in figure 11.

Chapter 3: Theory

35

Figure 12: Sinusoidal Uni-Polar PWM

The main reason that uni-polar switching is preferred over bi-polar switching is that it

effectively doubles the switching frequency and at the same time cuts maximum voltage

transitions in half.

A simple analysis of figure 22 shows that the voltages vAN and vBN are 90º out of phase

with each other. The switching frequency harmonic components of vAN and vBN however

have the same phase. Thus, switching frequency harmonics disappear from the output

voltage. The sidebands of the switching frequency harmonic component also disappear,

as does the dominant harmonic at twice the switching frequency. Clearly then, uni-polar

switching provides a significant reduction in EMI.

Chapter 3: Theory

36

Of importance here also is that the output voltage is dependent on the amplitude

modulation ratio ma through the following relationships:

daO VmV =1ˆ 0.1≤am

dOd VVVππππππππππππππππππππππππππππ4ˆ

1 <<

In these equations, 1ˆOV represents the peak value of the fundamental component of the

output voltage.

3.6 Digital Control Algorithms

PID Control is a significantly older art than the microprocessors they are now being

implemented on – but without a brief overview of basic control algorithms in their

digital form – the following sections outlining the software implementation would be

difficult to follow.

Referring back to figure 6 in section 2.6, the digital controller must use the error value

generated from comparison of the ‘reference’ with the ‘actual output’. The speed and

type of response depends on the type of system implemented. The term PID control

(proportional-integral-differential) refers to a simple control loop that uses a sum of past

errors (integral), the current error (proportional) and rate of change of errors

(differential) to vary the output in response to the error signal. The simplest equation for

PID control can be written as follows:

E(i) = Error Signal at the ‘ith’ sampling interval.

U(i) = Digital Controller output at the ‘ith’ sampling interval.

T

iEiEKjEKiEKiU d

i

jip

))1()(()()()(

0

−−++= ∑=

Chapter 3: Theory

37

Where Kp, Ki and Kd are the proportional, integral and differential gain coefficients

that characterise the controllers response and T is the sampling interval.

By looking at the above equation – it is clear that the proportional term depends only on

the current value of the error signal. The integral term however depends on a

summation of all previous error values and as such smooths oscillations and adds the

advantage of accumulating small errors that the proportional term would ignore. A

small error that has existed for a number of iterations would slowly build in the integral

term until it produced a change to correct the error. The derivative term looks at the rate

at which the error is changing and varies the control output accordingly. The

differential term is approximated closely enough by looking at only the previous change

in error divided by the sampling interval.

Implementing this control algorithm on a microprocessor is done by considering only

the incremental change in output signal between sampling intervals rather than

calculating the entire control equation at each sampling interval. The equation for

incremental variation in controller output can be determined by induction:

T

iEiEKjEKiEKiU d

i

jip

))2()1(()()1()1(

1

0

−−−++−=− ∑−

=

Now subtracting U(i-1) from U(i) yields:

)2()1()()1()( 321 −+−++−= iEKiEKiEKiUiU

Where the constants K1, K2 and K3 are given by:

pd

di

id

KT

KK

T

KTKK

TKT

KKpK

−=

−=

++=

3

2

1

2

Chapter 3: Theory

38

These constants are typically calculated once only at the start of the control routine –

evaluated from entered values for the PID constants. There are cases however, where

these constants are re-evaluated during the control cycle to achieve an optimum

response. This type of control is called adaptive control.

Chapter 4: Design and Implementation

39

Chapter 4

4 Design and Implementation The central aim of this thesis was to produce a working – though non-ideal - product to

illustrate that the control principles and theory behind it are sound. With this in mind,

the following sections explain the decisions made during the design and

implementation, with reference to earlier literature and theory sections.

4.1 DC-DC Converter The DC-DC Converter, under the scope of this thesis, was designed to provide a steady

400V output to allow implementation of the more complicated inverter stage. The

design was obtained primarily by re-working application notes concerning the Unitrode

3825 series of PWM Current-Mode control ICs – in particular application note U110

listed in [10]. As the primary focus of this thesis was on the control of the inverter

stage, this simplified DC-DC stage allowed more time to be spent on the inverter stage

as required.

4.1.1 Choice of topology

The Push-Pull topology was initially chosen due to both it’s ease of implementation, it’s

good power handling capabilities and isolation through a relatively small transformer (at


40

high switching frequencies). The initial choice of current mode control reinforced this

choice, as its inherent flux balancing is essential in the push-pull configuration to

prevent core saturation [4]. Time restrictions however forced the final design to discard

the current mode controller and instead consisted of a simple voltage mode controller

with current limiting capabilities.

4.1.2 The PWM Controller IC The UC3825 is ostensibly sold as a high-speed current mode PWM control IC. It has a

long list of features that made it particularly suitable for this application and – with the

detailed design note – made the construction and testing of the DC-DC stage as simple

as possible.

The following figure shows the basic diagram of a Push-Pull converter using Voltage

Mode control with Current Limiting[4]:

Figure 13: Push-Pull Converter Using Voltage Mode Control

While initial current mode control loops were tested – time limitations forced only a

simple current limiting feedback through the 3825’s internal current limiting pin.

4.1.3 Design Issues


41

The primary issues with the design of this stage was on the choice of components which

was heavily dependent on two design choices – namely switching frequency and output

power.

The choice of switching frequency was a difficult one in that switching losses and

magnetic component sizes decrease with switching frequency – at the expense of noise

limitations and faster switching devices. This decision was made easier by the wide

range of high speed MOSFETs available while PCB design was used to minimise

circuit noise in an effort to produce error free operation. Output power was selected to

show primarily the viability of the control scheme and to remain low enough to allow

bread boarding of the inverter stage to ease in testing and fault finding.

The final design settled on a switching speed of 100Khz at 100W. The final design can

be found in the appendices.

Transformer design was made quite complicated by the combination of high power and

high switching frequency requirements. The final transformer used was obtained from

Oatley Electronics and is used in a simple 110W CFL Inverter kit. By utilising a pre-

built transformer that was used in a similar circuit at the same frequency only

rudimentary testing needed to be undertaken to ensure it functioned as required.

4.1.4 Feedback Control The feedback control loops for this section were designed with simplicity in mind. The

voltage feedback consists entirely of a resistive bridge to scale the 400V signal into the

5V range that is fed directly back to the inverting input of the error op-amp. A variable

resistor was attached to the non-inverting input to provide a variable reference voltage.

No compensation was used in the feedback loop – although it was catered for in the

PCB design to facilitate later testing if time permitted.

4.2 DC-AC Inverter

The DC-AC Inverter was built around a standard full-bridge topology due entirely to its

high power handling capabilities. The input voltage is provided by the DC-DC stage


42

and is assumed to be 400V ± 20V. With this in mind, a simple PID control system was

implemented using a Hitachi SH1 32bit RISC Microprocessor with voltage feedback to

produce the 240VAC output. This section will explain the decisions made in choosing

components and drive circuitry.

4.2.1 Circuitry

The circuitry utilised in the inverter stage is a standard hard-switched full-bridge

topology. The full-bridge topology was chosen due to its power handling capabilities

and the ability to provide bi-polar PWM and thus effectively double the switching

frequency of the output (as mentioned in chapter 3).

The switching components are standard 500V MOSFETs, chosen for minimal Rds,on and

high speed switching characteristics. The devices chosen were IRF460s. Drive

circuitry was kept as simple as possible, and utilised the IRF2110 driver IC from

International Rectifier. These IC’s have both high and low-side outputs and can switch

high-side MOSFET’s up to 600V - which make them ideal for this configuration. The

datasheet included in the appendices details the exact specifications of the IRF2110.

While isolation was definitely an issue in the feedback path, the voltage divider and

amplification op-amp provided enough protection at this power level to protect the

microprocessor. The simulated circuitry also contained two Shottky diodes placed to

limit the output of the op-amp to the microprocessor supply rails – thereby ensuring no

transient under or over voltage spikes would destroy the Microprocessor A/D port. The

following simple op-amp based feedback path was used for voltage feedback to the SH1

A/D port. The SH1 A/D ports have a dynamic range of 0-5v. This signal was then used

as an input to the PI Algorithm.


43

Figure 16: Feedback Circuitry (Note V6 is the simulated 240V Output)

This circuitry was initially tested in PSpice to verify its functionality and the following

response noted:

Figure 17: Feedback Circuitry Simulation


44

4.3 Digital Control System The ‘heart’ of this inverter is the Hitachi SH1 microprocessor. This controller was

utilised to perform what is a very simple PI control algorithm to supervise the output

voltage. The following section describes the choice of control algorithm and software

design issues.

4.2.2 The Hitachi SH1 The Hitachi SH RISC family “combines the computational ability of a high speed RISC

core with embedded Multiply-Accumulate hardware and extensive on-board peripheral

function to enable a virtual single chip PID controller.” [10]. This thesis uses the first

channel of the ITU (Internal Timer Unit) to generate interrupts at 500uS intervals to

read the voltage data from the first AD channel and implement the control algorithm.

Channel 3 and 4 of the ITU are used in complementary PWM mode - with

programmable deadtime - to generate the chopping waves for sinusoidal PWM.

4.2.3 PID Controller

The PID Controller was implemented as outlined in chapter 3. The constants were to be

determined experimentally – from observations of the output response to step changes

in the load. The code for the PID control loop used a number of arrays to store previous

values of error signal – and also to ensure that the MAC functions of the SH-1 are

utilised [10]. The code for this can be clearly seen in the appendices.

4.2.4 Software Organisation The software was divided into three main sections, these being the main service routine,

the initialisation routine and the interrupt handlers.

The Main Service Routine:

The main service routine consists of a simple branch to initialisation code and then an

infinite loop.


45

Figure 19: Main Service Routine

Initialisation Code:

The initialisation code simple sets up the ITU to operate as follows:

Channel 1: Generate a interrupt every 500uS. The interrupt handler will ensure that

output voltage sampling and PID and correction calculations are done. This routine will

provide the new values for the buffer registers (BRB3/BRA4) but the interrupt handlers

for Channel 3 and 4 will actually perform the write to these buffer registers.

Channel 3 and 4: These channels were used in complementary PWM mode to output

the unipolar PWM signal to the gates of the full-bridge circuit. This section is easiest to

explain with a few simple definitions:

Signal Name Description

GRA3 General Register A for Channel 3 (Sets max. amplitude of chopping

wave).

GRA/B General Registers for Channel 3/4 (Used to vary the width of the

PWM signals).

TCNT3/4 Up-Down Counters for Channel 3 and 4.

BRA/B Buffer Registers A and B (for each channel). Value in these

transferred to GRA/B at each TCNT overflow or underflow.

Table 2: SH-1 Terminology

Initialise ITU, A/D, IO and Interrupts. Start ITU

Counters.

Infinite Loop


46

The following diagram illustrates clearly just how these up-down counters and the

GRA/B Registers are used to generate a PWM signal.

Figure 20: Complementary PWM with the SH-1

Clearly then, by varying the value in GRB3 and GRA4 with an output generated from a

comparison of a reference sinusoid with the output voltage then simple sinusoidal PWM

can be generated.

The major design issues with this segment of the code is with regards to changing the

values in GRB3 and GRA4 while the system is operating. Consider, for example, if the

value of GRB3 is changed after TCNT3 matches but before TCNT4 matches. This

would force an un-desired non-sinusoidal output. This is where the buffer registers

come in to action. The buffer registers are transferred into their respective general

registers on peaks or troughs of the chopping wave. The only issue then, is to ensure

that the cases of buffer register values in the space between the relative maxima and


47

minima of TCNT3 and TCNT4 are dealt with correctly. The following text is an

excerpt from a Hitachi Design Note [9], and explains the limitations on these changes

quite clearly:

“If T is the difference between TCNT3 and TCNT4, the non-overlapping distance, then

let us define:

• Max(TCNT3) = GRA3 + 1 = Max value obtained by TCNT3

• Max(TCNT4) = GRA4 + 1 – T = Max value obtained by TCNT4

• Min(TCNT4) = 0x0000 = Min. value attained by TCNT4

• Min(TCNT3) = T – 1 = Min. value attained by TCNT3

With this in mind the following precautions must be taken with regards to register

updates:

If a control register is currently set to a value between Max(TCNT3) and Max(TCNT4),

and the next value is going to be outside this range, it must be done when TCNT4

underflows rather than when TCNT3 overflows. The buffer register can still be used to

update the control register, but care must be taken to update the buffer register between

the time of a TCNT3 overflow and a TCNT4 underflow.

If a control register is currently set to a value between Min(TCNT3) and Min(TCNT4),

and the next value is going to be outside this range, it must be done when TCNT3

overflows rather than when TCNT4 underflows. The buffer register can still be used to

update the control register, but care must be taken to update the buffer register between

the time of a TCNT4 underflow and a TCNT3 overflow.

If a control register is to be updated in such a way as to create a 0% duty cycle, writing

a value greater than GRA3 to the buffer register can do this. Care must be taken,

however, to do it while the chopping wave is decrementing. This is the time between a

TCNT3 overflow and a TCNT4 underflow.


48

If a control register is to be updated in such a way as to create a 100% duty cycle,

writing a value greater than GRA3 to the buffer register can do this. Care must be

taken, however, to do it while the chopping wave is incrementing. This is the time

between a TCNT4 underflow and a TCNT3 overflow.”

Clearly then, this defines a simple set of conditions which allow safe updating of the

buffer registers. This can be seen quite clearly in the interrupt routines for Channel 3

and 4 in the code.

To set up each channel to operate correctly the following code was used:

Figure 21: Channel 3 and Channel 4 of ITU Initialisation

The final step in the initialisation process was to set up the A/D Converter to operate

through port 0 and also code to ensure that all I/O ports are correctly configured.

Set TCNT3 not cleared by match with GRA3/GRB3. Count Rising Edges Only. Use system clock.

Clear all Interrupt Flags.

Disable interrupt on GRA3/B3 Match. (See CH1 Interrupt Code)

Set maximum amplitude of chopping wave (GRA3).

Set initial value for TCNT3. (Keeping non-overlapping time in mind).

Set TCNT4 not cleared by match with GRA4/GRB4. Count Rising Edges Only. Use system clock.


Disable interrupt on GRA4 /B4 Match. (See CH3 Interrupt Code)

Set initial value for TCNT4. (Keeping non-overlapping time in mind).


49

Interrupt Handlers:

The first interrupt handler is that for Channel 1 – which executes every 500uS and

performs all the necessary steps to execute the PI control loop.

Figure 22: Channel 1 Interrupt Service Routine

The PI Controller evaluates new values for GRB3 and GRA4 – although it doesn’t

actually write those values to the buffers. Due to the restrictions on the updates of

GRB3 and GRA4 it is left to the service routines for the Channel 3 and Channel 4

interrupts to actually write the values to the buffer.

The channel 3 and 4 interrupt handlers are enabled only when the PI Controller needs to

write new values to the buffer registers. This is the reason that they are initially

disabled and only turned on by the Interrupt Service Routine for Channel 1. The

following software flow chart is derived directly from the conditions stated earlier in

this chapter. The following chart has some small pictures designed to illustrate the

‘rule’ it is trying to enforce.

Read AN0 as input to A/D Converter and perform ADC conversion.

Execute Inverter PI Controller.

Clear Channel 3 interrupts and enable Channel 3 interrupts.



50

Figure 23: Channel 3 Interrupt Service Routine

The channel 4 Interrupt handler simply allows the designer to set the PWM output to

100% duty cycle in either channel – it is performed in the channel 4 interrupt handler

because it is too late to perform the change after the channel 3 interrupt has occurred.

The earlier limitations stated that a 100% duty cycle write must be performed when the

chopping wave is incrementing (ie. At a channel 4 underflow).

4.3.3. Conclusion

The software outlined above completely and simply controls the inverter stage of this

thesis. The remainder of the code included in the appendices simply links together

these core sections and is heavily commented to allow future modifications.

Chapter 5: Review of Results

51

Chapter 5

5 Review of Results

The system outlined above was implemented and tested both on breadboard and PCB.

While the final results weren’t as successful as originally planned – they did serve to

highlight some of the areas of difficulty with a design of this type. Testing on the

PCB’s for both stages showed that the hardware design was valid and the following

results were noted.

5.1 DC-DC Converter Performance The DC-DC Stage performed quite well after some early problems with the PCB design.

The waveforms to the MOSFET pair showed no noticeable ringing or any other major

undesirable effects, and the circuit seemed to perform very well to variations in input

voltage (limited downwards by the voltage requirements of the UC3825). It showed a

steady no load voltage of 373V for inputs ranging between 10V and 30V. The

following waveforms show the MOSFET gate drive waveforms and also the feedback

signals in operation.


52

Figure 24: Switching DC-DC Waveforms

The generating signal and feedback circuitry also seemed to work quite well, as the

following two diagrams (both recorded at different supply voltages) will testify. It is of

importance to note here that the output voltage recorded for both of these graphs (the

first at 16V input, the second at 14V) was still 373VDC (no load).

Figure 25: Gate Drive waveforms and PWM Generation (10:1 Probe).


53

This clearly reinforces the theory shown with regards to the feedback control of a push-

pull converter – and illustrates quite clearly how the waveforms are generated by the

UC3825.

Initial problems with the design resulted in the early destruction of a pair of MOSFET’s

and the initial transformer. Small modifications to the design – which mainly included

the introduction of a 400V 470uF Low ESR (equivalent series resistance) capacitor on

the output – along with a set of fast recovery diodes in place of the standard line

frequency diodes. This solved all of the apparent problems with the board – and under

small load conditions (1-10W) it performed very well. The following waveforms were

obtained looking at the AC component of the output voltage transposed onto the gate

drive signals:

Figure 26: Switching Transients on Output (12V input, 10:1 Probe)

These switching transients, at a peak of 0.2V in 400V are clearly not of concern.

Power consumption seemed to be quite small – considering that very little of the design

process was concerned with maximising inverter efficiency. At no-load the circuit drew

0.09A at 12V from the power supply (it did fluctuate and as such the 0.09A should be


54

taken as a rough average of the supply current). Under small load conditions the current

drawn remains quite small – at 0.09A at 12V – with a 160kOhm Load over 374V. This

gives a rough efficiency measurement of only 28% - which is very poor considering

most modern converters have efficiencies well into the 80% range.

Higher loads required significantly increased supply current – which was unavailable

during testing as it needed to draw in excess of 5A to be tested at it’s rated power. This

poor efficiency however would only be mirrored at higher loads.

5.2 DC-AC Inverter The DC-AC Inverter circuitry failed to work on PCB. Initial testing on breadboard did

indicate that the circuit design was valid when switching small voltages (20VDC).

However, any attempt to switch the 400V supplied by the DC-DC Converter resulted in

no output whatsoever.

This result is clearly the due to late addition of the IR2110 – and insufficient testing on

the breadboards. The initial design attempted to use BJT’s in a totem pole configuration

to drive the MOSFET’s directly from the microprocessor, this was scrapped however

with the intention of using specialist MOSFET driver IC’s – like the HIP4081 or

IR2110. The idea of switching the high voltage full-bridge with the IR2110 is the best

design – as the HIP4081 cannot handle over 80V - it just needs considerably more

refinement and testing before it will function as required.

The feedback circuitry was constructed using a standard LM358 op-amp and did

function as outlined in the SPICE simulation in chapter 4. Later problems with the

control system did not allow this circuitry to be tested within the circuit – but it should

prove useful to later students.

5.3 Control System The control system was also something of a disappointing section. Initial testing

showed that the Complementary PWM mode of the SH-1 functioned exactly as required

– and in fact is clearly built for this type of application. The initial set up verified the


55

500uS interrupt on channel 0, and the introduction of the sinusoidal complementary

PWM into channel 3 and 4 also produced good results as the following graph depicts:

Figure 27: Uni-Polar PWM (not at 50hz).

This graph was obtained looking at the outputs of TIOCA3 and TIOCA4 – the primary

PWM outputs. The troubles began when the outputs of TIOCB3 and TIOCXA4 – the

complementary outputs – were examined:

Figure 28: Errors in Complementary PWM


56

Clearly – the top waveform is the output of TIOCA3 as in figure 25, the bottom

waveform however is the output of TIOCB3. These signals are supposed to be

complementary as set by the SH-1. Their subtraction then should produce a bi-polar

PWM signal. Clearly – the second waveform is not functioning as the complement of

the top waveform – as it seems to be ‘resetting’ at a similar point in each cycle.

All of the obvious solutions – such as invalid addressing of the Sine table, unwanted

interrupts and incorrect setting of the registers controlling complementary PWM were

carefully examined and no obvious solution was apparent. Article [10] outlines the use

of a SH-1 to perform a very similar style of PWM (albeit three-phase) – and uses

exactly the same settings as the code presented in this thesis to initialise channel 3 and 4

into Complementary PWM mode. This problem completely halted progress on this

section of the inverter for over three weeks – and no solution was found during the

course of this thesis.

The other side effect of the failure of the PWM code was that the PID control system

could not be tested. The code was written and is included in the appendices. The A/D

Converter was also coded and tested – and did function correctly.

5.4 Conclusions The overall system did not function as required – although the information gathered on

the design of a power DC-AC inverter may prove invaluable for future undergraduate

students. The work into utilising the SH-1 for this type of application should also prove

useful – even if only by highlighting some of the pitfalls of a project of this kind.

Chapter 6: Conclusions and Discussion

57

Chapter 6

6 Conclusions and Discussion

Clearly, despite the type of the outcome of a research and development project of this

kind, conclusions can be drawn that will aid further research into the area. This thesis

provides considerable ground for additional research – in a number of areas – and also

brings to light some lessons to be learned in switch-mode power supply design.

6.1 Thesis Summary This thesis has covered the research, development and testing of a high power inverter

capable of producing 240VAC from a 12V DC source. The thesis was developed in

three stages – a DC-DC Step Up stage, a DC-AC Inversion stage that was controlled by

the third stage – a PID control algorithm on a Hitachi SH-1 Microprocessor.

The literature review covered recent literature concerning power inverters, their control

and some of the recent advances in circuit and component design that can be used to

increase the inverters performance and reliability. The following chapter outlined the

relevant theory behind switch-mode inverters – paying particular attention to the push-

pull DC-DC converter and the full-bridge inverter. It also gave a thorough background

to microprocessor based control schemes and sinusoidal PWM.


58

This chapter was followed by a detailed design explanation – that covered each stage in

detail and outlined the major design decisions that were made. This thesis then covered

the results obtained from the prototype inverter – and highlighted the areas success and

failure of each stage.

The appendices contain complete circuit schematics, PCB layouts, code from the SH-1

and datasheets for the SG3825, IRF2110 and a small brief on the Hitachi SH-1.

6.2 Conclusions This thesis was clearly not as successful on the surface as was originally hoped. Of all

three stages – only one produced the required outputs – and even that performed at a

very sub-standard level. Despite this, many conclusions can be drawn that place the

results of this thesis in a more ‘successful’ light.

• The design of a high power inverter involves the creation of several quite

complicated power conversion stages. This thesis is the first attempt at building

a complete inverter at the University of Queensland, and as such will provide a

considerable basis for future work.

• The work into interfacing the Hitachi SH-1 into a switch mode power supply has

clearly shown that it is an ideal processor for this kind of task. The opportunities

for this processor to be used in later work of this nature is substantial. The

additional functionality a microprocessor of this nature can add to a converter –

like that found in a standard on-line UPS – can easily be controlled by the SH-1.

• All circuitry designed was kept as simple as possible – yet room was made for

small modifications – such as closed loop current mode control – that could

significantly increase the systems response to varying loads or a non-ideal

supply.


59

The major question that needs to be answered is “Why was the thesis unsuccessful?”

This can be answered in a number of ways. In hindsight quite a few things would have

been done differently – the major one being concentrating less on the ‘theoretical’

journal articles and instead concentrating on application notes, design notes, datasheets

and the like. With a more ‘practical’ grounding from the beginning of the design

process, more informed decisions with regards to the circuits functionality can be made.

Decisions made early on in the design process cropped up late in the testing stages and

caused significant disruption to the thesis – for example, neglecting to use fast-recovery

diodes in the push-pull converter was quite definitely an oversight and combined with

other small bugs caused quite a large amount of valuable time to be lost.

The evaluation board for the SH-1 was also not obtained until late in the project –

another mistake in misjudging what would be required to generate a ‘simple’ sinusoidal

PWM signal. This, combined with the hardware problems made developing a working

prototype a very difficult task.

In conclusion, this thesis needed to be more thoughtfully planned from inception – and

would benefit greatly from the attention of more than one student in future years.

6.3 Future Work

The future work of most interest of this type depends on what the following students see

as the ultimate aim of a power inverter – for example, UPS applications or remote

power supply applications. At the conclusion of this thesis, I see the most valuable path

being the pursuit of a UPS style application. This provides significant ground for future

work – as most UPS systems consist of multi-levels of power conversion and very

intelligent control systems.

Despite this, there is great potential for a inverter of this type – with an embedded SH-1

– to be modularised into small inverters that can be paralleled into a high power system.

This has particular application to the current federal government and private programs

to grid connect personal solar panels – and literally cause the electricity meter to turn


60

backwards while home owner’s are not using electricity. It would be no small task to

add PFC (power factor correction) and grid synchronisation to an inverter of this kind –

but could prove to be an interesting thesis topic once the initial bugs that have stalled

the development of this thesis have been ironed out. In this new era of ‘clean’

electricity – the demand for intelligent and efficient inverters of this type will be

growing rapidly.

Appendix I - Hardware

61

Appendix 1 – Hardware Specification

DC-DC Converter Schematic


62

DC-AC Converter Schematic


63

DC-DC PCB


64

DC-AC PCB

Appendix II - Software

65

Appendix II – Software

This section contains the following files:

Pid.H: This file contains all of the local variables used in the generation of the

sinusoidal PWM signals and also the constants for the PID control loop.

Vects.c: This file lists the interrupt locations and the handlers assigned to them (only

three in this case).

Inv.c: This file contains all of the code for running the control of the full-bridge

inverter. It set’s up the ITU, A/D and I/O. Currently only tested to the stage outlined in

the thesis document.

Note: Several other linking and assembler files are included with the C Compiler for the

SH-1. These standard files were not modified and so are not included.


66

Pid.H: /*************************************** Pid.H: Clifton Cunningham 8/10/99 This file contains constants for the inverter code. ****************************************/ char temp_char; unsigned int data_a = 0x0000; /*Record current data for CH3 PWM*/ unsigned int data_b = 0x0000; /*Record current data for CH4 PWM*/ unsigned int current_pos = 0x0000; /*Current location in sin table*/ unsigned int MAX_CH0 = 0x04e2; /*Determines freq of CH0 Int - 500uS*/ unsigned int T; /*PID period*/ unsigned int T3_MAX = 0x02d6; /*Max level of chopping wave*/ unsigned int T3_min = 0x001f; /*Minimum level of TCNT3*/ unsigned int T4_max = 0x02b7; /*Maximum level of TCNT4*/ unsigned int deadtime = 0x20; /*Difference between TCNT3 and TCNT4*/ unsigned int Kp = 100; /*PID Constants*/ unsigned int Ki = 3; unsigned int Kd = 12; signed int K[3]; /*PID gain factors*/ signed int error[3]; /*Storage of previous error calcs*/ unsigned int A100_SET; unsigned int B100_SET; unsigned int Sin[0x0200] = { 0x016B,0x016F,0x0174,0x0178,0x017D,0x0181,0x0186,0x018A,0x018F, 0x0193,0x0197,0x019C,0x01A0,0x01A5,0x01A9,0x01AD,0x01B2,0x01B6, 0x01BB,0x01BF,0x01C3,0x01C8,0x01CC,0x01D0,0x01D4,0x01D9,0x01DD, 0x01E1,0x01E5,0x01E9,0x01EE,0x01F2,0x01F6,0x01FA,0x01FE,0x0202, 0x0206,0x020A,0x020E,0x0212,0x0216,0x021A,0x021E,0x0222,0x0226, 0x0229,0x022D,0x0231,0x0235,0x0238,0x023C,0x0240,0x0243,0x0247, 0x024A,0x024E,0x0251,0x0255,0x0258,0x025B,0x025F,0x0262,0x0265, 0x0269,0x026C,0x026F,0x0272,0x0275,0x0278,0x027B,0x027E,0x0281, 0x0284,0x0286,0x0289,0x028C,0x028F,0x0291,0x0294,0x0296,0x0299, 0x029B,0x029E,0x02A0,0x02A2,0x02A5,0x02A7,0x02A9,0x02AB,0x02AD, 0x02AF,0x02B1,0x02B3,0x02B5,0x02B7,0x02B9,0x02BA,0x02BC,0x02BE, 0x02BF,0x02C1,0x02C2,0x02C4,0x02C5,0x02C6,0x02C8,0x02C9,0x02CA, 0x02CB,0x02CC,0x02CD,0x02CE,0x02CF,0x02D0,0x02D1,0x02D1,0x02D2, 0x02D3,0x02D3,0x02D4,0x02D4,0x02D5,0x02D5,0x02D5,0x02D6,0x02D6, 0x02D6,0x02D6,0x02D6,0x02D6,0x02D6,0x02D6,0x02D6,0x02D5,0x02D5, 0x02D5,0x02D4,0x02D4,0x02D3,0x02D3,0x02D2,0x02D1,0x02D1,0x02D0, 0x02CF,0x02CE,0x02CD,0x02CC,0x02CB,0x02CA,0x02C9,0x02C8,0x02C6, 0x02C5,0x02C4,0x02C2,0x02C1,0x02BF,0x02BE,0x02BC,0x02BA,0x02B9,


67

0x02B7,0x02B5,0x02B3,0x02B1,0x02AF,0x02AD,0x02AB,0x02A9,0x02A7, 0x02A5,0x02A2,0x02A0,0x029E,0x029B,0x0299,0x0296,0x0294,0x0291, 0x028F,0x028C,0x0289,0x0286,0x0284,0x0281,0x027E,0x027B,0x0278, 0x0275,0x0272,0x026F,0x026C,0x0269,0x0265,0x0262,0x025F,0x025B, 0x0258,0x0255,0x0251,0x024E,0x024A,0x0247,0x0243,0x0240,0x023C, 0x0238,0x0235,0x0231,0x022D,0x0229,0x0226,0x0222,0x021E,0x021A, 0x0216,0x0212,0x020E,0x020A,0x0206,0x0202,0x01FE,0x01FA,0x01F6, 0x01F2,0x01EE,0x01E9,0x01E5,0x01E1,0x01DD,0x01D9,0x01D4,0x01D0, 0x01CC,0x01C8,0x01C3,0x01BF,0x01BB,0x01B6,0x01B2,0x01AD,0x01A9, 0x01A5,0x01A0,0x019C,0x0197,0x0193,0x018F,0x018A,0x0186,0x0181, 0x017D,0x0178,0x0174,0x016F,0x016B,0x0167,0x0162,0x015E,0x0159, 0x0155,0x0150,0x014C,0x0147,0x0143,0x013F,0x013A,0x0136,0x0131, 0x012D,0x0129,0x0124,0x0120,0x011B,0x0117,0x0113,0x010E,0x010A, 0x0106,0x0102,0x00FD,0x00F9,0x00F5,0x00F1,0x00ED,0x00E8,0x00E4, 0x00E0,0x00DC,0x00D8,0x00D4,0x00D0,0x00CC,0x00C8,0x00C4,0x00C0, 0x00BC,0x00B8,0x00B4,0x00B0,0x00AD,0x00A9,0x00A5,0x00A1,0x009E, 0x009A,0x0096,0x0093,0x008F,0x008C,0x0088,0x0085,0x0081,0x007E, 0x007B,0x0077,0x0074,0x0071,0x006D,0x006A,0x0067,0x0064,0x0061, 0x005E,0x005B,0x0058,0x0055,0x0052,0x0050,0x004D,0x004A,0x0047, 0x0045,0x0042,0x0040,0x003D,0x003B,0x0038,0x0036,0x0034,0x0031, 0x002F,0x002D,0x002B,0x0029,0x0027,0x0025,0x0023,0x0021,0x001F, 0x001D,0x001C,0x001A,0x0018,0x0017,0x0015,0x0014,0x0012,0x0011, 0x0010,0x000E,0x000D,0x000C,0x000B,0x000A,0x0009,0x0008,0x0007, 0x0006,0x0005,0x0005,0x0004,0x0003,0x0003,0x0002,0x0002,0x0001, 0x0001,0x0001,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, 0x0000,0x0000,0x0001,0x0001,0x0001,0x0002,0x0002,0x0003,0x0003, 0x0004,0x0005,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B, 0x000C,0x000D,0x000E,0x0010,0x0011,0x0012,0x0014,0x0015,0x0017, 0x0018,0x001A,0x001C,0x001D,0x001F,0x0021,0x0023,0x0025,0x0027, 0x0029,0x002B,0x002D,0x002F,0x0031,0x0034,0x0036,0x0038,0x003B, 0x003D,0x0040,0x0042,0x0045,0x0047,0x004A,0x004D,0x0050,0x0052, 0x0055,0x0058,0x005B,0x005E,0x0061,0x0064,0x0067,0x006A,0x006D, 0x0071,0x0074,0x0077,0x007B,0x007E,0x0081,0x0085,0x0088,0x008C, 0x008F,0x0093,0x0096,0x009A,0x009E,0x00A1,0x00A5,0x00A9,0x00AD, 0x00B0,0x00B4,0x00B8,0x00BC,0x00C0,0x00C4,0x00C8,0x00CC,0x00D0, 0x00D4,0x00D8,0x00DC,0x00E0,0x00E4,0x00E8,0x00ED,0x00F1,0x00F5, 0x00F9,0x00FD,0x0102,0x0106,0x010A,0x010E,0x0113,0x0117,0x011B, 0x0120,0x0124,0x0129,0x012D,0x0131,0x0136,0x013A,0x013F,0x0143, 0x0147,0x014C,0x0150,0x0155,0x0159,0x015E,0x0162,0x0167 };


68

Vects.c: /************************************************************************ Interrupt vectors section - SH1 created 6-Sep-95 :: PBB Modified: 5/10/99: Clifton Cunningham ************************************************************************/ /*********************************************************************** Place the prototypes for interrupt service routines here */ void start (void); /* Startup code (in start.s) */ void stack (void); /* infact this is a constant! */ void pid_control (void); /*CH0 isr*/ void int3 (void); /*CH3 ISR*/ void int4 (void); /*CH4 isr*/ /*********************************************************************** Typedef for the function pointer*/ typedef void (*fp) (void); /*********************************************************************** Place the interrupt service routine symbols in the table to create the vector entry */ const fp HardwareVectors[] __attribute__ ((section (".vects"))) = { start, /* Reset vector (hard, NMI high) */ stack, /* Stack pointer from hard reset */ start, /* Reset vector (soft, NMI low) */ stack, /* Stack pointer from soft reset */ (fp)0L, /* Illegal instruction exception */ (fp)0L, /* Reserved */ (fp)0L, /* Illegal slot exception */ (fp)0L, /* Reserved */ (fp)0L, /* Reserved */ (fp)0L, /* CPU Address error */ (fp)0L, /* DMAC Address error */ (fp)0L, /* NMI */ (fp)0L, /* User Break */ /*************** Reserved */ (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, /*************** TRAPA 0-31*/ (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, /*************** IRQs 0-7 */


69

(fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, /*************** DMAC 0-3 */ (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, /*************** ITU 0 */ pid_control, /* IMIA0 */ (fp)0L, /* IMIB0 */ (fp)0L, /* OVI0 */ (fp)0L, /* Reserved */ /*************** ITU 1 */ (fp)0L, (fp)0L, (fp)0L, (fp)0L, /*************** ITU 2 */ (fp)0L, (fp)0L, (fp)0L, (fp)0L, /*************** ITU 3 */ int3, (fp)0L, (fp)0L, (fp)0L, /*************** ITU 4 */ (fp)0L, (fp)0L, int4, (fp)0L, /*************** SCI 0 */ (fp)0L, (fp)0L, (fp)0L, (fp)0L, /*************** SCI 1 */ (fp)0L, (fp)0L, (fp)0L, (fp)0L, (fp)0L, /* Parity control unit */ (fp)0L /* A/D */ }; /***********************************************************************/


70

Inv.C: /************************************************************************** SH7000/7600 APPLICATION CODE FOR HIGH POWER INVERTER CREATED: 9/10/99 BY CLIFTON CUNNINGHAM FUNCTION: Produce a sinusoidal unipolar (four outputs) to drive the full-bridge Inverter. Also implement a small PID control algorithm. ***************************************************************************/ #include "iosh7030.H" /*Include port definitions for SH7032*/ #include "pid.H" /*local variables and sin table*/ #define THESIS 1 #define FINISHED 0 #define LED_ON 0x8000 #define FULL 0xFFFF extern inline set_interrupt_mask(char); /*Unknown – but required*/ void setup_io(void) /*Function : Set up the IO Ports TIOCA3 -> Port B, bit 2 (Drive Q1) TIOCB3 -> Port B, bit 3 (Drive Q2) TIOCA4 -> Port B, bit 4 (Drive Q4) TIOCXA4 -> Port B, bit 6 (Drive Q3) LED -> Port B, bit 15 (Flashing Led)*/ { PFC_PBIOR = 0xFF3F; /*Set outputs as outlined above*/ PFC_PBCR1 = 0x0000; /*Leave entire upper register as general I/O (inc. PB15)*/ PFC_PBCR2 = 0x22A0; /*Set Ports above to TIOC Modes...*/ /*Might as well initialise the PID variables here*/ K[0] = Kp +Kd/T+Ki*T; K[1] = Ki*T – 2Kd/T; K[2] = Kd/T – Kp; } void setup_ad (void) /*Function: Setup the AD to read in the fedback voltage value (set up in scan mode)*/ { ADCSR = 0x39; ADCR = 0x7f; } void setup_itu(void) /*Function : Setup ITU – channels as outlined in thesis*/


71

{ /*General ITU Settings*/ temp_char = ITU_TSTR; ITU_TSTR = 0x00; /*Stop all Counters*/ ITU_TSNC = 0xE0; /*All channels run independently*/ ITU_TFCR |= 0x6E; /*Set Ch3/Ch4 in CPWM, both in buffer mode*/ ITU_TOCR = 0xFF; /*Channel 0 to operate at 500uS Interrupts*/ ITU_TCNT0 = 0x0000; /*Clear up counter before start*/ ITU_GRA0 = MAX_CH0; /*Get first count value - const.*/ ITU_TCR0 = 0x23; /*TCNT cleared by GRA using internal/8 */ ITU_TIOR0 = 0; /*GRA used but with no inputs/output pins*/ ITU_TSR0 = 0; /*Make sure all status flags cleared*/ ITU_TIER0 |= 0X01; /*Enable Interrupt from GRA compare match*/ /*Now set up channel 3 and 4*/ ITU_TCR3 = 0x00; /*Ch 3 Not cleared by GRA3/GRB3 Match*/ temp_char = ITU_TSR3; /*Read before write*/ ITU_TSR3 = 0x00; /*Clear status register*/ ITU_TIER3 = 0x00; /*Disable Interrupts*/ ITU_GRA3 = T3_MAX; /*Set maximum amplitude of chopping wave*/ ITU_GRB3 = 0x016b; /*Initialise GRB3 with first element of sine wave*/ ITU_BRB3 = 0x016b; /*Initialise BRB3 with first element of sine wave*/ ITU_TCNT3 = 0x016a; /*Initialise TCNT3*/ ITU_TCR4 = 0x00; /*Ch 4 Not cleared by GRA4/GRB4 Match*/ temp_char = ITU_TSR4; /*Read before write*/ ITU_TSR4 = 0x00; /*Clear status register*/ ITU_TIER4 = 0x00; /*Disable Interrupts*/ ITU_GRA4 = 0x016b; /*Initialise GRA4 with first element of inverse sine wave*/ ITU_BRA4 = 0x016b; /*Initialise BRA4 with first element of inverse sine wave*/ ITU_GRB4 = 0x0016b; ITU_BRB4 = 0x0016b; ITU_TCNT4 = ITU_TCNT3 - deadtime; /*Initialise TCNT4*/ /*Set Interrupt Priority Registers*/ INTC_IPRC |= 0x00A0 ; /*Set ITU Ch 0 at highest*/ INTC_IPRD |= 0x0CB0 ; /*Set ITU Ch 4 then Ch 3*/ } #pragma interrupt void pid_control(void) /*Function : PID Control Loop*/ { unsigned int ad_value;

current_pos += 0x0D; /*Step required to generate 50Hz from 500uS*/ if(current_pos >= 0x0200){ current_pos = 0x0200 - current_pos; /*Reset current_pos on sin table overflow*/ }


72

/*Read in current value from output*/ do { ;; } while (ADCSR && 0x80 == 0); ADCSR |=0x7f; /*Clear adf bit and begin a new conv.*/ ad_value = AD_DRA; /*This will give us a voltage in the range from 0x0000 to 0xFFFF (0-5V). Scale it down to the same amplitude as the control sine wave*/ ad_value = ad_value/0x02d6; error[0]=Sin[current_pos] – ad_value; data_a += K[0]*error[0]+K[1]*error[1]+K[2]*error[2]; data_b+= (0x02d6 – data_a); error[1] = error[0]; /*for next iteration*/ error[2] = error[1]; /*This PID loop has not been tested*/

temp_char = ITU_TSR3; ITU_TSR3 = 0x00; ITU_TIER3 |= 0x01; /*Enable Interrupts on Ch 3*/ ITU_TSR0 &= 0xFE ; /*Clear flag */ } #pragma interrupt /*Function: To ensure buffers are updated at the correct time (particularly with respect to the 'danger' areas as outlined in thesis document.*/ void int3 (void) { if (data_a < T3_min) { /*Is it in the lower boundary area?*/ ITU_BRB3 = 0x7fff; /*If so - Set it to 0% Duty Cycle*/ } else { if (data_a > T4_max) { /*Is it in the upper boundary area?*/ A100_SET=0x01; /*Set flag to get INT4 to set 100%*/ temp_char=ITU_TSR4; /*duty cycle.*/ ITU_TSR4 = 0x00; ITU_TIER4 |= 0x04; /*Enable channel 4 OVF interrupt*/ } else { ITU_BRB3=data_a; /*Otherwise just write to buffer*/ } } if (data_b < T3_min) { /*Is it in the lower boundary area?*/ ITU_BRA4 = 0x7fff; /*If so - Set it to 0% Duty Cycle*/ ITU_BRB4 = 0x7fff; }


73

else { if (data_b > T4_max) { /*Is it in the upper boundary area?*/ B100_SET=0x01; /*Set flag to get INT4 to set 100%*/ temp_char=ITU_TSR4; /*duty cycle.*/ ITU_TSR4=0x00; ITU_TIER4 |= 0x04; /*Enable channel 4 OVF interrupt*/ } else { ITU_BRA4=data_b; ITU_BRB4=data_b; /*Otherwise just write to buffer*/ } } ITU_TSR3 &= 0xFE ; /*Clear flag */ ITU_TIER3 = 0x78; /*Disable Interrupts*/ } #pragma interrupt /*Function: To ensure buffers are updated at the correct time (particularly with respect to the 'danger' areas as outlined in thesis document.*/ void int4 (void) { if(A100_SET == 0x01) { ITU_BRB3 = 0x7fff; /*Set for 100% Duty Cycle*/ A100_SET = 0x00; /*Clear flag*/ } if(B100_SET == 0x01) { ITU_BRA4 = 0x7fff; /*Set for 100% Duty Cycle*/ ITU_BRB4 = 0x7fff; B100_SET = 0x00; /*Clear flag*/ } ITU_TSR4 &= 0xFB ; /*Clear flag */ ITU_TIER4 = 0x78; /*Disable Interrupts*/ } main() { set_interrupt_mask(3); /*Intetrupt mask at 5 - adi not accepted*/ setup_io(); /*Setup PB-15 as led control*/ setup_itu(); /*Setup ITU to control flash rate*/ ITU_TSTR = 0x79; /*Start the counter*/ while (THESIS != FINISHED) { } } int __main(){} /*Required by compiler*/

References

75

References

1. S. Musumeci, A. Raciti, A. Testra, A. Galluzo, and M. Melito, ``Switching Behaviour Improvement of Insulated Gate-Controlled Devices,'' IEEE Trans. Power. Electron., vol. 12, no. 4, pp. 645-653, 1997.

2. N. Mohan, W. Robbins and T. Undeland, ``Power Electronics - Converters,

Applications and Design (2nd Ed),'' Wiley and Sons, New York, 1995.

3. S.Y.R. Hui, I. Oppermann, and S. Sathiakumar, ``Microprocessor-Based Random PWM Schemes for DC-AC Power Conversion,'' IEEE. Trans. Power. Electron., vol. 12, no. 2, March 1997.

4. J.G. Cho, G. Hua, F.C.Y. Lee, and J.A. Sabate, ``Zero-Voltage and Zero-Current

Switching Full Bridge PWM Converter for High-Power Applications,'' IEEE. Trans. Power. Electron., vol. 11, no. 4, July 1996.

5. H. Akagi, H. Ayano, and S. Ogasawara, `Àn Active Circuit for Cancellation of

Common-Mode Voltage Generated by a PWM Inverter,'' IEEE. Trans. Power. Electron., vol. 13, no. 5, September 1998.

6. C.L. Chen, and C.J. Tseng, ``Novel ZVT-PWM Converters with Active

Snubbers,'' IEEE. Trans. Power. Electron., vol. 13, no. 5, September 1998.

7. J.G. Cho, C.Y. Jeong, and F.C.Y. Lee, ``Zero-Voltage and Zero-Current-Switching Full-Bridge PWM Converter Using Secondary Active Clamp,'' IEEE. Trans. Power. Electron., vol. 13, no. 4, July 1998.

8. Y.T. Chen, `À New Quasi-Parallel Resonant DC Link for Soft-Switching PWM

Inverters,'' IEEE. Trans. Power. Electron., vol. 13, no. 3, May 1998.

9. S. Choudhury, `Ìmplementing Triple Conversion Single-Phase On-line UPS using TMS320C240'' Texas Instruments Application Report, SPRA589, September 1999.

10. K. Schultz, `Àn Application of the Low Cost Hitachi SH-1 RISC Controller for

PID Control of a Three-Phase Brushless DC Motor System,'' Hitachi Application Note, Preliminary V0.1, PMH11IA05D1, September 1997.

11. B. Andreycak, “1.5Mhz Current Mode IC Controlled 50 Watt Power Supply,”

Unitrode Application Note, no. U-110, Unknown Publication Date.

12. K.J. Astrom, `Àutomatic Tuning of PID Controllers,'' Instrument Society of America, New York, 1988.

References

76

13. P.G. Barbosa, L.G. Rolim, E.H. Watanabe, and R. Hanitsch ``Control Strategy for grid-connected DC-AC converters with load power factor correction,'' IEEE. Proc. Gener. Transm. Distrib., vol. 145, no. 5, September 1998.

Datasheets

77

Datasheets

A High Power Inverter for Remote Applications

Documents

Transcript of A High Power Inverter for Remote Applications