A Fully-Integrated 5GHz CMOS Wireless-LAN Receiver
Transcript of A Fully-Integrated 5GHz CMOS Wireless-LAN Receiver
A Fully-Integrated 5GHz CMOSWireless-LAN Receiver
Hirad Samavati
Center for Integrated Systems
Stanford University
Motivation
Introduction to Wireless LAN
Receiver Architecture
Circuit Implementations
Offset Cancellation Techniques
Fractal Capacitors
Measurements
Conclusions
Outline
• Demand for wideband wireless local area network (LAN)
- High data rate (> 20Mb/s)
- Low cost (CMOS)
- Low power
• New released frequency band in US
- Unlicensed national information infrastructure (U-NII) band
• Existing frequency band in Europe
- High performance radio LAN(HIPERLAN) band
Motivation
• U-NII and HIPERLAN frequency bands.
• Proposed channel allocation for a U-NII band WLAN system.
- Compatible with HIPERLAN.
HIPERLAN U-NII
5.15 5.30 5.35 5.725 5.825 GHz
GHz5.15 5.35
23.5MHz
Available Frequency Bands
Modulation GMSKMaximum signal level -25dBmSensitivity -70dBmChannel bandwidth 23.5MHzSpurious emissions 30MHz-1GHz 1GHz-25.5GHz
-57dBm-47dBm
HIPERLAN Receiver Requirements
NF < −143.7dBm/Hz − 12dB − (−174dBm/Hz)=18.3dB
Sensitivity
Pre-detection SNRAvailable noise power of the antenna
(-70dBm)/(23.5MHz)
Receiver Architecture
VCO
LNA
PFDChargePump
Vc
Filter
Loop
Image-Reject PLL
Tracking
BufferI
Q
VCO
Tracking ILFD
Loop FilterCharge
PFD
2Prescaler
N/N+1
Program &Pulse Swallow
Counters
Channel Select Bits
8
LO1 Buffers
fref
Pump
LO2 Buffers
Synthesizer
Baseband
Differential Input5.15-5.35 GHz
Quadrature
+
+
+
_Σ
Σ
Q I Q I
Fractal Capacitors
BufferBaseband
Filter
LO Frequencies
Satellite downlink
LO1LO2
1617------ ωSig⋅1
17------ ωSig⋅
Sig.Img.
÷2LO1 LO2
Low-power injection-locked frequency divider
÷8
• Image signal is small.
• LO2 easily obtained from LO1.
Image Rejection
In
M3
M1
X
Out
Zf
• Series resonance @fImg→ improves image rejection
fsigfimgFrequency
VOut f( )VIn f( )------------------
fmin fmax
Parasitic capacitance Cx degrades the noise performance.
Noise Rejection
In
M3
M1
XCx Lx
• Parallel resonance @fSig→ improves noise figure
fsigfimg
FrequencyN
oise
Fig
ure Without LX
With LX
fmin fmax
Solution: Third-Order Filter
Z f s( )L5 C3 C1+( ) s
21+⋅ ⋅
C1 C3 L5 s3⋅ C3 s⋅+⋅ ⋅
---------------------------------------------------------=
ωp 0=
ωp1
L5 C1⋅---------------------±=
ωz1
L5 C3 C1+( )⋅---------------------------------------±=
C3
C1L5
Zf
LNA/Filter Transfer Function
fsigfimg
Frequency
VOut f( )VIn f( )------------------
1gm3---------
log
Z f f( )log
fmin fmax
fsigfimgfmin fmaxIn
OutM3
M1
C3
C1L5
Zf
1/gm3
Equivalent Noise Circuit for the LNA
M1
X
Cx
Zin
Ls
Lg
M3 Iout
+−
+−
Vs2
Vg12
I g12
I d32Rs
Rin1 Cx
1/gm3gm3V3Gm1V1
+
−
+
−
V1 V3
Iout
Second stageFirst stage(all noise sources modeled)
(Only drain noisemodeled)
Filter Noise Model
I d52
I L52
C3
C1CxL5
1gm5----------–
ψ I d52
I L52
+
1GL5-----------
Simplifies to
Where ,
and F1 is the noise figure of the first stage defined in: D. Shaeffer and T. Lee, “A1.5V, 1.5 GHz CMOS Low Noise Amplifier”, IEEE Journal of Solid-State Circuits,May 1997, pp. 745-759.
Fno filter– F1 4Rsγ3gdo3
ω02
ωT2
------- Cx
2
gm32
---------ω02
+=
Fwith ideal– filter– F1=
Ftot F1 ψ 4R⋅ s γ5gdo5 GL5+( )ω0
2
ωT2
-------
+=
ψC3
2 ω⋅ 02
C32
Cx C3+-------------------
2
ω02⋅ GL5 gm5–( )2
+
-----------------------------------------------------------------------------=
Noise Formulas
Receiver Architecture
VCO
LNA
PFDChargePump
Vc
Filter
Loop
Image-Reject PLL
Tracking
I
Q
LO1 Buffers LO2 Buffers
+
+
+
_Σ
Σ
Q I Q I
Fractal Capacitors
BufferBaseband
Filter
LO1 LO2Synthesizer
BufferBaseband
Circuit Implementation: LNA and filter
M5 M6
M1 M2
M3 M4
I1 (Const. gm source)
I2 (Const. gm source)
C1 C2C3 C4
L1 L2
L3 L4
L5 L6
In-In+
Filter
LNA
Vc
Receiver Architecture
VCO
LNA
PFDChargePump
Vc
Filter
Loop
Image-Reject PLL
Tracking
I
Q
LO1 Buffers LO2 Buffers
+
+
+
_Σ
Σ
Q I Q I
Fractal Capacitors
BufferBaseband
Filter
LO1 LO2Synthesizer
BufferBaseband
- A. Shahani, et al, “A 12-mW wide dynamic range front-end for a por-
table GPS receiver,” IEEE J. Solid-State Circuits, vol. 32, pp. 2061-
2070, Dec. 97.
Circuit Implementation: First Mixers
M1 M2
M3 M4LO1
LO1
RF+ RF-
IF+
IF-
LO1
LO1
Receiver Architecture
VCO
LNA
PFDChargePump
Vc
Filter
Loop
Image-Reject PLL
Tracking
I
Q
LO1 Buffers LO2 Buffers
+
+
+
_Σ
Σ
Q I Q I
Fractal Capacitors
BufferBaseband
Filter
LO1 LO2Synthesizer
BufferBaseband
Loop Mixer
Circuit Implementation: VCO and Loop Mixer
M5 M6
M1 M2
M3 M4
I3
C1 C2C3C4
L5 L6
VCO
Loop Mixer
LO1
LO1
Vbias
Vbias
Vc
RF+ RF-
IF+
IF-
LO1
LO1
Receiver Architecture
VCO
LNA
PFDChargePump
Vc
Filter
Loop
Image-Reject PLL
Tracking
I
Q
LO1 Buffers LO2 Buffers
+
+
+
_Σ
Σ
Q I Q I
Fractal Capacitors
BufferBaseband
Filter
LO1 LO2Synthesizer
BufferBaseband
Circuit Implementation: Second Mixers
LO+
-
+In -In
+Out -Out
Ib
To Current Summing Resistors
DC Offsets
BasebandAmp
LOLO Leakage
BasebandAmp
LO
InterfererLeakage
• Capacitive Coupling
- Requires a large capacitor
• Negative Feedback
- Nonlinear
• TDMA offset Cancellation
- Requires a large capacitor
DC Offset Cancellation Techniques
BasebandAmp
LO
BasebandAmp
LO
-a
BasebandAmp
LO
MOS Capacitor
Switch
Traditional Capacitors
Gate Capacitance:
Junction Capacitance:
High capacitance per unit areaNonlinearRequires DC bias voltageLow breakdown voltageMedium Q
Highly nonlinearRequires DC bias voltageSensitive to process variationsLow QLarge temperature variation
Metal to Metal / Poly Capacitance:LinearHigh QSmall temperature variationLow capacitance per unit area
Thin-Insulator Capacitors:Linear
Not available in standard CMOSExpensive
• Lateral flux improves capacitance density.
• Structures with large periphery are desirable.
• Some fractals have finite area but infinite perimeter.
Improving Capacitance Density
Fractal Capacitor
Horizontal spacing=0.6µm
Vertical spacing=0.8µmCapacitance boost factor=2.3
# of cross-connected layers=4
Scalability
Unlike conventional parallel-plate structures, thecapacitance per unit area increases as the processtechnologies scale.
Reduction of the Bottom-Plate Capacitance
First Terminal
First Terminal
Substrate
Second Terminal
Second Terminal
Area is smaller.
Some of the field lines terminate on the adjacentplate instead of the substrate.
Improved Matching
5.4pF 5.5pF 5.6pFCapacitance
0
1
2
3
4
5
6N
umbe
r of
dic
eCentral sites
Capacitance distribution across the wafer
σcentral=9.4fF (0.2%)
22mm
8”
m=5.5pFσ=83fF
CAD Tool
LGFCLayout Generator for Fractal Capacitors
LGFCField
Tech. File
Fractal
User
Layout
Report
CSolver Ls & rs
Input
Lib.
Receiver Architecture
VCO
LNA
PFDChargePump
Vc
Filter
Loop
Image-Reject PLL
Tracking
I
Q
LO1 Buffers LO2 Buffers
+
+
+
_Σ
Σ
Q I Q I
Fractal Capacitors
BufferBaseband
Filter
LO1 LO2Synthesizer
BufferBaseband
CapacitorArea:131x165µmCapacitance value:15pFBottom-plate capacitance/terminal:1.2pFSelf-resonance frequency:11.3GHz
Capacitance density: 700aF/µm2
Capacitance boost factor:3.5Resistor
Area: 103x61mmResistance value:2.1MΩBottom-plate capacitance/terminal:0.3pF
Offset Cancellation Circuit
Corner frequency5kHz
Die Area:4mm2
Technology:0.24-µm CMOS
Die Micrograph
Measured Receiver NF
5.15 5.20 5.25 5.30
Frequency (GHz)
5.35
Noi
se F
igur
e (d
B)
6.8
7.0
7.2
7.4
7.6
7.8
8.0
Measured Image Rejection
5.15 5.20 5.25 5.30Frequency (GHz)
47.0
49.0
51.0
53.0
55.0
57.0Im
age
Rej
ectio
n (d
B)
Ch1 Ch2Ch3
Ch4Ch5 Ch6 Ch7 Ch8
5.35
IP3 Measurement Results
-40 -35 -30 -25 -20 -15 -10 -5 0Source Power (dBm)
-80
-60
-40
-20
0
20O
utpu
t Am
plitu
de (
dBV
)Two-tone test (f1=5.263, f2=5.265GHz)
IIP3=-7dBm
1-dB Compression-Point Measurement
-50.0 -40.0 -30.0 -20.0 -10.0Source Power (dBm)
-30.0
-20.0
-10.0
0.0
10.0
20.0O
utpu
t Vol
tage
(dB
V)
1dB
-18 dBm
1-dB Blocking Desensitization Point
-700 -500 -300 -100 100 300 500 700-24
-22
-20
-18
-16
-14
Offset Frequency (MHz)
LO1Blo
ckin
g S
ourc
e P
ower
(dB
m)
Measured S11 of the Receiver
Frequency (GHz)
S11
(dB
)
4.0 4.5 5.0 5.5 6.0-25
-20
-15
-10
-5
0
Measured Performance Summary
Signal path performance Noise figure Voltage gain S11
Image rejection (filter only) Image rejection (total) Input-referred IP3 1-dB compression point LO1 Leakage to RF LO2 Leakage to RF
Achieved7.2dB26dB< -14dB16dB53dB-7dBm-18dBm-87dBm-88dBm
Required18.3dB
-21dBm-47dBm-57dBm
Power dissipation Synthesizer Divide-by-8 (for LO2) Signal path Image-reject PLL LO buffers Biasing Total power Supply voltage
25.3mW6.0mW18.5mW3.1mW5.0mW0.9mW58.8mW1.8V
Implementation Die area Technology Package
4mm2
0.24-µm CMOS32-pin ceramic flat pack
• Im -LAN receiver.
Th
• De
• D ning tech-
ni image-reject
PL
plementing the first 5GHz CMOS wireless
e receiver is:
- highly integrated
- low power
- highly linear and tolerates large blockers
veloping a novel RF filter topology that:
- rejects the image signal
- improves the LNA noise figure
emonstrating the feasibility of automatic tu
ques at RF frequencies using a low power
L.
Contributions
• Im ing fractal
ge
• De tors including:
• De erate custom
fra
plementing a novel capacitor structure us
ometries.
monstrating the benefits of fractal capaci
- area efficiency
- linearity
- scalability
- reduced bottom-plate capacitance
- improved matching characteristic
veloping a CAD tool to automatically gen
ctal layouts.
Contributions