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Int. J. Electron. Commun. (AEÜ) xxx (2013) xxx– xxx

Contents lists available at SciVerse ScienceDirect

International Journal of Electronics andCommunications (AEÜ)

jo ur nal ho me page: www.elsev ier .com/ locate /aeue

fully integrated 2.4 GHz CMOS high power amplifier using parallellass A&B power amplifier and power-combining transformer for

iMAX application

hmad Rahati Belabad ∗, Nasser Masoumi, Shahin J. Ashtianichool of Electrical and Computer Eng., Department of Electronics, RF Circuits and Systems Lab., College of Engineering, University of Tehran, Tehran, Iran

a r t i c l e i n f o

rticle history:eceived 15 December 2012ccepted 7 June 2013

eywords:MOS

a b s t r a c t

A new structure integrated power amplifier with watt-level output power is presented in a standard0.18 �m CMOS process for WiMAX applications. A parallel cascode class A&B power amplifier with opti-mized widths is proposed to increase linearity and efficiency simultaneously. A novel interleaved PCTpower combiner is proposed for increasing output power that combines output current of two similarclass A&B power amplifiers. Proposed interleaved transformer heightens coupling factor compared to

ower amplifier (PA)arallel class A&B PAransformeriMAX

typical transformer.The proposed power amplifier with 3.3 V power supply provides maximum output power of 32.5 dBm

and power added efficiency of 37.9% at 2.4 GHz operating frequency. The proposed power amplifierexhibits high output power of 32.3 dBm at 1 dB compression point. The simulation results for proposedPA with modulated OFDM signal show that −31 dB error vector magnitude at the average power of 25 dBm

can be achieved.

. Introduction

Today, fully integration of analog, digital and even RF functionss inevitable work in advanced wireless communication industryn order to reduce manufacturing cost and size. The most effec-ive way for this implementation has been CMOS technology thatlready is dominant way for implementation of RF, analog andaseband digital transceiver circuits [1]. Power amplifiers are mainlocks for constructing wireless communication systems [2]. Also,adio frequency power amplifiers are one of challenging blocks inesigning RF transceivers. Because of low cost and easy fabrica-ion of CMOS technology, this technology has been proposed andsed for designing and implementation of many power amplifierst various applications [3–7].

While a PA consumes a majority of DC power in the RF front-nd side, a highly efficient PA with high output power is necessaryor longer battery life in wireless applications. However, because ofow breakdown voltage and lossy substrate of CMOS compared toII–V devices, the design of an efficient CMOS PA with high output

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ower remains a challenging task [8]. In other word, the design of high performance power amplifier has bound designers to useomplicated procedures for compensating mentioned problems of

∗ Corresponding author.E-mail addresses: a.rahati@ece.ut.ac.ir (A. Rahati Belabad), nmasoumi@ut.ac.ir

N. Masoumi), sashtiani@ut.ac.ir (S. J. Ashtiani).

434-8411/$ – see front matter © 2013 Elsevier GmbH. All rights reserved.ttp://dx.doi.org/10.1016/j.aeue.2013.06.004

© 2013 Elsevier GmbH. All rights reserved.

CMOS technology [9]. When CMOS technology is famous for lowpower driving; additional function is required for increasing outputpower of PA, i.e. power combiner that combines several power cellsin order to achieve high output power. The schematic diagram ofpower combiner is shown in Fig. 1.

As shown in Fig. 1, M differential power amplifiers are connectedto the power combiner which combines the output current or volt-age of power amplifiers. The combiner also converts the differentialsignals to single ended signals.

Recently, the most successful attempts for creating a componentthat performs impedance matching and power combining simul-taneously have been done. One of functions that fulfill this workis transformer that according to the class of combining current orvoltage is classified into series-combining transformers (SCTs) andparallel-combining transformers (PCTs), respectively [10]. Trans-formers are superior to transmission-line based parallel-combiningstructures in terms of integration and design simplicity [11]. Theyalso have wider operating bandwidth and less optimization issuesthan the LC-based network exploited in [12].

Wireless communications create many challenges upon poweramplifiers for current and modern applications. The requirementof high-speed date rate causes using of complex digitally mod-ulated signals at OFDM mode. These days WiMAX standard is

lly integrated 2.4 GHz CMOS high power amplifier using par-for WiMAX application. Int J Electron Commun (AEÜ) (2013),

one of the prominent standards in the world. WiMAX that standsfor “Worldwide Interoperability for Microwave Access” is the lasttechnology and generation for broadband wireless access. It isbased on IEEE 802.16 standards [13]. The WiMAX standard provides

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AEUE-51059; No. of Pages 8

2 A. Rahati Belabad et al. / Int. J. Electron. C

Power

Combiner

V11

V12

V21

V22

VM1

VM2

Output

PA1

PA2

PAM

uwmtlo

pancdtr

2c

peuohm1sctteuPufiFi

cmoioiaP

p2mi

Fig. 1. Block diagram of parallel-combining PA.

p to 15 Mbps of data rate and 28 MHz of signal bandwidth with aireless coverage of four to six miles [14]. However, using OFDModulation in WiMAX applies a lot of restrictions in scaled CMOS

echnology [15]. Dealing with radio frequency (RF) signals modu-ated with high complexity, PAs must simultaneously achieve highutput power, high peak-power efficiency, and good linearity [9].

In this work, a fully integrated power amplifier with high out-ut power using a parallel class A&B for WiMAX applications in

standard 0.18 �m CMOS process is presented. In Section 2, aew interleaved power-combining transformer is proposed thatan increase coupling coefficient. In Section 3, the design proce-ure and all components of power amplifier are described. Finally,he simulation results of the new designed power amplifier and theesults compared to several other PAs are presented in Section 4.

. The new interleaved transformer design as powerombiner

Recently, power combiners as a method for increasing outputower, impedance matching and converting differential to single-nded signal in power amplifier circuits have been extensivelysed. Also in the last decade, the power combiner architecture inrder to produce high power with low voltage CMOS transistorsas been noticed. A distributed active transformer (DAT) is one ofethods which is used for generating the output power more than

W [16]. However, a large area of chip is allocated to DAT and tran-istors are laid near the transformer in this structure. Because ofircular shape of this transformer and coupling the input signal withhe transformer, this structure may cause instability [17]. Using aransformer as PCT and SCT with detailed simulations and analyticalxpressions were analyzed in [10] and then it has been extensivelysed in designing power amplifiers with high output power. UsingCT as a power combiner was used in [9,10,18–21] and SCT has beensed in [15,22–26] for increasing the output power of power ampli-ers. The schematic diagram of a 2 × 1:2 transformer is shown inig. 2(a). This transformer is constructed from two primary wind-ngs which have magnetic coupling with the secondary winding.

Fig. 2(a) shows the outputs of two power amplifiers which areonnected to the primary windings of transformer and because ofutual inductance between primary and secondary windings the

utput current will be the ratio of input current at primary wind-ngs. Fig. 2(b) depicts the physical layout of 2 × 1:2 transformer. Inrder to achieve an output power more than 1 W, in this design PCTs preferred to SCT because PCT has lower area than SCT. Addition-lly, in terms of power-combining ratio and transformer efficiencyCT is better than SCT.

The idea of interleaved structure is used for designing the

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ower-combining transformer [27]. The top view of proposed × 1:2 interleaved transformer is shown in Fig. 2(c). Each wideetal in Fig. 2(b) by using the interleaved structure is divided

nto two metals with equal widths for increasing the coupling

PRESSommun. (AEÜ) xxx (2013) xxx– xxx

coefficient, and are placed in parallel between secondary adjacentlayers. The three-dimensional proposed interleaved power-combining transformer layout is shown in Fig. 2(d). To study moreover this layout, each first winding of proposed transformer isshown with one secondary winding in Fig. 2(e). In Fig. 2(e), if twoprimary windings laying over together with the secondary wind-ing, this layout of transformer will be the same layout in Fig. 2(c).For the stability purpose, the input ports align in the left side andthe output port is aligned in the right side of the transformer. Theproposed transformer has two input ports (P1, P2) and one outputport (P3). The input ports (P1, P2) are connected to the drain ofpower amplifier and the output port (P3) is connected to the resis-tive load. The standard 0.18 �m CMOS process with six aluminummetal layers was used for designing this transformer.

Four metal layers are used in this transformer which the mainmetals are located in the top layer. The underpass layers are placedin the bottom metal layers that have 0.53 �m thickness. The pro-posed interleaved transformer has a size of 780 �m × 800 �m. Thethickness of substrate is 200 �m and the metal is Al with conduc-tivity 3.65e7 S/m. In the design procedure of the transformer, thephysical parameters such as the outer dimension, metal widthsand the spacing between metals are important parameters foroptimizing the transformer. The outer dimension effectively deter-mine self-inductance values for mutual coupling, the widths andthickness determine the quality factors for primary and secondarywinding inductors and the spacing between two adjacent metalsis trade-off between capacitive coupling and mutual coupling intransformers. At first, because the output power more than 1 W isrequired for designing the power amplifier, metal widths in thistransformer and the spacing of metals are chosen 30 �m and 5 �m,respectively. After using the method of interleaving, the metalwidths are chosen 15 �m.

In this paper, two transformers are designed and simulatedusing ADS momentum; the interleaved and typical transformer andtheir results are compared at 2.4 GHz frequency in Table 1. All speci-fications of two transformers such as area, spacing, technology, andmetal thicknesses are equal and the only difference between themis the interleaved metals.

The inductance values of primary and secondary windings fromthe layout are calculated as follows:

L1 = Im(Z11)ω

(1)

L2 = Im(Z22)ω

(2)

where L1 and L2 are primary and secondary inductances of thetransformer. As shown in Table 1, the interleaved structure causesthe self-inductance of the primary and secondary windings todecrease. The self-inductance of the primary and secondary wind-ings of typical transformer is 1.9 nH and 4.79 nH, respectivelyand these values for the interleaved transformer are 1.58 nH and4.13 nH. Also, the quality factor Q, the coupling coefficient K, andthe mutual inductance M are calculated as follows:

QP = Im(Z11)Re(Z11)

, QS = Im(Z22)Re(Z22)

(3)

K(L1, L2) = M√L1L2

=√

(Y−111 − Z11)Z22

Im(Z11)Im(Z22)(4)

where QP and QS are the quality factor for primary and secondary

lly integrated 2.4 GHz CMOS high power amplifier using par-for WiMAX application. Int J Electron Commun (AEÜ) (2013),

winding, respectively. The quality factor for primary and secondarywindings of the typical transformer is 10.32 and 16.52, respectively.Because of reducing the self-inductance in the interleaved struc-ture, the quality factor for the proposed transformer decreases to

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F × 1:2d conne

9tciw

s

TT

ig. 2. (a) Schematic diagram of 2 × 1:2 transformer. (b) Physical layout of typical 2imensional top view of the proposed transformer. (e) Two primary windings that

.97 and 15.64 for the primary and secondary windings, respec-ively. The purpose of this method is increasing the couplingoefficient. As we can see in Table 1, the coupling coefficient is

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ncreased from 0.63 to 0.73 by using the interleaved structurehich means it is suitable for transferring current.

The mutual inductance has no sensible change because theelf-inductances are reduced and the coupling coefficient is

able 1he interleaved and typical transformer specifications at 2.4 GHz operating frequency.

Transformer 2 × 1:2 Typical

Winding Secondary

Self-inductance (L1, L2) 4.79 nH

Parasitic resistance (R) 4.37 �

Quality factor (Q) 16.52

Turn ratio (N2/N1) 1.58

Mutual inductance (Lm) 1.90 nH

Coupling coeff. (K) 0.63

Efficiency (%) 81.4

Area 0.78 mm × 0.80 mm

Technology 0.18 �m

transformer. (c) Top view of proposed 2 × 1:2 interleaved transformer. (d) Three-ct the drain of power stage transistors. One secondary winding is also shown.

increased at the same time. Also, the turn ratio is nearlythe same for two designed transformers and the actual turnratio value from primary and secondary windings is defined

lly integrated 2.4 GHz CMOS high power amplifier using par-for WiMAX application. Int J Electron Commun (AEÜ) (2013),

as [5]

N2

N1=

√L2

L1(5)

Interleaved

Primary Secondary Primary

1.90 nH 4.13 nH 1.58 nH2.78 � 3.94 � 2.39 �10.32 15.64 9.97

1.611.86 nH

0.7384.2

0.78 mm × 0.80 mm0.18 �m

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-30

-20

-10

0

10

Tra

nsm

issio

n C

oeffic

ient [d

B]

0 1 2 3 4 5

-10

0

10

20

30

Frequency(GHz)

Ph

ase

Err

or

(De

gre

es)

S31

S32

PhaseError(|S13-S23|)

Ft

wadpttitatt

�

M1C1

L1

V_bias

Rb

Mn

V_bias

Rb

Vdd

calculated to be 87.4%. Moreover, the transformer efficiency with

ig. 3. Simulated transmission coefficients and phase error for 2 × 1:2 interleavedransformer.

here N1 and N2 denote the number of turns at the primarynd secondary windings. One of the most important points inesigning transformer power combiner is that lengths of tworimary windings from input to output must be equal in ordero avoid phase difference. Frequency responses for the proposedransformer when it is driven by a differential input are illustratedn Fig. 3. As shown in Fig. 3, two primary windings have very lit-le difference in the transmission coefficient magnitude (S31, S32),nd the phase error of two primary windings |S13–S32| is closeo zero and it is below 0.01. One of parameters that is defined for

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ransformer is transformer efficiency that can be expressed as:

PCT = PLoad

PIn-total(6)

Fig. 5. Proposed high power am

Vin

Fig. 4. A stacked power amplifier.

where PLoad is the transferred power at the load and PIn-total is thesum of power on all primary windings.

The efficiency for the proposed transformer by using a formulain [10] that considers ideal K and high M for the transformer is

lly integrated 2.4 GHz CMOS high power amplifier using par-for WiMAX application. Int J Electron Commun (AEÜ) (2013),

non-ideal K and M is defined by [9]

�PCT = RL

M × Re(A((R1 + jω(1 − k)L1A) + (X/n))∗)(7)

plifier circuit schematic.

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X

A

warte2ctp

3

icsSvtTiosVpiewrotcfius

idahtp

e2ti

Fig. 6. (a) Circuit model of balun and (b) layout of balun.

= jω(1 − k)

ML2 + R2 + RL (8)

= n

M+ X

jωL1n (9)

here M is the number of input primary winding and R1 and R2re parasitic resistors for the primary and secondary windings,espectively. The parameter n is the real turn ratio and parame-ers X and A are calculated by Eqs. (8) and (9). The real transformerfficiency for the interleaved transformer is 84.2% by (7) at the.4 GHz operating frequency. As we can see from Table 1, the effi-iency for the typical transformer is less than that of the interleavedransformer. The interleaved transformer has higher K and lowerarasitic impedance compared to typical transformer.

. Proposed high power amplifier

Generally, there are two methods for increasing output powern RF power amplifiers: (1) stacking of transistors and (2) powerombiners. The first approach proposes stacking of transistors forolving the problem of low breakdown voltage in submicron CMOS.tacking of three or four transistors in order to share the stressoltage among transistors and increase the power supply magni-ude for getting more output power has been proposed in [28,29].he schematic diagram of the stacked power amplifier is depictedn Fig. 4. The concept of this approach is explained as: if N stagesf power amplifier which every stage has one transistor and powerupply Vdd connect together as stacking, the value of power supplydd for stacked power amplifier can be n times of power sup-ly of every power amplifier stage. This method is appropriate for

ncreasing the output power but as seen in [28] the power addedfficiency of power amplifier becomes very low. There are otherays for decreasing the stress voltage upon the transistors which

esults in a higher output power by increasing power supply. Onef these methods is self-biased where it reduces swing voltage overhe cascode transistor and divides the stress equality between theommon source and common drain in the cascode power ampli-er. This approach has been proposed in [30] and it has been widelysed in designing linear power amplifiers. The negative point of theelf-biased method is reduction in gain of power amplifier.

The whole schematic diagram of the proposed power amplifiers illustrated in Fig. 5. The proposed PA consists of the input balun,river stage, interstage impedance matching network, power stagend PCT. All blocks of this PA, except the input and output ports,ave differential operation in order to increase the voltage swingo twice more; so a higher output power is achieved with the sameower supply.

The balun in Fig. 5, which is named T1 converts the single-

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nded signal to the differential signal. The ratio of conversion is:4 and then, it has no gain or attenuation. For implementation ofhe balun we used the interleaving method described in [27]. Fig. 6llustrates the layout and circuit schematic of the balun. The metal

Fig. 7. Simulated gm for class A, class B and parallel class A&B power amplifier.

width is 9 �m and the spacing between metals is 1.5 �m. The cou-pling coefficient K for this balun at 2.4 GHz frequency is calculatedto be 0.9.

A double stage is used for providing enough gain and becauseof avoiding high stress voltages over CMOS transistors which areprone to breakdown under high voltages, the driver and powerstages are designed in the cascode topology.

Also, the driver stage is biased in class A for increasing over-all linearity of PA. Impedance matching networks are placedbetween the driver and power stages such that they maximize thetransferred power from the driver to the power amplifiers. Thecomponents for this network are C3, L3, and C4 for the upper PAand C5, L4, and C6 for the lower PA. In this design of power ampli-fier, two amplifiers are used and their output current is added usinga 2 × 1:2 transformer. It is noticeable that the upper PA is similar tothe lower PA.

For linearity improvement of power amplifiers, many lineariza-tion techniques such as feed forward, feedback and predistortionhave been proposed. But, many of these techniques do not havethe capability of integration in integrated circuits. Many methodsfor linearization of power amplifiers have been proposed in CMOStechnology [31–33]. One of these methods presented in [32] canimprove the nonlinearity of gate-source capacitor for NMOS classAB power amplifier. The nonlinearity has been compensated byusing the PMOS transistor alongside the NMOS. However, this tech-nique reduces the gain of power amplifier because many parasiticcapacitors are laid at the input of power amplifier.

The nonlinear transconductance (gm) of the CMOS transistor isone of the reasons for nonlinear PAs. For this reason, the input ofpower stages is divided into two distinct parts: class A and classB power amplifiers [34]. Using parallel class A&B power amplifiercan improve the dynamic range and PAE [35].

Fig. 7 shows simulated gm for class A, class B and parallel classA&B power amplifiers versus input voltage. As seen from Fig. 7,gm of class A has a compressive nonlinearity and it is reduced withincreasing the input voltage. In contrast with class A, the gm of classB at low input voltages is increased and has expansive characteristicas depicted in Fig. 7. If we parallelize the class A and class B poweramplifiers, the gm of the parallel class A&B power amplifier will belinear in a wide range as seen in Fig. 7. The parallel class A&B poweramplifier combines the transconductance of the class A and class Bpower amplifiers at low input level as follows:

lly integrated 2.4 GHz CMOS high power amplifier using par-for WiMAX application. Int J Electron Commun (AEÜ) (2013),

gmA&B = gmA + gmB (10)

Combining the class A and class B power amplifiers can improvethe linearity of the transconductance and therefore increase P1dB

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F

opta0assAwbPpeptccAccloocib

at

Ft

10

20

30

40

Input Power (dBm)

Pout (d

Bm

), G

ain

(dB

)

-30 -25 -20 -15 -10 -5 00

10

20

30

40

PA

E(%

)

Pout

Gain

PAE

0

Fig. 10. PAE, gain and output power versus input power.

Table 2Width values for the power stage transistors.

Transistor M5 M6 M7 M8 M9 M10 M11 M12

Width (�m) 450 450 900 900 2000 2000 2000 2000

those obtained cause lower PAE and lower output power. With this

ig. 8. PAE and the output power versus the input power for different width ratios.

f the power amplifier. When the input signal is low, the class Aower amplifier produces most of the output power, and whenhe input signal increases, the class B power amplifier is the mainmplifier for producing the output power. In each stage, the stacked.35 �m thick-oxide transistors for the common-gate (CG) stages,nd the 0.18 �m thin-oxide transistors for the common-source (CS)tages are used. The transistors M9, M10, M11 and M12 that arehown with a thick gate in Fig. 5, are those with a thick-oxide gate.s we see in Fig. 8, four simulation results with different ratios ofidth for transistors in the class A and B power amplifiers have

een illustrated. As the first case, if the transistors of the class BA have a width twice more that of those in the class A PA theower amplifier will have maximum PAE and output power. In thequal width case (second case), the PAE is reduced and the outputower does not have any difference with the previous state becausehe class A is drawing a lot of current from the power supply, andompressive property of transconductance of the class A. When thelass B transistors widths are three or four times of those in the class

(third and fourth case), PAE in these cases are higher than secondase and it is lower than the first case and output power is reducedompared to first and second cases. In these two last state, PA hasower efficiency and output power compared with first state. Theptimum value for the transistors widths in the class B and class Af this power amplifier is the ratio of two. As shown in Fig. 9, forhoosing an optimum width, the output power and PAE versus thenput power in three different widths with the ratio of two have

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een swept.The best value for the class B and class A widths are WA = 450 �m,

nd WB = 900 �m. As we predict, increasing the width more thanhose obtained values not only decrease the PAE but also the

ig. 9. PAE and the output power versus the input power for several widths withhe ratio of two.

Fig. 11. Intermodulation distortion in a two-tone test with 1 MHz spacing.

output power cannot increase. Additionally, the widths less than

lly integrated 2.4 GHz CMOS high power amplifier using par-for WiMAX application. Int J Electron Commun (AEÜ) (2013),

selection of the width ratio of the class B to class A, the class B cancompensate the nonlinearity of class A. Width values for the classB and class A power amplifiers are shown in Table 2.

Fig. 12. Harmonic distortion for proposed PA.

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Fig. 13. (a) Spectrum of the proposed power amplifier with WiMAX (802.16e) signal. (b) Constellation diagram of proposed power amplifier at 25 dBm average output power.

Table 3Proposed PA simulation-based specifications and comparison with several integrated CMOS power amplifiers.

Reference CMOS tech. (nm) Frequency (GHz) VDD (V) PoutSat (dBm) P1dB (dBm) PAE@Psat (%) PAE@P1dB (%) PA class Gain (dB) Application

This work 180 2.4 3.3 32.5 32.3 37.9 36 A/B 32.4 WiMAX[9] 180 2.4 3.3 31 28 34.8 27 AB 37.5 WiMAX[10] 180 1.8 3.3 31.2 27 41 – E – –[15] 90 2.4 3.3 30.1 27.7 33 26 AB 28 WiMAX

28

–

–

pppo

aatwrCisitttCis

4

ipoppsw1at

[18] 180 2.5 3.3 31

[19] 180 1.8 3.3 30.2

[28] 65 6.5 4.6 29.6

The above mentioned width selection cause that the class Aower amplifier produces most output power when the inputower is less than −5 dBm and after that because of compressiveroperty of class A, the class B power amplifier is the main producerf the output power.

Transistors M7 and M8 are biased in class B and transistors M5nd M6 are biased in class A. The only difference between class And class B is transistor widths and their bias voltage. The induc-ors connected to the common-gate transistors are of the bondingire type. Remaining of the inductors are implemented as spi-

al inductors, and the capacitors are MIM cap with the standardMOS 0.18 �m RF process. The power combiner transformer was

ntroduced in Section 2. The resistors Rp1 and Rp2 are the para-itic resistors for the primary winding of the transformer, and Rp3s the parasitic resistor of the secondary winding. For optimiza-ion of the primary and secondary windings of the transformer andhe resonance with the effective inductance, which is seen from theransformer, the input capacitors C15, C16 and the output capacitorout are placed in parallel with the primary and secondary wind-

ngs. The proposed power amplifier is simulated in ADS using thetandard 0.18 �m CMOS process.

. Simulation results

Fig. 10 shows the PAE, gain, and the output power versus thenput power at the 2.4 GHz operating frequency. With the 3.3 Vower supply, the proposed PA provides a maximum output powerf 32.5 dBm, and a PAE of 37.9% is achieved at the maximum outputower. This PA exhibits a gain of 32.4 dB, and at 1 dB compressionoint (P1dB) its output power is 32.2 dB. For the two-tone test, twoinusoids around 2.4 GHz frequency with a certain offset frequency

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ere injected into the PA. The output spectrum for tone-spacing of MHz is shown in Fig. 11.As seen in Fig. 11, the IM3 at 25 dBm aver-ge output power is better than −31 dBc. Moreover, it is noticeablehat there is balance between upper and lower distortion products.

34.8 28 AB 31.3 WiMAX36.8 – E – –20.3 – E/F 11.6 –

Also, a harmonic test is done for the proposed PA with applyingone tone at the 2.4 GHz operating frequency. The output spectrumof PA is shown in Fig. 12 and as seen, the third harmonic of PA isless than 0 dBm at 7.2 GHz frequency, and the second and forth har-monics of PA are less than −20 dBm. This PA has been tested withWiMAX OFDM (802.16e) signal of 10 MHz bandwidth, and deliv-ers an output power of 25 dBm. The output spectrums with therequired mask for WiMAX standard are shown in Fig. 13(a).

At 25 dBm output power, the constellation diagram of the pro-posed power amplifier driven with the 16 QAM WiMAX signal isshown in Fig. 13(b). The error vector magnitude (EVM) at 25 dBmoutput power is −31 dB which satisfies the EVM requirement ofWiMAX application. As shown in Fig. 13(a), the measured spec-trum is totally under the WiMAX mask. The specifications of newdesigned PA and those of other several PAs are shown in Table 3.The results of proposed PA is just simulation with real componentof 0.18 �m CMOS technology. As we can see, our PA provides a con-siderable output power for the load, and because of using parallelclass A&B, it has a noticeable P1dB compared to the other PAs.

5. Conclusion

In this paper, we have proposed an integrated high power ampli-fier in standard 0.18 �m CMOS process; the PA was designed andextensively simulated for different specifications. Indeed, a modi-fied parallel class A&B power amplifier is proposed for increasingthe efficiency and linearity. As shown, this topology can increase thedynamic range. For designing power stage and obtaining high out-put power, two similar PAs have been used. The output of these twopower amplifiers is connected together by proposed interleavedpower combining transformer. The interleaved power-combiningtransformer causes increasing coupling factor in comparison with

lly integrated 2.4 GHz CMOS high power amplifier using par-for WiMAX application. Int J Electron Commun (AEÜ) (2013),

a typical transformer. The values of widths for the class A and Bpower amplifiers after several simulations are chosen 450 �m and900 �m, respectively. The proposed power amplifier exhibits sat-urated output power as high as 32.5 dBm and PAE of 37.9% at the

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aximum output power with 3.3 V power supply. Also, a high out-ut power of 32.2 dBm is achieved at 1-dB compression point. Weave tested our designed PA using an OFDM WiMAX signal andave shown EVM of −31 dB at 25 dBm average output power.

cknowledgements

The authors wish to acknowledge the financial support of Uni-ersity of Tehran, and Iran Telecommunication Research CenterITRC) for this research.

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Ahmad Rahati Belabad was born in Tehran, Iran, in1987. He received the M.Sc. degree in electrical engineer-ing from University of Tehran, Tehran, Iran, in 2012. Hisresearch interests include radio-frequency integrated cir-cuit design, CMOS power amplifiers design and analysisand modeling of on-chip transformers and spiral induc-tors. He is currently working as a researcher and designerat a RF circuits and system and advanced VLSI Lab at Uni-versity of Tehran.

Nasser Masoumi (S’90–M’96) received the B.Sc. and M.Sc.degrees from University of Tehran, Tehran, Iran, in 1988and 1990, respectively, both in electrical and computerengineering, and the Ph.D. degree in electrical and com-puter engineering from University of Waterloo, Waterloo,ON, Canada, in 2001. Dr. Masoumi joined the Schoolof Electrical and Computer Engineering, University ofTehran, in 1991. He is currently an Associate Professor,the head of Department of Electronics, and founder ofAdvanced VLSI and RFIC Laboratories, in the University ofTehran. He also has been President of Science and Technol-ogy Park of University of Tehran from 2005 to 2006. Themain topics of his research has focused on: interconnects,

nano-wires, carbon nanotubes (CNTs), VDSM and nano VLSI circuits and systemsdesign, CAD for VLSI, power management in VLIS, on-chip crosstalk, signal integrityand reliability issues. His research interests also include substrate coupling, mod-eling and synthesis of RF/microwave spiral inductors, RF wireless communicationstransceiver and power amplifier design, mixed-signal IC design, CMOS high perfor-mance and low-power analog and digital design. Dr. Masoumi has been the head ofDepartment of Electronics in School of ECE, College of Eng., University of Tehran since2009. He is a member of several internationally recognized scientific and industrialorganizations and journals. He has also served as a scientific committee member formany conferences and symposiums.

Shahin J. Ashtiani received the B.Sc. (Hons.) and M.A.Sc(Hons.) degrees from the University Of Tehran, Iran in1998 and 2001, respectively in electronics engineering.He received the PhD degree from University of Waterloo,Waterloo, Ontario, Canada in 2007. His PhD project wason driver circuits for active-matrix organic light-emittingdiode (AMOLED) displays. From 2001 to 2003 he was withValence Semiconductor Inc. as an analog design engineer,

lly integrated 2.4 GHz CMOS high power amplifier using par-for WiMAX application. Int J Electron Commun (AEÜ) (2013),

working on low-power, high-speed analog-to-digital con-verters. Since 2008, his is an assistant professor at theschool of electrical and computer engineering, Universityof Tehran, Iran. His current research interests are biomed-ical instrumentation and low-power data converters.