1726IEICE TRANS. ELECTRON., VOL.E88–C, NO.8 AUGUST 2005

PAPER Special Section on Papers Selected from AP-ASIC 2004

A Fully Integrated 1.7–3.125 Gbps Clock and Data RecoveryCircuit Using a Gated Frequency Detector

Rong-Jyi YANG†, Nonmember and Shen-Iuan LIU†a), Member

SUMMARY A fully integrated clock and data recovery circuit with theproposed gated frequency detector (GFD) is presented. It has been realizedin a standard 0.25-µm CMOS technology. The proposed voltage-controlledoscillator (VCO) can achieve wide operation range and reasonable conver-sion gain by employing the analog/digital dual loop architecture. The char-acteristics of small VCO gain can help to reduce loop bandwidth withoutenlarge the capacitors and relax the constraint on choosing the loop pa-rameter to reduce the size of the on-chip capacitor. The proposed GFDwill make the frequency lock time fixed and can avoid the harmonic lock-ing problem in digital domain for wide data rate operations. All measuredBERs are less than 10−12 with the data rate from 1.7 Gbps to 3.125 Gbps.key words: DLL, CDR, dual loop

1. Introduction

The requirements for faster information exchanging haveled to the demand for high speed data communications. Var-ious researches focus on high speed transceivers, especiallyfor the clock and data recovery (CDR) circuits [1]–[6]. For aconventional charge-pump CDR with the loop filter of RP inseries of CP, the natural frequency, ωn, and the damping ra-tio, ζ, of the closed loop transfer function can be representedas [7]

ωn =

√IPDT KVCO

2πCPand (1)

ζ =RP

2

√IPDT CPKVCO

2π, (2)

where IP is charge pump current, DT is input data transitiondensity and KVCO is gain of the voltage-controlled oscillator(VCO). Usually, the tuning range of a VCO should be largeenough to overcome the process, voltage and temperaturevariations, i.e., KVCO will be large. A large CP might beneeded to reduce loop bandwidth for jitter suppression. AsCP is large enough, the −3 dB bandwidth of the loop can beexpressed as [7]

ω−3 dB �RPIPDT KVCO

2π. (3)

The ways to reduce loop bandwidth are to decrease IP andRP for a fixed KVCO. The smaller IP will induce the se-rious mismatch between charging and discharging current.

Manuscript received November 3, 2004.Manuscript revised February 15, 2005.†The authors are with the Graduate Institute of Electronics En-

gineering and Department of Electrical Engineering, National Tai-wan University, Taipei, Taiwan, 10617, R.O.C.

a) E-mail: lsi@cc.ee.ntu.edu.twDOI: 10.1093/ietele/e88–c.8.1726

Reducing loop bandwidth by RP has to further increase CP

to maintain the same damping ratio. Moreover, for a fixed−3 dB bandwidth, if KVCO is reduced by a factor of k, RP

can be increased by the same factor. And the damping ra-tio can be increased by a factor of

√k. The jitter tolerance

can be also improved [7]. If CP is also reduced by a factorof k, the natural frequency and damping ratio will remainthe same. The required die area for the on-chip loop filtercould be reduced and is easier to be integrated. In orderto enlarge the tuning range and reduce the KVCO, an ana-log/digital dual-controlled VCO (DVCO) with 56% tuningrange and reasonable KVCO is proposed.

Owing to the small lock range of the phase detectors(PDs), an accessory frequency tracing loop is needed forwide tuning range VCOs in CDR circuits. Since the wholefrequency range of the proposed DVCO is divided into sev-eral bands, a frequency detector in digital domain would benecessary. Quadricorrelators [8]–[10] are widely used forfrequency acquisition. The characteristics of narrow capturerange and the probabilistic nature [10] makes it impossibleto be used in this work. To avoid this predicament, a digitalgated frequency detector (GFD) is presented to acquire thewide range data without harmonic locking issue.

2. Circuit Description

The proposed fully integrated CDR circuit is shown inFig. 1. It consists of a digital GFD, an analog/digital DVCO,a linear half-rate phase detector [1] and a charge-pump (CP).To receive the data, the signal, Start, is set to low to clearthe GFD. When the signal Start changes to high, the GFDwould output 5-digit control code to select the proper fre-quency band of the DVCO according to the input data rate.After the digital loop is stopped, the analog loop would be

Fig. 1 Half-rate CDR architecture.

Copyright c© 2005 The Institute of Electronics, Information and Communication Engineers

YANG and LIU: A FULLY INTEGRATED 1.7–3.125 Gbps CLOCK AND DATA RECOVERY CIRCUIT1727

Fig. 2 The proposed GFD.

Fig. 3 Delay cell of DVCO and DCDL.

activated and the linear PD and CP would take over the restjob until the phase is correct.

The proposed GFD consists of two gated oscillators(GOs), a dual-controlled delay line (DCDL), a phase com-parator (PC), a 5-bit successive approximation register-controlled (SAR) [11] controller and a differential to single-ended (DTS) buffer, as shown in Fig. 2. The two GOswould be triggered by the first rising and falling edges ofthe preamble signal, respectively, and generate the signalsVGO1 and VGO2. The signal VD is generated by the DCDLfrom the signal VGO1. The PC will compare the phase rela-tion between the signals VD and VGO2 and output the signalLead/Lag for the 5-bit SAR controller to adjust the DCDL.And the clock signal which triggers the SAR controller isgenerated by the signal VGO2 through the DTS buffer. Af-ter the 5-bit binary searching is finished, the controller willoutput the signal PowerDown to turn off the GOs and theDCDL to reduce the power consumption. The delay cells inthe DCDL, as shown in Fig. 3, are identical to those in theDVCO. The only difference between them is that the signal,PowerDown, of the delay cells in the DVCO is connected topower supply while that in the DCDL is controlled by the5-bit SAR controller.

In order to operate correctly, the preamble signal isneeded as shown in Fig. 4. Suppose that the first two dataare “10,” i.e., logic one followed with a logic zero and theremaining preamble signal can be random data or periodicdata of 1010. . . Assume these two GOs are identical; theywill oscillate at the same frequency and keep a constantphase difference. Since the time difference between the firstrising and falling edges of the preamble is equal to a bittime, the phase difference between VGO1 and VGO2 would bethe same. If VD is aligned with VGO2, the delay time of theDCDL would be close to a bit time. In other words, if these

Fig. 4 Timing diagram of digital GFD.

delay cells are connected as a ring oscillator, it will oscillateclose to half data rate.

While the most significant bit is switched from low tohigh in binary searching, the maximum change of delay timein a DCDL would be a half of tuning range. Such a rapidchange might result in the harmonic locking problem forthe GFD. The oscillating frequency of the two GOs shouldbe chosen carefully to prevent the issue. Considering thetiming relation for a certain data rate as shown in Fig. 4, thedelay time, TD, of the DCDL has to satisfy the followingconstraint:

Tbit − TGO

2≤ TD ≤ Tbit +

TGO

2, (4)

where Tbit is the bit time of data and TGO is the oscillatingperiod of the two GOs. This constraint has to be satisfied forall data rates in wide range applications. Equation (4) couldbe rewritten as

Tbit,max − TGO

2≤ TD,min and (5)

TD,max ≤ Tbit,min +TGO

2, (6)

where Tbit,max and Tbit,min represent the maximum and min-imum bit time, respectively. Ideally, TGO should be greaterthan twice of the delay range and the constraint of Eq. (6)would be vanished for any value of Tbit. For example, ifthe data rate from 1.7 Gbps to 3.125 Gbps for a CDR circuitis desired, TD should cover the range from 320 ps to 588 psand TGO has to greater than 536 ps. One can simply chooseTGO to be larger than 2 × Tbit,max, i.e. 1.17 ns. The detectionrange could be enlarged by increasing TGO. In this paper,TGO is set to 2 ns to ensure that GFD have adequate opera-tion range.

The frequency resolution of the GFD is determined bythe variable delay time, TLS B, corresponding to the least sig-nificant bit (LSB) in the DCDL. Because the binary searchalgorithm could only guarantee that the steady-state error isless than ±1 LSB, The value of TLS B should be designedsmall enough and could not exceed the capture range of PD.The maximum frequency error, ∆ f , of the GFD could beexpressed as

∆ f =1

2(Tbit − TLS B)− 1

2Tbit�

TLS B

2T 2bit

. (7)

1728IEICE TRANS. ELECTRON., VOL.E88–C, NO.8 AUGUST 2005

Fig. 5 Phase detector with MUX in [1].

Fig. 6 Current mode XOR gates [1] with modified charge pump.

If TLS B is 30 ps, the maximum frequency error would be43 MHz for the data rate of 1.7 Gbps and the analog tuningrange of the DVCO has to cover that. The accuracy of theGFD could be improved by reducing TLS B. But the num-ber of bit of the digital loop should be increased to maintainthe same tuning range and the digital lock time would belonger. In wide data-rate applications, the frequency accu-racy would be better in low data-rate cases.

A linear half-rate PD [1] is employed in this work asshown in Fig. 5. Conventional static and dynamic logicscannot perform phase detection for such a high speed. Toextract high speed phase information, all logic componentsin Fig. 5 are implemented in current mode logic (CML) [12].The current mode XOR gates [1] with the modified chargepump are implemented as shown in Fig. 6 to achieve highspeed operation. The symmetry configuration could reducethe loading mismatch of phase detector.

3. Experimental Results

The proposed CDR has been fabricated in a standard 0.25-µm CMOS technology and occupies a chip area of 1.5 ×1.8 mm2 including the on-chip loop filter. Figure 7 showsthe die photograph. This CDR consumes 200 mW from asingle 2.5 V supply at the data rate of 3.125 Gbps. To makesure that the proposed GFD catches the correct period ofone data bit, the differential input data is set to logic zerowhile the signal start is switched from low to high by theoff-chip manual control. After the signal start is enabled,the data pattern is changed from the fixed logic zero to the

Fig. 7 Die photo of the proposed CDR.

Fig. 8 Measured transient response for the GFD at the data rate of2.5 Gbps.

pre-programmed 27 − 1 PRBS pattern. The first two bitsof the chosen data pattern are a logic one followed with alogic zero. The pattern of other bits will not affect the op-eration of GFD. Figure 8 illustrates the measured transientresponse for the GFD at the data rate of 2.5 Gbps. The oper-ating frequency of the digital GFD is 500 MHz. The signal,PowerDown, of the GFD will switch from logic one to logiczero and thus turn off the GOs and the DCDL after 5 cyclesof the GO.

Figures 9(a) and 9(b) illustrate the retimed data andclock when the CDR locks to 1.7 Gbps and 3.125 Gbps NRZdata with a PRBS of 27 − 1, respectively. To reduce therequired bonding pads for the measurement consideration,the differential retimed clock and data are transformed intosingle-ended by differential-to-single-ended buffers. Thesebuffers degrade the CMRR and PSRR performance and con-tribute noise and jitter. Further, the rail-to-rail input sig-nals for the open-drain buffers will cause large ripples whenthe output signals are at the maximum or minimum volt-age. The measured jitter histograms are shown in Fig. 10.The measured rms and peak-to-peak jitters from 1.7 Gbps to

YANG and LIU: A FULLY INTEGRATED 1.7–3.125 Gbps CLOCK AND DATA RECOVERY CIRCUIT1729

(a) (b)

Fig. 9 Retimed data and clock at the data rate of (a) 1.7 Gbps (b)3.125 Gbps.

3.125 Gbps are below 7.4 ps and 62.2 ps, respectively. Fig-ure 11 illustrates the measured result of jitter transfer func-tion at the data rate of 2.5 Gbps. The measured loop band-width is around 1 MHz without large off-chip capacitors andthe measured jitter transfer functions for all data rates are al-most the same. This is because the KVCO is small and nearlyconstant under different digital control codes. The bit-error-rate (BER) testing time was set to be 20 minutes and no er-ror occurred. The measured BERs are all smaller than 10−12

when the data rate is from 1.7 Gbps to 3.125 Gbps of 27 − 1PRBS. The maximum length of consecutive 1’s or 0’s is 15when the BER is lower than 10−12. Table 1 gives the perfor-mance summary of this work.

4. Conclusions

A 1.7–3.125 Gbps CDR circuit is realized in a 0.25-µm stan-dard CMOS technology including the passive on-chip loopfilter. The DVCO incorporating with the proposed widerange GFD can achieve both small KVCO and wide opera-tion range without harmonic locking issue. This dual looparchitecture could reduce the KVCO and provide another wayto decrease the loop bandwidth. It can relax the loop param-eter and further reduces the area of on-chip capacitor. Thelarge off-chip capacitors are not required in this design andmake it suitable for system-on-a-chip (SoC) design. TheGFD has a fixed lock time and is independent of data pat-

(a)

(b)

Fig. 10 Measured jitter histograms at the data rate of (a) 1.7 Gbps and(b) 3.125 Gbps.

Fig. 11 Measured jitter transfer at the data rate of 2.5 Gbps.

tern. All the measured BERs are less than 10−12 at the datarate from 1.7 Gbps to 3.125 Gbps.

Acknowledgement

The authors would like to thank Chip Implementation Cen-

1730IEICE TRANS. ELECTRON., VOL.E88–C, NO.8 AUGUST 2005

Table 1 Performance summary.

ter (CIC), Taiwan, for fabricating this chip. This work wassupported in part by MediaTek Inc.

References

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Rong-Jyi Yang was born in Taipei, Tai-wan, R.O.C., in 1973. He received the B.S.degree in electrical engineering from NationalCentral University, Jhongli, Taiwan, R.O.C., in1998. He is currently working toward the Ph.D.degree in electronics engineering, National Tai-wan University, Taipei, Taiwan, R.O.C. Hisresearch interests include phase-locked loops,delay-locked loops, and high-speed CMOS datarecovery circuits for multiple gigabit communi-cation.

Shen-Iuan Liu was born in Keelung, Tai-wan, Republic of China, 1965. He received boththe B.S. and Ph.D. degree in electrical engineer-ing from National Taiwan University (NTU),Taipei, in 1987 and 1991, respectively. Dur-ing 1991–1993 he served as a second lieutenantin Chinese Air Force. During 1991–1994, hewas an Associate Professor in the Department ofElectronic Engineering of National Taiwan In-stitute of Technology. He joined in the Depart-ment of Electrical Engineering, NTU, Taipei,

Taiwan in 1994 and he has been the Professor since 1998. He obtained theEngineering Paper Award from the Chinese Institute of Engineers, 2003.He obtained the Young Professor Teaching Award from MXIC Inc., theResearch Achievement Award from NTU, and the Outstanding ResearchAward from National Science Council, 2004. His research interests are inanalog and digital integrated circuits and systems. Dr. Liu has served achair on IEEE SSCS Taipei Chapter from 2004. He has served a generalchair on the 15th VLSI Design/CAD symposium, Taiwan, 2004 and a Pro-gram Co-chair on the Fourth IEEE Asia-Pacific Conference on AdvancedSystem Integrated Circuits, Japan, 2004. He is a senior member of IEEE.