IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 11, NOVEMBER 2010 863

A Family of Low-Voltage Bulk-Driven CMOSContinuous-Time CMFB Circuits

Juan M. Carrillo, Guido Torelli, Senior Member, IEEE, Miguel A. Domínguez, Raquel Pérez-Aloe,José M. Valverde, and J. Francisco Duque-Carrillo

Abstract—This brief introduces four different structures for im-plementing a continuous-time common-mode feedback (CMFB)network for fully differential (FD) amplifiers. The proposed cir-cuits use bulk-driven MOS transistors, thus representing a low-voltage realization of their gate-driven counterparts. The CMFBcircuits were included in a 1.5-V FD buffer implemented instandard 0.35-µm CMOS technology. Experimental results il-lustrate the performance of the proposed schemes, demonstratingtheir suitability to operate with a low supply voltage.

Index Terms—Bulk-driven MOS transistors, CMOS analog in-tegrated circuits, common-mode feedback (CMFB), fully differen-tial amplifiers, low-voltage.

I. INTRODUCTION

THE OVERALL performance of analog and mixed-modesystems may be improved by adopting a fully differential

(FD) implementation. The use of this approach entails severalwell-known advantages, such as the extension of the dynamicrange, the ideal cancellation of even-order harmonics, and thereduction of the effects of undesired noises coming from thesupplies, which may be considered as common-mode (CM)signals [1]. Nevertheless, there are also disadvantages associ-ated to the use of FD circuits. The duplication of most partsof the circuit leads to area and power consumption increase.Moreover, an additional network, referred to as CM feedback(CMFB) circuit, must be used to control the CM component ofthe output signal [1]–[4]. Some approaches have been reportedin order to avoid the need for a CMFB loop in FD circuits[5]–[7]. However, all the proposed techniques have their ownbenefits and drawbacks.

The conventional block diagram of a FD amplifier includinga CMFB loop is shown in Fig. 1. The amplifier output voltages,V +

out and V −out, are fed to a CM detector. This block provides a

signal, Vs, which monotonously tracks the amplifier output CMvoltage Vout,CM = (V +

out + V −out)/2. This signal is compared to

a reference voltage, Vref , by means of an error amplifier whose

Manuscript received March 30, 2010; revised June 15, 2010; acceptedJuly 28, 2010. Date of current version November 17, 2010. This work wassupported by the Junta de Extremadura R&D Plan under Grants 3PR05C008and PRI09A080. This paper was recommended by Associate Editor N. Neihart.

J. M. Carrillo, M. A. Domínguez, R. Pérez-Aloe, J. M. Valverde, andJ. F. Duque-Carrillo are with the Department of Electronics, University ofExtremadura, 06006 Badajoz, Spain (e-mail: jmcarcal@unex.es).

G. Torelli is with the Department of Electronics, University of Pavia, 27100Pavia, Italy (e-mail: guido.torelli@unipv.it).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSII.2010.2068090

Fig. 1. FD amplifier with feedback control of the output CM voltage.

output signal, Vcmfb, is injected back into the FD amplifier soas to close a negative feedback loop.

The CM loop must be able to operate with high accuracy atleast up to the highest frequency at which output balancing isdesired [1], [2]. Therefore, the CMFB circuit must be designedin such a way that CM and differential-mode (DM) loopsprovide similar accuracy and speed response, which entails

LGCM∼= LGDM (1a)

LGBWCM∼= LGBWDM (1b)

that is, the CM open-loop DC gain, LGCM, and gain-bandwidthproduct, LGBWCM, must be comparable to the correspondingparameters for the DM signal, i.e., LGDM and LGBWDM,respectively [1]. These requirements may be met by providingsimilar paths to the DM and CM components of the signal.

There is an additional drawback when the FD amplifieris required to operate in low-voltage conditions. In a systeminvolving different basic building blocks, the output DC voltageof each block should be set to a level compatible with theinput voltage range of the cascaded stage. Nevertheless, themost convenient level for the output CM voltage of the overallsystem is usually midsupply, as in this case the output signalswing is maximized. If the supply voltage is lower than 2|VGS|(VGS being the gate-to-source voltage of an MOS transistor inits active region), the DC level at midsupply is not sufficientto turn either a p- or an n-channel transistor on. In this case, aconventional CM detector based on gate-driven MOS devicescannot be directly driven by the amplifier output terminalsand passive voltage shifters or non-standard CMOS fabricationtechnologies should be used [8]. Besides, even when the supplyvoltage is above 2|VGS|, a conventional CM detector networkcould have difficulties to operate in worst-case conditionsand/or could show a very limited signal swing.

A possible solution to implement low-voltage continuous-time basic building blocks in standard CMOS technology is

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864 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 11, NOVEMBER 2010

Fig. 2. Conceptual implementation of a CM detector scheme based on twopassive resistors and two voltage buffers.

to use bulk-driven MOS transistors [9]–[12]. In this brief,this approach is followed to design four different continuous-time CM detectors able to operate over a wide voltage rangeunder low-voltage conditions. In Section II, conventional (gate-driven) continuous-time CMFB circuits and their limits arebriefly reviewed, and bulk-driven counterparts are proposed.These blocks were included in a low-voltage FD buffer asillustrated in Section III. An experimental comparison of theproposed CM detectors is provided in Section IV and, finally,conclusions are drawn in Section V.

II. BULK-DRIVEN CMFBS IN STANDARD

CMOS TECHNOLOGY

A key building block in the implementation of an FD am-plifier is the CM detector. This circuit must generate a voltage,Vs, that monotonously tracks the output CM voltage, Vout,CM,of the FD amplifier. If the value of Vs is linearly related toVout,CM, the linearity of the amplifier is further enhanced. Tothis end, different approaches have been reported in literature[1]–[4], [8], [13]–[15]. The simplest network for CM detec-tion is illustrated in the shadowed area of Fig. 2, assumingvoltages V +

out and V −out to be directly connected to Va and Vb,

respectively. The operation principle of this circuit is basedon generating voltage Vs with the help of two identical series-connected passive resistors, R. Ideally, the value of Vs is equalto the CM voltage of the applied signals, Vout,CM. Nevertheless,an important limitation of this scheme is the loading effectof resistors on the FD amplifier. A conventional solution toovercome this drawback is to use voltage buffers as illustratedin the overall circuit of Fig. 2. The unity gain amplifiers maybe easily implemented by means of source followers (SFs) [1].However, the drawback of using voltage buffers is the distortionintroduced by active devices. The linearity of the overall FDamplifier may be enhanced if the voltage buffers are imple-mented by using flipped voltage followers (FVFs) [13].

Another possibility to build a CM detector is to take advan-tage of the operation of a differential pair (DP) [1]. Indeed,when a differential pair works in its linear region, the voltageat the common source terminal of the input transistors followsthe CM component of the voltage signals applied to their inputterminals with (ideally) unity gain. The main drawback of thisapproach is the reduced input DM range of a CMOS differentialpair, which leads to substantial distortion amounts even whenthe applied differential signal is very small. Linearity maybe improved by connecting two pairs of the same polarity inparallel to implement a current-based (CB) solution [1], [14].In this case, one of the input terminals of both differential pairsis connected to reference voltage Vref and the outputs of theFD amplifier are connected to the other two input terminalsof the pairs. A signal current is generated and gives rise to

Fig. 3. Low-voltage bulk-driven CM detectors relying on (a) a differentialpair (DP), (b) a source follower (SF), (c) a flipped voltage follower (FVF), and(d) current-based operation (CB).

control voltage Vcmfb in the FD amplifier. Improved linearityis achieved thanks to the differential structure and operation ofthe CM detector.

The circuit techniques described above were previously im-plemented by using standard gate-driven transistors which im-poses a minimum supply voltage of 2(VGS + VDSat + Vsignal),where VDSat is the drain-to-source saturation voltage of anMOS transistor and Vsignal is the peak amplitude of theprocessed signal. The factor of two in the above expressionholds assuming that the output CM voltage is set to midsupply.

The supply requirements of a continuous-time CM detectormay be reduced if a bulk-driven approach [9]–[12] is followed,as in this case the minimum required supply voltage is onlyVGS + VDSat. Indeed, it is not necessary to spend a part ofthe voltage applied to the input terminals to turn the inputdevices on. The bulk-driven implementation of four differentCM detector circuits derived from the gate-driven schemesdepicted above, namely, solutions relying on a differentialpair (DP), a source follower (SF), a flipped voltage follower(FVF), and CB operation, is illustrated in Fig. 3. The operationprinciple of circuits DP [Fig. 3(a)], SF [Fig. 3(b)], and FVF[Fig. 3(c)] is similar to that of the corresponding gate-drivencounterpart, which has been explained above. In these cases,the block diagram shown in Fig. 1 for the FD amplifier is usedand voltage Vref can be generated with the help of a replicaof the main CM detector: this way, the two blocks are affectedby the same variations during fabrication and hence, errors in

CARRILLO et al.: FAMILY OF LOW-VOLTAGE BULK-DRIVEN CMOS CONTINUOUS-TIME CMFB CIRCUITS 865

Fig. 4. FDDA: (a) circuit schematic; (b) unity-gain non-inverting FD bufferconfiguration.

setting Vout,CM to the required value are reduced. Regardingthe approach in Fig. 3(d), a current Icmfb is generated by theCM detector and is then fed to the FD amplifier by means ofvoltage Vcmfb, thus closing the feedback loop with no need forany error amplifier.

The input-referred noise contribution of a bulk-driven MOStransistor is higher as compared to that of a gate-driven device[9], [11]. Nevertheless, as the CMFB circuit directly acts overthe output branches of the FD amplifier, the noise contributionof the bulk-driven transistors in the CMFB is divided by theoverall gain of the amplifier when its input-referred noise iscalculated. Thus, the noise contribution of the bulk-driven tran-sistors in the above CMFB networks is negligible as comparedto the noise contribution of the input transistors of the FDamplifier. Finally, it is worth to note that the maximum inputcurrent of bulk-driven MOS transistors when their parasitic pnsource-bulk junction is forward biased can be kept to a very lowlevel [16], as will be shown in Section IV.

III. LOW-VOLTAGE FD BUFFER

With the goal of comparing the performance of the fourCM detector networks introduced above, the FD differenceamplifier (FDDA) illustrated in Fig. 4(a) was designed [17].The amplifier was connected according to the configurationshown in Fig. 4(b), thus obtaining a FD voltage buffer. Theinput stage of the FDDA is based on bulk-driven input tran-sistors and drives an output stage biased in class A. The goalof using a bulk-driven input stage in the FDDA is to achieveinput rail-to-rail operation, so as to verify the operating voltagerange of the proposed bulk-driven CM detectors. The frequencyresponse of the two-stage scheme is compensated by means ofa conventional Miller network including a zero-nulling resistor.The FD amplifier outputs are capacitively loaded by the bulk-driven MOS transistors of the CM detector. However, thiscapacitance is connected in parallel with the load capacitor, CL,and, typically, its effect is almost negligible. The error amplifier

Fig. 5. Low-voltage error amplifier (Vb represents a suitable bias voltage).

Fig. 6. Chip microphotograph of the four FD buffers fabricated.

in Fig. 5 was included in the CMFB loop based on the DP, theSF, and the FVF solutions in order to set the output CM voltageto the desired value, Vref .

In order to accomplish (1), the paths for the DM and theCM signals should be as similar as possible. For the circuitsproposed, the DM signal path coincides exactly with the pathprovided by the FDDA in Fig. 4(a). On the other hand, the CMloop includes the CM detector (which is based on bulk-drivendevices) and the error amplifier (if any) along with the inputstage of the FDDA (driven by transistors MA7 and MA8) as aninput section and the class-A stage of the FDDA as an outputsection. Therefore, it is not difficult to achieve the conditionsin (1) as in each case, both the DM and the CM path includea bulk-driven stage cascaded by a gate-driven stage (the latterbeing the same for the two paths). When a gate-driven approachis followed for the input stage of the FD amplifier, the gain andthe frequency response of the bulk-driven CM detector may beenhanced by using appropriate circuit techniques [11] to satisfyrequirements in (1). Finally, it is worth to point out that the low-gain configuration chosen for the error amplifier in Fig. 5 makesit easier to compensate the frequency response of the CM loop,where the two high-gain stages indicated above are present.

IV. EXPERIMENTAL RESULTS

Four FD buffers, including the FDDA in Fig. 4(a), the CMdetector networks in Fig. 3 (DP, SF, FVF, and CB approach,respectively), and the error amplifier in Fig. 5 when required,were designed in standard 0.35-µm CMOS technology (nom-inal threshold voltage values equal to 0.5 V and −0.65 V forn-channel and p-channel devices, respectively) to operate with

866 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 11, NOVEMBER 2010

Fig. 7. Measured DC transfer characteristic of the four FD buffers: (a) single-ended (V +

out, V−out) and (b) fully differential (Vout,DM = V +

out − V −out)

outputs.

a 1.5-V supply voltage (VDD = −VSS = 0.75 V). A micropho-tograph of the chip is depicted in Fig. 6. The biasing currentsof the input and the output stage of the FDDA, IB and IBO,were set to 10 µA and 20 µA, respectively, while the value ofbiasing currents in the CM detectors and their respective replicacircuits, IB,CMFB, (when needed) was chosen equal to 10 µA.The quiescent values of currents IB,E1 and IB,E2 in the erroramplifier were set to 15 µA and 2.5 µA, respectively. Thereis no risk that current sources IB and IB,CMFB operate in thetriode region. Indeed, the connection of the gate terminal ofthe bulk-driven MOS transistors to VSS provides these currentsources with a large value of the drain-to-source voltage, VDS.This degree of freedom for VDS allows including cascode tran-sistors in the current sources when a demanding CM rejectionratio (CMRR) performance is required. The value of resistorsR, which were implemented with nonsilicided polysilicon, wasselected to be equal to 10 kΩ. The channel length of MOStransistors was set to 1 µm in order to minimize the effectof mismatches, except for the devices involved in the biasing

Fig. 8. Measured THD as a function of the input signal amplitude Vin,pp foran input frequency of (a) 1 kHz and (b) 10 kHz.

circuitry, for which a length equal to 2 µm was used for thesake of accuracy.

The simulated values of LGDM and LGBWDM, whichcorrespond to the DC gain and the gain-bandwidth product ofthe FDDA in Fig. 4(a), were 71 dB and 1.2 MHz, respectively.The simulated LGCM and LGBWCM were equal to 78 dBand 1.0 MHz for the FD buffer with the DP, the SF, and theFVF CM detector whereas, for the FD buffer based on theCB approach, the simulated LGCM and LGBWCM were equalto 80 dB and 1.3 MHz, respectively. The improvement in thefrequency response is due to the fact that, in the last solution,no error amplifier is involved in the CM path.

The experimental DC transfer characteristics of the FDbuffers with the four different CM detectors are illustrated inFig. 7. The individual responses (V +

out and V −out) of each CMFB

circuit, depicted in Fig. 7(a) as a function of the input voltage(V +

in and V −in ), are linearized when one of the two comple-

mentary output voltage signals is subtracted from the otherto obtain the differential output Vout,DM, which is illustratedin Fig. 7(b). The linearization is due to the cancellation ofeven-order harmonics. According to Fig. 7, the CB approachprovides the output response that is closest to the input signalfor a wider voltage range. It is worth noting that the worst-case

CARRILLO et al.: FAMILY OF LOW-VOLTAGE BULK-DRIVEN CMOS CONTINUOUS-TIME CMFB CIRCUITS 867

TABLE IEXPERIMENTAL PERFORMANCE COMPARISON OF FOUR FD BUFFERS

CONTAINING THE CM DETECTORS IN FIG. 3 (TECHNOLOGY: 0.35-µmCMOS, VDD = −VSS = 0.75 V, Vref = 0 V, CL = 10 pF)

DC input current arises for Vin,cm = VSS, where the measuredvalue of Ii for the four implementations ranges between 2 nAand 4 nA. This leads to a worst-case effective input resistance,Ri, between 7.4 MΩ and 17.0 MΩ.

In order to determine the linearity of the four schemesimplemented, the total harmonic distortion (THD) of the outputsignal of the FD buffers was measured. Fig. 8 illustrates theexperimental THD as a function of the input signal peak-to-peak amplitude for two different input frequencies, that is,1 kHz [Fig. 8(a)] and 10 kHz [Fig. 8(b)]. Approaches CBand FVF provide the best performance. Fig. 8 also shows thedistortion level introduced by the circuit used to convert asingle-ended input voltage into the FD signal that is fed to theFD buffer.

A summary of the experimental performance of the four FDbuffers is provided in Table I, where statistical data refer to mea-surements on 20 different samples of each circuit. The DC gain,Av, was measured for the FDDA in open-loop configuration,while the unity gain bandwidth, UGB, stands for the −3-dBbandwidth of the FDDA in the buffer configuration illustratedin Fig. 4(b). The CM offset voltage, Vos,CM, shows the accuracyof the CMFB circuit in setting Vout,CM to the desired referencevalue, whereas the DM offset voltage, Vos,DM, is a consequenceof mismatches between the two sides of the FD circuit. It maybe deduced from Figs. 7 and 8, as well as from Table I, that theCMFB approach CB represents the most linear solution, whilealso leading to the lowest power and area consumption, mainlydue to the fact that no additional error amplifier is required inthis case.

V. CONCLUSION

The use of bulk-driven MOS transistors is a suitable ap-proach to implement low-voltage continuous-time CMFB net-works. Bulk-driven standard MOS devices allow setting theCM component of the output voltage of a FD amplifier to

midsupply even for supply voltages as low as VGS + VDSat,which represents an important reduction in terms of minimumsupply voltage as compared to the case of a conventionalcontinuous-time CMFB circuit based on gate-driven devices.The operation of the proposed solution was validated by meansof measurements on four FD buffers using different bulk-driven CM detectors, which demonstrated their good linearityperformance and suitability to low-voltage operation.

ACKNOWLEDGMENT

The authors wish to thank the support of I. Brinquete infabricating the printed circuit boards used for test purposes.

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