Ms Vincy JosephAdvanced MicroprocessorTE CMPNA/B

80386DX

Features

It supports 8/16/32 bit data operands

It has 32-bit internal registers

It supports 32-bit data bus and 32-bit non-multiplexed address bus

It supports

Physical Address of 4GB

Virtual Address of 64TB

Maximum Segment size of 4GB

It operates in 3 different modes

Real

Protected

Virtual 8086

MMU provides virtual memory, paging and 4 levels of protection

Clock Frequency : 20,25 and 33MHz

It has 132 pin package

Architecture of 80386

UQ: Draw the block diagram of the 80386 DX Processor and explain each block in brief

The internal architecture of 80386 is divided into three sections:

1. Central Processing Unit

2. Memory Management Unit

3. Bus Interface unit

Central Processing Unit

The CPU is further divided into Instruction Unit and Execution Unit

Instruction Unit:

It decodes the opcode bytes received from the 16-byte instruction queue and arranges them into a 3-decoded instruction queue.

After decoding it is passed to control section for deriving necessary control signals

Execution Unit:

It has 8 general purpose and 8 special purpose registers which either handles data or addresses

The 64-bit barrel shifter increases the speed of all shift, rotate, multiply and divide operations

The multiply/divide logic implements the bit-shift-rotate algorithms to complete the operations in minimum time(Even 32bit multiplication is done in 1s)

Elements of Execution Unit

1. Arithmetic/logic unit (ALU): Performs the operation identified by ADD, SUB, AND, etc.

2. Flags register: Holds status and control information

3. General-purpose registers: Holds address or data information

4. Control ROM: Contains microcode sequences that define operations performed by machine instructions

5. Special multiply, shift, and barrel shift hardware: Accelerate multiply, divide, and rotate operations

Memory Management Unit

MMU consists of a segmentation unit and paging unit

Segmentation Unit:

It allows the use of two address components - segment and offset for relocability and sharing of data

It allows a maximum segment size of 4GB

It provides a 4-level protection mechanism for protecting and isolating systems code and data from those of application program

The limit and attribute PLA checks segment limits and attributes at segment level to avoid invalid accesses to code and data in memory segment.

Paging Unit

It organizes physical memory in terms of pages of 4KB size

It works under the control of segmentation unit

It converts linear addresses into physical addresses

The control and attribute PLA checks privileges at page level.

Bus Interface Unit

It has a prioritizer to resolve the priority of various bus requests. This controls the access of the bus

The address driver drives the bus enable and address signals A2 A31.

The pipeline/bus size unit handles the control signals for pipelining and dynamic bus sizing units

The data buffers interface the internal data bus with system bus

Signal Interface of 80386DX

Signals are arranged by functional groups.

The # symbol indicates active low signal.

When no # is present, the signal is active high.

Example: M/IO# - High voltage indicates memory selected

- Low voltage indicates I/O selected

Clock (CLK2):

It is divided by two internally to generate the internal processor clock.

The phase of internal processor clock can be synchronized to a known phase.

Data Bus (D0 through D31):

It has three-state bidirectional signals.

It can transfer data on 32- and 16-bit buses using a data bus sizing feature.

Address Bus (A2 through A31)

These three-state outputs provide memory or I/O port addresses.

It can access 4GB of physical memory from 00000000H to FFFFFFFFH

Of the total 32-bits, only higher 30 are released by MP

A1 & A0 are used internally by MP to produce 4 bank enable signals(BE3# - BE0#)

Byte Enable Outputs( BE0# -- BE3#)

enable 4 memory banks

indicates which bytes of the 32-bit data bus are involved with the current transfer.

BE0# applies to D0-D7

BE1# applies to D8-D15

BE2# applies to D16-D23

BE3# applies to D24-D31

No. of Byte Enables asserted indicates physical size of operand being transferred (1, 2, 3, or 4 bytes).

BE3#

BE2#

BE1#

BE0#

Operation

1

1

1

1

No Operation

1

1

1

0

Bank0 (8-bit)

1

1

0

1

Bank1 (8-bit)

1

0

1

1

Bank2 (8-bit)

0

1

1

1

Bank3 (8-bit)

1

1

0

0

Bank 0,1 (16-bit)

1

0

0

1

Bank 1,2 (16-bit)

0

0

1

1

Bank 2,3 (16-bit)

1

0

0

0

Bank 0,1,2(24-bit)

0

0

0

1

Bank 1,2,3(24-bit)

0

0

0

0

Bank 0,1,2,3 (32-bit)

Bus Cycle Definition Signals (W/R#, D/C#, M/IO# , LOCK#)

three-state outputs

W/R# :distinguishes b/w write and read cycles.

D/C# :distinguishes b/w data and control cycles.

M/IO# :distinguishes b/w memory and I/O cycles.

LOCK# :distinguishes b/w locked and unlocked bus cycles. It enables CPU to prevent other bus masters (like coprocessor) from gaining the control of system bus.

These control signals are decoded by the bus control logic to decide which bus cycle to be performed:

M/IO#

D/C#

W/R#

Bus Cycle Type

Locked?

0

0

0

Interrupt Acknowledge

Yes

0

0

1

Inactive

--

0

1

0

I/O Data Read

No

0

1

1

I/O Data Write

No

1

0

0

Memory Code Read

No

1

0

1

HALT

No

1

1

0

Memory Data Read

Sometimes

1

1

1

Memory Data Write

Sometimes

Bus Control Signals(ADS#,READY#,NA#,BS16#):

indicates when a bus cycle has begun and allow other system hardware to control address pipelining, data bus width and bus cycle termination.

ADDRESS STATUS (ADS#) : indicates that a valid address is driven at 80386DX pins.

TRANSFER ACKNOWLEDGE (READY#) : indicates that the previous bus cycle is complete and bus is ready for next bus cycle. It is useful for interfacing slow peripherals

NEXT ADDRESS REQUEST (NA#) :

This is used to enable address pipelining.

It indicates that the system is prepared to accept the next address even if the end of current cycle is not being acknowledged on READY#.

BUS SIZE 16 (BS16#) :

Asserting this input constrains current bus cycle to use only D0-D15 of data bus.

Bus Arbitration Signals (HOLD, HLDA)

BUS HOLD REQUEST (HOLD):

This input indicates some other device requires bus mastership.

HOLD must remain asserted as long as any other device is a local bus master.

HOLD is not recognized while RESET is asserted. (i.e. RESET has priority over HOLD and places the bus into an idle state rather than hold acknowledge state)

HOLD is level-sensitive.

BUS HOLD ACKNOWLEDGE (HLDA):

This output indicates 80386 has relinquished control of its local bus in response to HOLD asserted and it is in Bus Hold Acknowledge state.

This state offers near-complete signal isolation ( It is the only signal being driven by 80386)

The other output signals (D0-D31, BE0#-BE3#, A2-A31, W/R#, D/C#,M/IO#, LOCK# and ADS#) are in a high-impedance state so the requesting bus master may control them.

Coprocessor Interfacing

Intel 387DX numeric coprocessor is I/O mapped

As Intel386DX begins supporting a coprocessor instruction, it tests the BUSY# and ERROR# signals to determine if the coprocessor can accept its next instruction

Intel 387DX can be given its command opcode immediately

COPROCESSOR REQUEST (PEREQ) :

This input signal indicates a coprocessor request for a data operand to be transferred to/from memory by Intel386 DX.

In response, Intel 386DX transfers information between the coprocessor and memory

Since Intel386 DX has internally stored the coprocessor opcode being executed, it performs the requested data transfer with the correct direction and memory address.

PEREQ is level-sensitive

COPROCESSOR BUSY (BUSY#) :

This input indicates that coprocessor is still executing an instruction and is not yet able to accept another.

This sampling of BUSY# input prevents overrunning the execution of a previous coprocessor instruction.

BUSY# is level-sensitive

COPROCESSOR ERROR (ERROR#) :

This input signal indicates that the previous coprocessor instruction generated a coprocessor error of a type not masked by coprocessor's control register.

This input