A Direct-Conversion CMOS Radio Receiver for High Speed...
Transcript of A Direct-Conversion CMOS Radio Receiver for High Speed...
A Direct-Conversion CMOS Radio Receiver for High Speed Paging
A thesis submitted toThe Hong Kong University of Science and Technology
in partial fulfillment of the requirements forthe Degree of Doctor of Philosophy inElectrical and Electronic Engineering
by
Zhiheng Chen
Department of Electrical and Electronic Engineering
Bachelor of Engineering in Radio EngineeringSoutheast University, Nanjing, China, 1992
Master of Engineering in Radio EngineeringSoutheast University, Nanjing, China, 1995
November 2000
A Direct-Conversion CMOS Radio Receiver forHigh Speed Paging
by
Zhiheng Chen
Approved by:
Dr. Jack LauThesis Supervisor
Prof. John WeiThesis Examination Committee Member (Chairman)
Prof. Philip C. H. ChanThesis Examination Committee Member
Dr. Roger ChengThesis Examination Committee Member
Prof. Roland ChinThesis Examination Committee Member
Prof. Philip C. H. ChanHead of Department
Department of Electrical and Electronic EngineeringThe Hong Kong University of Science and Technology
November 2000
A Direct-Conversion CMOS Radio Receiver forHigh Speed Paging
by
Zhiheng Chen
for the Degree ofDoctor of Philosophy in Electrical and Electronic Engineering
at The Hong Kong University of Science and Technologyin November 2000
ABSTRACT
As the radio paging system is upgraded from POCSAG to the high speed FLEX or ERMES
protocol, both the modulation level and the baud rate are increased. What is unchanged is the
available bandwidth. Consequently, the modulation index is decreased and additional difficul-
ties are imposed on the design of a direct-conversion receiver. The main problems are (1) there
are no mature demodulation techniques available for zero-IF M-ary FSK signals, and (2) the
signal contains strong DC/low-frequency energy and hence DC offset cancellation is no longer
an easy task.
In this dissertation, a direct-conversion receiver is designed for high speed 4FSK radio pag-
ing applications. Various design considerations are discussed and analyzed. A zero-crossing
based counting/comparing scheme is chosen for the demodulation. The BER is improved by a
novel zero-crossing interpolation technique. Following official specifications on radio paging
receivers, a high level simulation is carried out to verify the demodulator performance and
derive circuit requirements. The self-mixing-related time-varying offset is suppressed by the
harmonic mixer to the noise level. A differential peak alignment method is developed to cancel
the mismatch-induced static offset. A frame-by-frame scheme is also proposed for further off-
set reduction.
A prototype receiver is fabricated in a 0.35 micron CMOS process, with all major building
blocks included. The front-end consists of a differential LNA and a quadrature harmonic
mixer. In the base-band, an AGC circuit provides over 30 dB gain tuning range. The channel
selection is done by a 5th order gyrator filter. The demodulator is formed by a 1-level zero-
crossing interpolator, clock recovery circuits and decision logics. Main functions of the
receiver has been verified.
To My Parents
ACKNOWLEDGEMENTS
Just like any other theses, this one is done with the help from a lot of people. Among them, my
supervisor Dr. Jack Lau is the first one to whom I would like to express my most sincere
thanks. In these years of studies, he has been the most important source of support. What I
have learnt from him is far beyond the scope of academic research. His optimistic character,
unyielding will plus intellectual maturity form the key to success. Our whole research group
has benefited from his foresight and creativity. It is an invaluable experience to have been with
Dr. Jack Lau in the past 5 years.
And I’m very grateful to those nice and talented professors of the EEE department for their
excellent course materials and teaching attitudes. They deserve the greatest respect. It is their
guidance, patience and encouragement that has led me to the exciting world of knowledge and
innovation. During my first semester in HKUST, Dr. Howard Luong showed me the beauty of
analog circuit designs, of which I had never been aware before. Dr. Chi-Ying Tsui, on the other
hand, guided me through CMOS digital designs, from the very bottom to the system level. Dr.
Roger Cheng introduced me to the mysterious world of personal wireless communication sys-
tems. Dr. Curtis Ling taught me the nature of high frequency components and circuits. I also
want to thank Prof. Charlie Sodini of MIT who provided practical yet deep insight of CMOS
analog circuits related issues during his visit at HKUST and Prof. Philip Chan who was my
mentor in the first year of my Ph.D. program.
This thesis could not have been completed without the contribution of Mr. Zhaofeng Zhang
and Mr. Louis Tsui, two of my group-mates. Zhaofeng developed the CMOS harmonic mixer
and Louis designed the differential LNA for my receiver. I’m indebted again to Zhaofeng for
his valuable suggestions on my thesis and the generous help he offered in many other aspects.
I appreciate very much the first class support from Mr. Siu-Fai Luk and Mr. Jack Chan.
With great kindness, they tried their best to satisfy my odd requests on EDA tools and tape-out
matters. The same kindness was also offered by Ms. Wendy Yuen, Ms. Venus Pang and other
ladies of the Department Office who helped me through a lot of administrative matters. And I
am obliged to many other people who supported my work in countless ways. Mr. Allen Ng of
DCL taught me the wire bonding skill; Mr. Joe Lai of WCL and Mr. Hi-Yin Man of the ELEC
storeroom provided the convenience to fulfill my measurements.
Thanks should also go to my fellow UMEN. As senior UMAN members, Frankie Hui,
Alan Pun, Louis Tsui, Tony Yeung and me shared many memorable days and nights. Keqiang
Shen and Zhiqing Li provided precious advice and suggestions. Wing-Faat Liu shared the
stress with me. Jing-Jung Tang, Cary Cheung, Jackey Cheung and Ricky Choi brought the lab-
oratory a lot of fresh air and fun.
Besides, I would like to take this opportunity to thank some old friends: William Lam,
Felix Wong, Maurice Chan, Andrew Hui, Vincent Cheung, Darwin Yim, Ho-Yin Pang, Lang
Lin, Wei Jin, Corbett R. Rowell and more. I enjoyed very much the time I spent with them. It is
also a good time for me to thank all my thesis examination committee members for their time,
earnestness and challenges.
Finally, I want to say thanks to my wife Maggie Song for her love, encouragement, and
patience as well as the numerous nice figures she created for my thesis. She is the reason for
me to enjoy my life, to take challenges and to be happy.
Table of Contents
Chapter 1 Introduction 11.1 High Speed Paging Systems and The FLEX Protocol . . . . . . . . . . . . . . . 1
1.1.1 FLEX Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.1.2 FLEX Signal Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 The Direct-Conversion Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Direct-Conversion for FLEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.4 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.5 Thesis Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2 FSK Modulation and Demodulation 82.1 The FSK Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.2 The Modulation Index and FSK Spectra . . . . . . . . . . . . . . . . . . . . . . . . . 92.3 The Phasor Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.4 FSK Demodulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.1 The Correlation-Squaring Receiver . . . . . . . . . . . . . . . . . . . . . . 122.4.2 The Quadrature Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.4.3 The Digital Phase Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 ZIFZCD and ZCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 3 System Modeling and Circuit Requirements 173.1 The Receiver Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.2 Official Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.3.2 Desensitization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.3.3 Intermodulation Response Rejection . . . . . . . . . . . . . . . . . . . . . 233.3.4 Phase Mismatch, Frequency Drift and Phase Noise . . . . . . . . . 243.3.5 RF Front-End Budget. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
vii
CONTENTS viii
Chapter 4 Circuit Design I 294.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294.2 LNA and Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.1 The Differential LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304.2.2 The Harmonic Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 VGA and AGC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324.3.1 The Variable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 334.3.2 The Control Circuitry and VGA Gain . . . . . . . . . . . . . . . . . . . . 354.3.3 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.4 Low Pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404.4.1 The Gyrator and Gyrator-C Simulated Inductors . . . . . . . . . . . 414.4.2 Simulation of The LC Ladder . . . . . . . . . . . . . . . . . . . . . . . . . . 424.4.3 The Linearized Transconductor . . . . . . . . . . . . . . . . . . . . . . . . . 444.4.4 Simulated Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.5 The DC Offset Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Chapter 5 Circuit Design II 515.1 The Overall Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515.2 Zero-Crossing Interpolator and Hard-Limiters . . . . . . . . . . . . . . . . . . . 525.3 Zero-crossing Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545.4 Direction and Speed Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.4.1 The Dual-Input 5-Bit Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 575.4.2 The Direction Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595.4.3 The Speed Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.5 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615.5.1 Transition Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625.5.2 Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705.5.3 VCO and Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735.5.4 Loop Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.6 An Overall Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Chapter 6 Measurement Results 806.1 AC Transfer Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806.2 Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816.3 Harmonic Distortion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836.4 AGC Gain and Dynamics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886.5 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906.6 Demodulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Chapter 7 Future Work and Conclusion 987.1 Possible Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.1.1 DC Offset Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
CONTENTS ix
7.1.2 System Noise Figure and Gain Distribution . . . . . . . . . . . . . . 1007.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
References 103
Appendix A Circuit Details 107A.1 The AGC Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
A.1.1 The Differential Variable MOS Resistor (DiffRes) . . . . . . . . . 109A.1.2 The OPAMP (Opamp1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109A.1.3 The Peak Detector (Rect2). . . . . . . . . . . . . . . . . . . . . . . . . . . . .111A.1.4 The Attenuator (LinAmp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
A.2 The Low Pass Filter (Gyt5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112A.2.1 The Gm Cell (Gm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
A.3 Offset Cancellation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112A.4 The Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113A.5 Zero-Crossing Interpolators and Pulse Generators . . . . . . . . . . . . . . . .114
A.5.1 The Adder (Iadd_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115A.5.2 The Limiter (Limiter). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115A.5.3 The Zero-Crossing Pulse Generator (PUL_Gen). . . . . . . . . . . .117
A.6 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118A.6.1 The Delay Element (CRC_delay) . . . . . . . . . . . . . . . . . . . . . . .119A.6.2 The Transition Detector (CRC_RS). . . . . . . . . . . . . . . . . . . . . .119A.6.3 The Phase Detector (CRC_PD) . . . . . . . . . . . . . . . . . . . . . . . . 121A.6.4 The Charge Pump Circuit(CRC_pump). . . . . . . . . . . . . . . . . . 121A.6.5 The VCO (CRC_v2i and CRC_ico) . . . . . . . . . . . . . . . . . . . . 122
A.7 The Decision Logic (DEMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122A.7.1 The Zero-Crossing Counter (Counter). . . . . . . . . . . . . . . . . . . 123A.7.2 The Direction Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123A.7.3 The speed comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
A.8 Building Blocks Using The Transmission Gate Logic. . . . . . . . . . . . . 124A.9 Biasing Circuits and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
A.10 List of Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Appendix B Base-band Testing 133B.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133B.2 The Testing Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134B.3 Testing Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
B.3.1 Power Supplies, Signal Sources and Analyzers. . . . . . . . . . . . 137B.3.2 Input Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
B.4 Operation Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Appendix C List of Publications 141
List of Figures
Figure 1.1. FLEX signal structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 2.1. Analytical power spectra of both the FLEX and POCSAG signals at dif-
ferent data rates (modulation indices). The y-axis is in dB; x-axis shows the frequency offset from the carrier in kHz. The lines in (a) and (b) arediscrete spectral components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2.2. The phasor diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Figure 2.3. Demodulation of BFSK signals with the correlation-squaring receiver. . . 12Figure 2.4. FM quadrature detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 2.5. Principle of Vance’s direct conversion radio paging receiver. . . . . . . . . . . 14Figure 2.6. 1-level zero-crossing interpolation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 2.7. The ZIFZCD with 1-level zero-crossing interpolation. . . . . . . . . . . . . . . . 16Figure 2.8. The zero-crossing pulse generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 3.1. The receiver model. The demodulator is shown in Figure 2.7. . . . . . . . . . 17Figure 3.2. BERs at different interpolation levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 3.3. Effect of the 2nd order nonlinearity on desensitization. . . . . . . . . . . . . . . . 22Figure 3.4. Effect of the 3rd order nonlinearity on desensitization. . . . . . . . . . . . . . . . 22Figure 3.5. The IMRR is 58 dB when the unwanted signals are 1 and 2 channels
above (m=1) or below (m=-1) the nominal, respectively. The meaningsof m, W and U are defined in Section 3.2. . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 3.6. Sensitivity degradation due to I/Q phase mismatch.. . . . . . . . . . . . . . . . . . 25Figure 3.7. Sensitivity degradation due to LO frequency drift. . . . . . . . . . . . . . . . . . . 25Figure 3.8. Constant overall IIP2 curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 3.9. Constant overall IIP3 curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 4.1. Block diagram of the receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 4.2. The differential low noise amplifier.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 4.3. The CMOS harmonic mixer with current injection. . . . . . . . . . . . . . . . . . . 32Figure 4.4. The AGC loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 4.5. The MOS differential variable resistor (a) and its equivalent (b). . . . . . . . 35Figure 4.6. The peak detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
x
LIST OF FIGURES xi
Figure 4.7. The level shift network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Figure 4.8. VGA gain as a function of the control voltage Vc. . . . . . . . . . . . . . . . . . . . 38Figure 4.9. Response of the AGC to a 2 kHz sinusoidal input decreasing from 2 Vpp
by 6 dB every 10 ms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 4.10. Response of the AGC to a 4.8 kHz sinusoidal input increasing from 1 mVpp
by 25 dB at 5 ms and 10 ms respectively.. . . . . . . . . . . . . . . . . . . . . . . . . . 39Figure 4.11. The gyrator and its small signal equivalent circuit. . . . . . . . . . . . . . . . . . . 42Figure 4.12. Simulation of inductors using gyrators and capacitors. . . . . . . . . . . . . . . . 43Figure 4.13. The 5th order gyrator-C elliptic low pass filter and its LC ladder prototype.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Figure 4.14. The linearized transconductor (a) and its biasing circuit (b). . . . . . . . . . . . 45Figure 4.15. Differential output current and transconductance of the linearized
transconductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Figure 4.16. Frequency response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Figure 4.17. Thermal noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Figure 4.18. Waveforms of the zero-IF 4FSK signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Figure 4.19. A half-wave rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Figure 5.1. The 4FSK demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Figure 5.2. The first level zero-crossing interpolator. . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 5.3. The adder schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 5.4. The transfer characteristic of the adder. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 5.5. The hard-limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 5.6. The zero-crossing pulse generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 5.7. Signal waveforms of the pulse generator. . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 5.8. The final detection stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Figure 5.9. The dual-input 5-bit counter.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Figure 5.10. The direction comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Figure 5.11. The speed comparator SCMP.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Figure 5.12. The clock recovery circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Figure 5.13. Simple transition detection with a trigger. . . . . . . . . . . . . . . . . . . . . . . . . . 63Figure 5.14. Lee’s synchronization scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Figure 5.15. Model of the transition detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Figure 5.16. Waveforms of the transition detector model. . . . . . . . . . . . . . . . . . . . . . . . 65Figure 5.17. Block diagram of the transition detector, the output stage excluded. . . . . . 66Figure 5.18. Working principle of the AC block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Figure 5.19. Circuit diagram of the AC block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Figure 5.20. The AOA block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Figure 5.21. State transition diagram and state transition table of the “11” detector. . . . 69Figure 5.22. Circuit diagram of the “11” detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Figure 5.23. Output stage of the transition detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Figure 5.24. The phase detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Figure 5.25. Dependence of the error signal on input duty cycle (a) and data transitions
LIST OF FIGURES xii
(b).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Figure 5.26. Waveforms of the phase detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Figure 5.27. The complete VCO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Figure 5.28. Multivibrator frequency vs. bias current. . . . . . . . . . . . . . . . . . . . . . . . . . . 74Figure 5.29. The charge pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Figure 5.30. Impact of the fout-dependent delay on the acquisition process: fin and fout
are (a) uncorrelated and (b) correlated.. . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Figure 5.31. An overall simulation of the demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . 79Figure 6.1. The die photo of the whole prototype receiver. . . . . . . . . . . . . . . . . . . . . . 80Figure 6.2. Simulated and measured AGC transfer curves at the maximum gain. . . . . 81Figure 6.3. Simulated and measured transfer curves of the LPF. . . . . . . . . . . . . . . . . . 82Figure 6.4. Simulated and measured transfer curves of the offset cancellation stage. . 82Figure 6.5. Cascaded noise voltage spectral densities at the output of the AGC, the
LPF and the offset cancellation stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Figure 6.6. Input-referred noise spectral densities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Figure 6.7. Noise simulation that estimates the flicker noise parameters by curve fitting.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Figure 6.8. Signal spectra of the harmonic distortion measurement. . . . . . . . . . . . . . . 85Figure 6.9. Signal spectra of the harmonic distortion measurement, with the input
inverted. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Figure 6.10. AGC gain at different input levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Figure 6.11. AGC output levels at different input levels. . . . . . . . . . . . . . . . . . . . . . . . . 89Figure 6.12. Measured AGC response to input amplitude variations. The input signal
is at 1.6 kHz and has an amplitude switching between 100 and 200 mV. . 90Figure 6.13. Simulated AGC response to the input signal given in Figure 6.12. . . . . . . 90Figure 6.14. Locking process of the clock recovery circuit. . . . . . . . . . . . . . . . . . . . . . . 91Figure 6.15. Spectra of the clock signal, before and after lock. . . . . . . . . . . . . . . . . . . . 92Figure 6.16. AGC I/Q input and LPF output waveforms.. . . . . . . . . . . . . . . . . . . . . . . . 92Figure 6.17. Signal Q1 (hard-limited version of the Q1 in Figure 5.1 on page 51). . . . . 93Figure 6.18. Signal N1 (see also Figure 5.1 on page 51). . . . . . . . . . . . . . . . . . . . . . . . . 93Figure 6.19. The asynchronous/synchronized direction signal. . . . . . . . . . . . . . . . . . . . 93Figure 6.20. The asynchronous/synchronized speed signal. . . . . . . . . . . . . . . . . . . . . . . 94Figure 6.21. Simulated demodulator input and output waveforms in a 5 ms interval. . . 95Figure 6.22. The incomplete transition detection and its effect on the demodulation. . . 96Figure A.1. The AGC loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Figure A.2. The differential variable MOS resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . 109Figure A.3. The OPAMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109Figure A.4. The CMFB circuit used in the OPAMP. . . . . . . . . . . . . . . . . . . . . . . . . . . .110Figure A.5. The CMFB buffer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110Figure A.6. The negative peak detector.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111Figure A.7. The attenuator and the source follower used in the AGC loop. . . . . . . . . .111Figure A.8. The 5th order gyrator-type elliptic filter. . . . . . . . . . . . . . . . . . . . . . . . . . .112
LIST OF FIGURES xiii
Figure A.9. The linearized Gm cell.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112Figure A.10. A simple offset cancellation method making use of a peak detector and an
adder.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112Figure A.11. The demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113Figure A.12. The zero-crossing interpolator, hard-limiters and zero-crossing pulse
generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114Figure A.13. The adder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115Figure A.14. The limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115Figure A.15. The first 2 stages of the limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116Figure A.16. The self-biased amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116Figure A.17. The zero-crossing pulse generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117Figure A.18. The clock recovery block.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118Figure A.19. The delay element. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119Figure A.20. The transition detector (the output stage excluded). . . . . . . . . . . . . . . . . . .119Figure A.21. The AC block of the transition detector.. . . . . . . . . . . . . . . . . . . . . . . . . . 120Figure A.22. The AOA block of the transition detector. . . . . . . . . . . . . . . . . . . . . . . . . 120Figure A.23. The “11” detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Figure A.24. The phase detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Figure A.25. The charge pump circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Figure A.26. The VCO circuit.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Figure A.27. The decision logic of the demodulator.. . . . . . . . . . . . . . . . . . . . . . . . . . . 122Figure A.28. The zero-crossing counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Figure A.29. The direction comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Figure A.30. The speed comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Figure A.31. Transmission gate based logic gates and their symbols.. . . . . . . . . . . . . . 124Figure A.32. The basic D flip-flop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124Figure A.33. The resetable D flip-flop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124Figure A.34. The 2 to 1 multiplexor (MUX21) and the 4 to 2 multiplexor (MUX42). . 125Figure A.35. The threshold voltage referenced current source (cell: iRefVth).. . . . . . . 126Figure A.36. The simple circuit for biasing the demodulator (cell: iRefSimp). . . . . . . 126Figure A.37. The analog buffer (cell: follow). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127Figure A.38. The digital buffer (cell: driver). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127Figure B.1. Pin assignment diagram of the base-band circuits. . . . . . . . . . . . . . . . . . . 133Figure B.2. The testing circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Figure B.3. The PCB designed for the base-band testing circuit. The size is
98.5mm×123.6mm.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136Figure B.4. The zero-IF quadrature components of the FSK signal of the “+3−3”
symbol series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139Figure B.5. Input setups for different types of measurement. The DC voltage is 1.1V.139
List of Tables
Table 1.1 Main features of POCSAG, FLEX and ERMES. . . . . . . . . . . . . . . . . . . . . . 2Table 3.1 RF Front-End Budget.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Table 5.1 State transition table of the counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Table 5.2 Truth table of the speed comparator.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Table 5.3 State transition table of the “11” detector. . . . . . . . . . . . . . . . . . . . . . . . . . 69Table 5.4 Truth table of the output stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Table 6.1 Cascaded harmonic distortions of the AGC, the LPF and the offset
cancellation stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Table 6.2 Performance summary of the base-band circuit.. . . . . . . . . . . . . . . . . . . . . 96Table 6.3 Performance summary of the front-end. . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Table 6.4 Summary of the whole receiver (off-chip matching inductor). . . . . . . . . . 97Table 7.1 Possible gain distribution and signal levels. . . . . . . . . . . . . . . . . . . . . . . . 100Table A.1 List of components.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Table B.1 Pin assignment of the base-band circuits . . . . . . . . . . . . . . . . . . . . . . . . . 134Table B.2 External components list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Table B.3 Data points of the arbitrary waveform. Frequency = 800 kHz. . . . . . . . . 139Table B.4 Typical DC operation points. Vdd=3.0V, Vdc=1.1V. . . . . . . . . . . . . . . . . 140
xiv
CHAPTER 1Introduction
The revolutionary advances in solid-state devices and integrated circuits (ICs) has brought the
world of wireless communications into a completely new era. The once bulky and luxury
mobile phones for example, are now handy and common tools for every individual from every-
where. Here new technologies act as the driving force which has been pushing the personal
wireless communications market into today’s boom. In return, the market motivates the tech-
nology by putting even aggressive demands on the performance, cost, form-factor and power
consumption of the mobile receiver/transceiver. Despite the remarkable progress made in the
very large scale integration (VLSI) technology, analog circuit design does not benefit as much
from the scaling-down and other advances, in terms of level of integration, power consumption
etc., as digital circuit design does. To meet these requirements, communication system consid-
erations, receiver/transceiver architecture innovations play the most essential role.
In this dissertation, we discuss the architecture and circuit design of a direct-conversion 4-
level frequency shift keying (FSK) radio receiver. This project is motivated by the new high
speed radio paging standard FLEX and the successful implementation of the direct-conversion
scheme in the binary FSK-based POCSAG paging system.
1.1 High Speed Paging Systems and The FLEX Protocol
For years, traditional pagers have been running in compliance with a standard known as POC-
SAG1 which utilizes the modulation scheme of binary FSK (BFSK) to support the data rate of
1. Post Office Code Standardization Advisory Group
1
CHAPTER 1 Introduction 2
1200 or 24001 bits per second (bps). The insatiable quest for information and the growth of
new paging markets in rapidly developing countries have called for a more efficient and higher
speed system. Two such systems, ERMES2 in Europe and FLEX3 in America and Asian Pacific
region, both make use of 4FSK and enable comparable top data rates of 6250 and 6400 bps.
We have focused on the latter for its popularity in the interested region but the former can be
treated in very much the same way. Furthermore, the concept also applies to other systems in
which digital frequency modulation is used. Table 1.1 gives a comparison of the 3 mentioned
standards.
1.1.1 FLEX Overview
FLEX is designed to be an adaptive protocol with the ability to adjust its date rate and modula-
tion level according to the channel loading. The idea is to achieve the best quality in low-traffic
hours and/or territories and to maximize the channel capacity when the traffic goes up. At its
top speed, the 6400 bps data rate enables 4 concurrent 1600 bps messages to be sent in a single
channel and thus increases the channel capacity by 4 times. It also offers better error immunity
by applying the Bose-Chadhuri-Hocquenghem (BCH) coding along with an interleaving pro-
cess. More information about this protocol can be found on Motorola’s FLEX web site [1].
1.1.2 FLEX Signal Structure
The FLEX signal is transmitted as a series of 4-minute cycles. Each cycle consists of 128
1.875-second long frames. A pager may be assigned to process any number of these frames
and skips the rest, thus minimizing the power for signal processing. As shown in Figure 1.1,
each FLEX frame has a synchronization portion and a data portion. The synchronization por-
tion consists of:
1. These are typical values. Other options include the low speed 512 bps and high speed but very uncommon 4800 bps.2. European Radio Message System3. An acronym for “FLEXible wide area paging protocol”, also a trademark of Motorola Inc.
Table 1.1 Main features of POCSAG, FLEX and ERMES.
POCSAG FLEX ERMES
Data Rates 1200 or 2400 bps up to 6400 bps 6250 bps
Modulation Binary FSK Binary or 4FSK 4FSK
Frequency Deviation 4.5 kHz 1.6 and 4.8 kHz 1.5625 and 4.6875 kHz
CHAPTER 1 Introduction 3
• First synchronization signal at 1600 bps for frame lock,
• 11-bit frame information word (7-bit frame number + 4-bit cycle number), and
• Second synchronization signal as the data rate indicator.
The data portion is divided into 11 data blocks, lasting 160 ms each. Thus the synchronization
portion is 115 ms long. This sets the constraint on the settling performance of the receiver.
Figure 1.1 is duplicated from [2] where a detailed description of the signal structure is pro-
vided, as well as other information such as FLEX message word definitions etc.
1.2 The Direct-Conversion Technique
Ever since the introduction of the superheterodyne system, it has been adopted in virtually
every radio receiver. The idea of down-converting the interested spectrum to one or more inter-
mediate frequencies (IFs) makes it possible to process the signal under well-controlled condi-
tions. High selectivity is achieved by inserting high quality filters at each IF strip. With the
need to suppress the image, an image-rejection filter is required at the radio frequency (RF)
front-end. The amount of image being rejected depends on the first IF frequency. Therefore,
conventional superheterodyne receivers have to work at a relatively high IF (say, 10% of the
carrier frequency). As a result, in addition to the RF image-rejection filter, high quality band-
Figure 1.1. FLEX signal structure.
Frame 127
Frame 0
Frame 1
Frame 2
Frame 125
Frame 126
Frame 127
One Cycle = 4 minutes
FrameInfo
Sync2Sync1 Block 0Word 0 to 7
Block 9Word 72 to 79
Block 10Word 80 to 87
One Frame = 1.875 seconds
One Block= 160 ms115 ms
CHAPTER 1 Introduction 4
pass IF filters must be used for an acceptable selectivity. As the transfer characteristics of these
filters are usually well beyond the capability of today’s IC technology, discrete passive devices
become the most common choice. On the positive side, the performance is guaranteed. On the
negative side, however, the drawback is at least 3-fold:
• higher cost;
• lower integration level;
• higher power consumption.
These points become very unfavorable when price and size is the issue. A lot of effort has
been made to seek an alternative or modified architecture to the conventional one such that the
requirements of the image-rejection and IF filters can be relaxed. The ultimate goal is to com-
pletely eliminate these off-chip filters. The RF filter may be realized in some applications in its
simplest form by utilizing the band-pass properties of the antenna and the low-noise amplifier
(LNA) without the burden of the image-rejection specification. The IF filters should be readily
replaced by their integrated counterparts.
Several receiver architectures have been conceived to implement the idea, each with its
pros and cons. The low-IF and direct-conversion (or zero-IF) are two of the most well-known.
The low-IF solution is based on the fact that theoretically, the image frequency can be
removed by a specially designed mixer (the image-rejection mixer) so that the IF frequency
can be lowered to enable the use of monolithic filters [3]. The problem associated with this
type of architectures is the limited image rejection ratio due to the mismatch in the image-
rejection mixer.
Direct-conversion is believed to be the most simple and straightforward way to build a
radio receiver. That’s why its embryonic form appeared only 6 years later than the non-zero-IF
superheterodyne receiver [13]. By converting the RF signal directly to the base band, the
image frequency no longer exists. The benefits are obvious: no circuitry is needed to do the
task of image-rejection; IF filtering could be performed by low pass filters (LPFs) in the form
of Gm-C or switched-capacitor (SC). Nevertheless, the idea didn’t seem to be much useful in
practical applications until the 80’s when it proved its value in the POCSAG radio paging
receiver[4][5]. Many more examples follow [6-10], including the designs presented in the lat-
est IEEE International Solid-State Circuits Conference (ISSCC) [11][12].
CHAPTER 1 Introduction 5
The merits and drawbacks of direct-conversion have been investigated intensively since its
success. Common design issues and their possible solutions have been identified and summa-
rized [3][13]. The biggest concern is known to be the DC offset related problems. Undesired
DC components are originated mainly from two different mechanisms: self-mixing and even
order distortion. In a fully balanced design, the latter is a result of device mismatch. When
referred to the output of the mixer, the offset level can easily reach the order of 10 mV. This is
more than enough to corrupt the weak signals (10 to 100 µV) and saturate the following stages.
To avoid the disaster, some kind of offset-cancellation strategy is inevitable. In the pager
example, AC-coupling capacitors are used to block the DC offset. Receivers work in the time-
division multiple access (TDMA) system can make use of the idle time slot to measure the off-
set and perform the cancellation in the coming operation mode. Recently, encouraging
progress has also been made on the reduction of the self-mixing caused offset by means of har-
monic mixing [33].
DC offset is not the only problem, troubles also come from the flicker or 1/f noise which is
found in all active and some passive devices, especially those in the CMOS technology. Just
like the offset, flicker noise can dominate weak signals before enough amplification is pro-
vided. Device size and bias conditions affect the flicker noise spectral density level and thus
can be tuned when necessary. More advanced techniques such as chopper stabilization and cor-
related double sampling (CDS) are very effective in reducing offset and low-frequency noise at
the price of increased complexity, power consumption and thermal noise.
Other things like the local frequency (LO) leakage must also be treated carefully but DC
offset and flicker noise is the main barrier which limits the direct-conversion to only a few type
of practical applications.
1.3 Direct-Conversion for FLEX
Because of its compact and low cost nature, direct-conversion is particularly appealing in low-
to medium-end devices like the pager units. The POCSAG receiver makes a good example.
While the new paging systems are more efficient, they do encounter difficulties during a simi-
lar refinement.
CHAPTER 1 Introduction 6
The first problem is how to suppress or cancel the DC offset. AC-coupling is no longer a
valid method due to the fact that, unlike POCSAG, the FLEX system incorporates a higher
modulation level with a much higher data rate and consequently creates significant energy in
the vicinity of DC. There is no perfect solution but as the first step we will use the harmonic
mixer to minimize the self-mixing related offset. Possible schemes for the reduction of mis-
match induced offset are also discussed.
The second problem is how to demodulate the zero-IF 4FSK signal. In conventional super-
heterodyne FSK (or FM) receivers, the frequency discriminator is commonly used to convert
frequency domain information to voltage (or current) domain. High sensitivity can be achieved
in this way but the penalty is again increased cost and lowered integration level. At the same
time, this approach works only at a non-zero IF frequency. Therefore it is not an appropriate
choice. Demodulation in the direct-conversion POCSAG receiver employs a phase-compari-
son method which makes a decision by simply observing the phase difference between the
quadrature I and Q components of the down-converted signal. Unfortunately it works only
with the binary FSK. A general M-ary FSK demodulator can be constructed by combining the
phase-comparator with a zero-crossing counter [7] which calculates the number of zero-cross-
ings in a symbol period. Its accuracy can be improved using a technique (termed zero-crossing
interpolation here) which generates additional zero-crossings for detection. It has been demon-
strated [14] that as more additional zero-crossings are generated the error probability
approaches that of the discriminator type demodulator.
1.4 Contributions
The primary contribution of this thesis is the system modeling, analysis, circuit design and
integration of a direct-conversion receiver for high speed radio paging applications. This is, to
the best of the author’s knowledge, the first time that the design of a direct-conversion receiver
for the 4FSK FLEX or ERMES system is reported. A combined solution which incorporates
the harmonic mixing mechanism with a differential peak alignment method is applied to com-
bat the DC offset problem. Information loss due to the use of the conventional DC-block
method [4-6] is thus avoided. The demodulation is done in the digital domain. The combina-
tion of the newly-developed zero-crossing interpolation (ZCI) technique and an effective clock
CHAPTER 1 Introduction 7
recovery scheme not only improve the bit error rate (BER) degradation resulted from low mod-
ulation indices but also yield a low-cost solution. These features make the receiver a novel and
unique design. Specifically, the thesis work that I have done independently can be summarized
in the list given below:
• a feasibility study on applying the direct-conversion architecture in FLEX paging
receivers [15];
• the modeling of the counter type M-ary FSK demodulator for BER analysis in the
additive white Gaussian noise (AWGN) environment and the derivation of circuit
requirements based on the BER analysis [16];
• the planning, design1 and integration of a CMOS prototype receiver which contains all
major building blocks [17-19];
• the introduction of a possible DC offset reduction method for direct-conversion receivers
working in frequency-modulated systems where AC-coupling is not viable.
1.5 Thesis Layout
A review on the FSK signal and its demodulation methods is given in Chapter 2. The counter
type zero-IF zero-crossing M-FSK demodulator (ZIFZCD) and the ZCI technique are then
introduced. Chapter 3 describes the modeling and performance of the ZIFZCD, followed by a
set of nominal circuit requirements which are necessary to achieve official paging receiver
specifications. Details on the circuit design of a prototype receiver are treated in the following
two chapters, 4 and 5. Chapter 6 presents the measurement results of the prototype receiver and
Chapter 7 concludes the whole design flow and gives suggestions on the future work. In
Appendices A and B detailed circuit parameters and measurement setup are provided.
1. The circuit design work covers the automatic gain control loop, the low-pass channel selection filter, the demodulator and the clock recovery loop. The RF front-end, including the low noise amplifier and the quadrature mixer, are designed by other people, as will be stated in Chapter 4.
CHAPTER 2FSK Modulation and Demodulation
As one of the basic band-pass modulation formats, FSK is used extensively in modern digital
communication systems because of its better noise immunity (compared to amplitude modula-
tion) and easier implementation (compared to phase modulation). The radio paging and cord-
less phone systems are two of the familiar examples.
In this chapter a review on some important properties of the FSK signal will first be given,
followed by a discussion of different demodulation methods. Finally the counter-type demodu-
lator and the ZCI technique will be introduced.
2.1 The FSK Signal
An FSK modulated signal has a constant envelop and very often a continuous phase (CPFSK).
In the mathematical form, it can be written as
(2.1)
where A0 is the signal amplitude, fc is the carrier frequency which can be either the RF fre-
quency fRF or the IF frequency fIF, α is the random carrier phase and
(2.2)
is the instantaneous phase introduced by the frequency modulation. Here we assumed that
there is no amplitude modulation, the digital symbol train starts from number 0 and the modu-
s t( ) A0 2πfct φ t( ) α+ +[ ]cos⋅=
φ t( ) 2πfd ang τ nT–( )n 0=
∞
∑ τd0
t
∫=
8
CHAPTER 2 FSK Modulation and Demodulation 9
lation begins at the time t = 0. In equation (2.2) fd is the minimum frequency deviation; T is the
symbol duration; an is the M-ary digital symbol value and
is a rectangular pulse. To use the bandwidth efficiently, the sinusoids used to represent the
symbols are usually evenly distributed over the frequency axis, resulting in a constant tone
spacing. In this case, fd can also be considered as a half tone spacing. Taking the 6400 bps 4-
FSK FLEX signal as an example,
While the carrier frequency affects only the location of the signal spectrum, the data rate and
frequency deviation (or tone spacing) determine the spectrum shape and other important prop-
erties. A specific parameter known as the modulation index is used to describe these proper-
ties.
2.2 The Modulation Index and FSK Spectra
The modulation index h is defined by the tone spacing to symbol rate ratio:
(2.3)
It has a close relationship to the signal spectrum. Higher modulation indices yield better spec-
tral efficiency but risk higher error rates. Power spectra of FSK signals can be obtained by sim-
ulation or measurement. A general analytical computation involves complex mathematical
theories and is beyond the scope of this dissertation. An excellent analysis can be found in
[20]. Here the result is directly applied to the interested cases. Figure 2.1 shows the power
spectra of both the FLEX (4FSK at 6400 bps and BFSK at 3200 bps) and POCSAG (BFSK
2400 and 1200 bps) signals. Assumption is made that the modulating digital bits are statisti-
cally independent. Observing the plots, one comes to the conclusion naturally that the energy
g t( )1 0 t T≤ ≤0 otherwise
=
fd 1.6 kHz=
an 1± 3±, ∈T 3.2 kHz=
h 2fdT=
CHAPTER 2 FSK Modulation and Demodulation 10
gets more confined to the tone frequencies as h increases. As a result, nulls are formed at DC in
the POCSAG spectra whereas significant DC components exist in the FLEX signals, espe-
cially when 4FSK modulation is used. This imposes additional difficulties to the direct-conver-
sion implementation of the FLEX receiver, as will be discussed later.
2.3 The Phasor Diagram
In a direct conversion FSK receiver, the input signal is down-converted to the base-band in-
phase (I) and quadrature-phase (Q) signals1. As the carrier phase is irrelevant in a non-coherent
detection process which we will focus on, it will be regarded as zero from now on, unless oth-
erwise stated. Thus, these two signals can be written as2
(2.4a)(2.4b)
1. The I and Q signals are also known as the real and imaginary parts of the band-pass RF signal’s complex envelop.2. The Q signal may also be expressed as sQ = −Asinφ(t), as the two quadrature LO signals are switchable.
−15 −10 −5 0 5 10 15−60
−50
−40
−30
−20
−10
0
−15 −10 −5 0 5 10 15−60
−50
−40
−30
−20
−10
0
−15 −10 −5 0 5 10 15−60
−50
−40
−30
−20
−10
0
−15 −10 −5 0 5 10 15−60
−50
−40
−30
−20
−10
0
Figure 2.1. Analytical power spectra of both the FLEX and POCSAG signals at different data rates (modulation indices). The y-axis is in dB; x-axis shows the frequency offset from the carrier in kHz. The lines in (a) and (b) are discrete spectral components.
(a) FLEX 6400, 4FSK; h=1.0 (b) FLEX 3200, BFSK; h=3.0
(d) POCSAG 1200; h=7.5(c) POCSAG 2400; h=3.75
sI A φ t( )cos=sQ A φ t( )sin=
CHAPTER 2 FSK Modulation and Demodulation 11
(2.4)Here φ(t) is defined in (2.2). The signal paths through which sI and sQ are processed are called
the I-channel and Q-channel, respectively. With these definitions, the FSK signal can be
explained in a more direct way using the phasor diagram shown in Figure 2.2. A phasor dia-
gram provides necessary information on the phase and hence the I/Q signals’ variations. The
phase variation can be characterized by the rotation speed and direction of the phasor:
In a BFSK system, the speed is a constant and the direction becomes the only variable. For M-
ary signals, the phasor rotates at different speeds depending on the instantaneous data value.
Consequently, demodulation of an MFSK signal requires the detection of both the speed and
direction. On the other hand, when the phasor rotates across any of the two axes from one
quadrant to another, a zero-crossing appears in either the I- or Q-channel. Counting both chan-
nels, the nominal number of zero-crossings in one symbol interval can be shown to be
(2.5)
The information a frequency modulated signal carries is solely embodied in the zero-crossings.
This feature will be used later to demodulate the signal.
speed1
2π------ d
dt----- φ t( ) an fd= =
direction an( )sgn=
Figure 2.2. The phasor diagram.
I
Q2πanfd
φ(t)
NZC 2 an h=
CHAPTER 2 FSK Modulation and Demodulation 12
2.4 FSK Demodulation
Theoretically, coherent detection is the optimal solution. However, a coherent receiver requires
the precise carrier frequency and phase information (fc and α in (2.1)) of the incoming signal.
Thus, a considerable amount of complexity has to be added into the system to achieve a satis-
factory carrier recovery. The problem gets even worse in a mobile fading channel. On the other
hand, non-coherent detection methods are easy to implement and used widely in applications
where a coherent method is not affordable or not necessary.
2.4.1 The Correlation-Squaring Receiver
When the carrier phase is unknown, it can be treated as a uniformly distributed random vari-
able over the [0, 2π] interval. The optimal receiver for FSK signals with such a property in the
AWGN channel is the Correlation-Squaring Receiver [21][22]. Figure 2.3 shows the demodu-
lation of BFSK signals with this receiver. M-ary signals can be handled in the same way but a
linear increase in the complexity with the modulation level M is expected.
Figure 2.3. Demodulation of BFSK signals with the correlation-squaring receiver.
∫0
Τ (∙)2
Σ
∫0
Τ (∙)2
∫0
Τ (∙)2
Σ
∫0
Τ (∙)2
ΣOutputInput
cos2π(fc+fd)t
sin2π(fc+fd)t
cos2π(fc-fd)t
sin2π(fc-fd)t
CHAPTER 2 FSK Modulation and Demodulation 13
2.4.2 The Quadrature Detector
Although the correlation-squaring receiver yields superior performance, the hardware penalty
and extra design efforts make it a less attractive choice. A class of detectors commonly used in
FM demodulation are known as the quadrature FM detectors or frequency discriminators
[23][24]. The basic circuit is shown in Figure 2.4. The input signal Vin is usually hard limited to
suppress amplitude modulation. The LC tank and the capacitor C1 resonate at the carrier fre-
quency fc. The signal V1 is a phase-shifted version of Vin, with some amplitude difference. The
amount of phase shift in terms of the input frequency f can be shown to be
where is the relative frequency deviation, is the loaded Q of the network. At
the carrier frequency φ(fc) = 90°. As the input frequency deviates from the carrier, additional
phase leading or lagging is resulted. The multiplier acts as a phase detector or comparator. Its
output contains a low frequency portion which is proportional to the phase difference and a
high frequency portion which will be filtered out. Thus, the output voltage will be proportional
to the input frequency variation. This detector is also used in superheterodyne FSK receivers.
Depending on the modulation index, its error performance can be comparable to that of the
correlation-squaring receiver [20].
Figure 2.4. FM quadrature detector.
VinV1
R C
C1
L
LC Tank or
LPFVout
V2
Ceramic Discriminator
φ f( ) 1 ξ+ξ 2 ξ+( )Q-------------------------atan=
ξf fc–
fc-----------= Q R
ω0L----------=
CHAPTER 2 FSK Modulation and Demodulation 14
2.4.3 The Digital Phase Comparator
The methods stated above operate at certain carrier frequencies. In a direct-conversion FSK
receiver, new detectors must be invented to accommodate the zero-IF. One such device was
presented by I.A.W. Vance in [5] and its simplified diagram is depicted in Figure 2.5. From the
discussion in the previous sections, it is clear that the DFF here works as a phase comparator
which detects the rotation direction of the phasor. The accuracy can be further improved with a
balanced structure [6].
2.5 ZIFZCD and ZCI
Vance’s FSK receiver and its variants detect only the phasor direction and are thus not applica-
ble to M-ary systems such as the FLEX. To extract the speed information, a straightforward
way is to count the zero-crossings symbol by symbol. But from (2.5) we know that as the mod-
ulation index becomes smaller, the number of zero crossings decreases. This will definitely
hurt the error performance. E.K.B. Lee et al. [14][25] discovered a simple method to compen-
sate for the loss. The idea is to generate more zero-crossings in the given symbol interval by
introducing more channels. As shown in Figure 2.6, with 2 additional axes I1 and Q1, the num-
ber of zero-crossings is doubled as the phasor rotates across all the axes. These new channels I1
and Q1 can be created using another pair of quadrature mixers, with the local oscillator (LO)
phase shifted by 45° and 135°, respectively. But a more effective way is to derive the 2
required signals by simple addition and subtraction operations at the base-band:
Figure 2.5. Principle of Vance’s direct conversion radio paging receiver.
90°LO
I-Channel
Q-Channel
Limiter
LNA
D
CLK
Q
DFF
DATAAmplifiers
5
4
3
2
131
2 4
5
CHAPTER 2 FSK Modulation and Demodulation 15
(2.6a)
(2.6b)
(2.6)The 3 dB amplification can be cancelled out by a gain adjustment. But this is not necessary as
the next stage will be a hard-limiting block. More axes can be generated in the same manner.
This technique is termed Zero-Crossing Interpolation (ZCI) here. The total number of axes in
the phasor diagram is 2i+1 where i is called the interpolation or ZCI level. Equation (2.5) which
calculates the total number of zero-crossings per symbol should also be revised to
(2.7)
A demodulator with 1-level ZCI is shown in Figure 2.7 where two new signals I1 and Q1 are
generated. The demodulation is done in the digital domain by applying hard-limiting to all
these signals. Each of the I/Q pair is then passed to a zero-crossing pulse generator which is
very similar to the BFSK demodulator described in [6] except that the RC differentiator is
replaced by a digital difference block which consists of a delay element and a difference ele-
ment (subtractor), as shown in Figure 2.8. The output of the pulse generator is a series of
pulses with positive or negative polarities to indicate the phase relationship between the I and
Q inputs, one pulse for one zero-crossing. The pulse polarity is used for phasor direction detec-
tion and the number of pulses are counted for speed detection.
In the examples of 0.5 and 1.5 modulation indices CPFSK signals given in [14], the error
probability performances approach those of the LDI (limiter-discriminator with integrator-
dump filter) demodulators as the ZCI level increases.
sQ1 sQ sI– A φ t( )sin A φ t( )cos– 2A φ t( ) π4---+cos= = =
sI1 sQ sI+ A φ t( )sin A φ t( )cos+ 2A φ t( ) π4---+sin= = =
NZC 2 i 1+( ) an h=
CHAPTER 2 FSK Modulation and Demodulation 16
Figure 2.6. 1-level zero-crossing interpolation.
I
Q
I1
Q1
45°135°
Σ
DirectionDecision
Counter
Σ
I1
1Q
Zero-CrossingPulse Generator
Zero-CrossingPulse Generator
Q
SpeedDecision
Speed
DirectionI
Figure 2.7. The ZIFZCD with 1-level zero-crossing interpolation.
∆t Σ
Σ∆t
Σ
Q
I
Output
Figure 2.8. The zero-crossing pulse generator.
CHAPTER 3System Modeling and Circuit Requirements
The ZIFZCD discussed in the last chapter is a novel digital M-ary FSK demodulator for direct-
conversion receivers. Before using it in a real system, a number of issues are to be resolved.
This chapter studies the system modeling of the direct-conversion FLEX paging receiver
with ZIFZCD. Official standards issued by the Hong Kong Office of Telecommunications
Authority (HKOFTA) [26] and the Ministry of Post and Telecommunications of China [27] on
radio receivers for public paging service are applied to the model to derive circuit requirements
of the front-end blocks. Issues such as gain, nonlinearity and noise will be examined.
3.1 The Receiver Model
A high level model of the direct-conversion receiver working in the AWGN channel is shown
in Figure 3.1. We first assume the RF section is ideal so that the noise free signal can be
Figure 3.1. The receiver model. The demodulator is shown in Figure 2.7.
90 LOLNA
demodulator
nonlinearity
nonlinearity
Noise FreeRF Signal
~
r tQ( )~
r tQ( )
n tS( )
n tC( ) r tI( )
r tI( )
17
CHAPTER 3 System Modeling and Circuit Requirements 18
directly down-converted to the base-band quadrature components without distortion. The cor-
responding base-band Gaussian noise terms are added in at the output of the mixer pair. Each
of the I and Q signals is then passed to a polynomial block to model the distortion introduced
by the RF front-end. Finally the channel selection is done by a 11th order Chebyshev filter pair.
Neglecting the high frequency components, at the input of the polynomial block, we have
(3.1a)(3.1b)(3.1)
where nc(t) and ns(t) are the equivalent base-band components of the band-limited input noise.
These signals are amplified and distorted by the polynomial block which has the function of
(3.2)
where x(t) and y(t) are the input and output signals respectively; a1, a2 and a3 are constant gain
factors. The second and third order input intercept points of the front-end are approximated by
(3.3a)
(3.3b)
(3.3)in linear scale. When referred to the 50Ω resistance, their more frequently used dBm equiva-
lents are
(3.4a)
(3.4b)
(3.4)
3.2 Official Specifications
The HKOFTA has defined 5 parameters for very high frequency (VHF) public radio paging
receivers as the minimum performance requirements:
1. reference sensitivity,
2. spurious response rejection,
rI t( ) A φ t( )cos nc t( )+=rQ t( ) A φ t( )sin ns t( )+=
y t( ) a1x t( ) a2x2 t( ) a3x3 t( )+ +=
IIP2a1
a2
----≈
IIP343--- a1
a3
----≈
IIP2 10 10 a1
a2
----2
log=
IIP3 10 1043--- a1
a3
----× log=
CHAPTER 3 System Modeling and Circuit Requirements 19
3. desensitization,
4. intermodulation response rejection, and
5. radiated spurious emissions.
These are originally defined for the POCSAG system. However, as standards for the paging
service, they should apply equally to the new system. As specifications 2 and 5 are more cir-
cuit-level related issues and can be satisfied with careful circuit design and layout, only the
other three are included in this high level simulation.
By definition, the reference sensitivity is the field strength surrounding the receiver antenna
and is 3 dB above the minimum value required for a successful calling rate of 80%. The equiv-
alent BER for the 80% successful calling rate is 3% in the POCSAG system [28]. In our simu-
lation, we used 1% BER as the borderline and defined the sensitivity as the minimum input
signal power delivered to the LNA to produce this BER. Therefore, the reference sensitivity
and the sensitivity are two related terms with different meanings here. Given the field strength
to calculate the amount of power available for the LNA, one needs to know the efficiency and
the effective aperture of the antenna as well as the carrier frequency [29]. The conversion prob-
lem will be discussed in the next section.
To measure the desensitization, an un-modulated signal which is at least one channel away
from the nominal operating frequency is introduced as the interference. The desired signal
level is adjusted to yield a field strength that is equivalent to the reference sensitivity level
around the antenna. The desensitization is the difference between the interference and the
wanted signal in dB when the successful calling rate is reduced by the interferer to 80%. In the
simulation the interferer is exactly one channel away from the desired signal.
The intermodulation response rejection (IMRR) measurement is a little more complicated.
According to the HKOFTA specification, a testing signal at the nominal operating frequency f0
is first applied to yield a successful calling rate of 80%. Its level U is recorded. The signal fre-
quency is then changed to f0 + 2nfch where n = ±4 and fch is the channel spacing. At the same
time, an un-modulated carrier at f0 + nfch is introduced. The levels of these two signals are kept
the same and increased to a minimum value V at which a false decoder response is obtained.
The IMRR is V − U in dB. An alternative definition is formulated by the Ministry of Post and
Telecommunications of China. It also uses the signal level U as the reference. But unlike the
HKOFTA specification, the level of the first testing signal is increased by 3 dB from U while
CHAPTER 3 System Modeling and Circuit Requirements 20
its frequency is unchanged. Two equal level unwanted signals are then applied. One of them is
an un-modulated carrier at f0 + mfch (m = ±1, ±2 or ±4) and the other is an FM signal at
f0 + 2m fch. The FM signal is modulated by a 400 Hz sinusoid with a peak frequency offset of 3
kHz. The level of these two signals are increased to W at which the successful calling rate
drops to 80%. The IMRR is W − U in dB. Since the BER is not an intuitive indicator of the
decoder response, we chose the second method for the IMRR simulation.
3.3 Simulation Results
The simulation is carried out to verify the performance of the demodulator, especially the sen-
sitivity and the interference rejection ability, as well as to investigate the circuit requirements
on the RF front-end. It is done with an effort to follow the setup which is suggested in formal
measurements. Besides the specifications described in Section 3.2, impacts of I/Q phase mis-
match and LO frequency drift are also studied. The channel spacing is 25 kHz. Bandwidth of
the channel selection filter is about 8 kHz.
3.3.1 Sensitivity
As shown in Figure 3.2, for the demodulator with 2-level interpolation, the 1% BER level is
achieved at an ES/N0 ratio of about 13.5 dB when the overall front-end IIP2 and IIP3 are 11
dBm and −36 dBm, respectively. Since
(3.5)
where N0 = kT is the thermal noise spectral density; Ps is the signal power; RS = 3200 symbols
per second is the baud rate, we have
(3.6)
at room temperature (300°K). Assume the equivalent noise bandwidth B is 9 kHz, the signal to
noise ratio (SNR) is:
ES
N0
-----Ps RS⁄
N0
--------------=
Ps 10 kT RS⋅( )logES
N0
----- 30+ +=
125.3 (dBm)–≈
CHAPTER 3 System Modeling and Circuit Requirements 21
(3.7)
At the presence of interference components, as is the case in the desensitization and IMRR
testing, the signal to noise-and-interference ratio (SNIR) should also be kept above this level in
order to maintain the successful calling rate. Neglecting the noise contribution of the base-
band stages, the receiver sensitivity is only limited by the noise performance of the RF front-
end. To achieve 120 dBm sensitivity the front-end noise figure (NF) must therefore be as low
as 5.3 dB. This number will be used in the following section to determine the RF front-end
gain and noise budget. The maximum reference sensitivity required by the HKOFTA is 26
dBmV/m. Using the same antenna parameters given by [29] and assuming perfect LNA input
matching, this field strength is equal to −109 dBm signal power input to the LNA at 280MHz
nominal operating frequency and the equivalent receiver sensitivity is 3 dB lower, i.e. 112
dBm. Hence we have an 8 dB margin to make up for the errors resulted from our simple model.
It is noticeable that a continued increase in the level of interpolation will yield only dimin-
ishing improvement. The extra cost of hardware will probably not justify it.
Figure 3.2. BERs at different interpolation levels.
11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 1610
−3
10−2
10−1
No interpolation1−level interpolation2−level interpolation
Es/N0 (dB)
Bit
Err
or R
ate
SNRES
N0
----- 10RS
B-----
log+ 9 (dB)≈=
CHAPTER 3 System Modeling and Circuit Requirements 22
3.3.2 Desensitization
The same method that is used in the HKOFTA desensitization testing is applied in the simula-
tion. To provide the reference sensitivity, the ES/N0 ratio is set to 16.5 dB. An un-modulated
interference signal which is 65 dB higher than and one channel apart from the wanted one is
Figure 3.3. Effect of the 2nd order nonlinearity on desensitization.
Figure 3.4. Effect of the 3rd order nonlinearity on desensitization.
−18 −16 −14 −12 −10 −8 −6 −4 −2 0
10−3
10−2
10−1
No interpolation1−level interpolation2−level interpolation
16.915.013.412.110.99.9 19.4 23.0 29.0 ∞IIP2 (dBm)
Bit
Err
or R
ate
a2
−3
10−2
10−1
No interpolation1−level interpolation2−level interpolation
-103-104-105 -102 -101 0 a3
IIP3
-106
(dBm)-6.25-16.25-26.25 3.7 13.7 ∞-36.25
Bit
Err
or R
ate
CHAPTER 3 System Modeling and Circuit Requirements 23
introduced to verify the performance. Since the minimum desensitization requirement is 65
dB, a BER of 1% or lower is expected. Simulation results at 25 dB gain (a1 = 17.8) are
depicted in Figure 3.3 and Figure 3.4 in the format of BER versus a2 (IIP2) and a3 (IIP3) of the
front-end, respectively. The relationship between the intercept points and the coefficients a2, a3
is given in (3.4). Not surprisingly, the 2nd order distortion plays a critical role because of the
resultant low frequency components which fall into the base-band and therefore can not be fil-
tered out. As a result, the RF front-end must yield at least 11 dBm IIP2 to satisfy the desensiti-
zation requirement.
Figure 3.4 is plotted here as a comparison. One shouldn’t come to the conclusion that the
receiver is able to work at very poor IIP3’s. In fact, as the only interferer in this simulation is
an un-modulated carrier which is one channel away from the nominal, the 3rd order distortion
creates no in-band interference at all. This is different from the case of intermodulation
response.
3.3.3 Intermodulation Response Rejection
As described in Section 3.2, two unwanted signals are present at f0 + mfch and f0 + 2mfch respec-
tively, where f0 and fch are the nominal frequency and the channel spacing; m could be plus or
minus 1, 2, or 4. Figure 3.5 shows that the IMRR is about 58 dB, 3 dB higher than the specifi-
cation, with m= ± 1. Better results are obtained when the unwanted signals get farther.
The IMRR specification can be use to estimate the SFDR (spurious free dynamic range)
and required IIP3. As we already set the sensitivity to be −120 dBm, the 55 dB IMRR implies
55 + (−120) = 65 dBm interference level. If the equivalent noise bandwidth B is restricted to
9 kHz, with 5.3 dB NF the input referred noise floor is
(3.8)
The SFDR can be calculated by
(3.9)
Finally the IIP3 required to achieve this SFDR is
Nfloor 10 kTB( )log NF 30+ +=
129 (dBm)–≈
SFDR 65– Nfloor – 64 (dBm)≈=
CHAPTER 3 System Modeling and Circuit Requirements 24
(3.10)
This result is close to the −36 dBm value used in the simulation.
3.3.4 Phase Mismatch, Frequency Drift and Phase Noise
It turns out that the demodulator can withstand quite a large phase mismatch between the I and
Q signals. A 10° mismatch results in only about 0.1 dB degradation in the 12 to 16 dB ES/N0
range, as shown in Figure 3.6. Modern IC technology can reduce the mismatch to a much
lower level. At the same time, severe performance degradation is observed when the LO drifts
from the nominal carrier frequency. In Figure 3.7 a 300 Hz drift worsens the sensitivity by 0.25
dB. At the 280 MHz band, this drift translates to about 1 ppm frequency stability. Over the 15
to 35°C temperature range for normal condition test, this is very difficult, if not impossible, to
achieve without careful (and probably expensive) compensation. It is therefore necessary to
apply some kind of automatic frequency control (AFC) and/or adaptive demodulation
schemes. An AFC algorithm proposed in [7] demonstrated the convergence of the drift fre-
quency from 1 to within 1/10 of the symbol rate (about 3 kHz). Another consideration is the
receiver bandwidth. The 8 kHz bandwidth is not supposed to accommodate the drift. In a prac-
Figure 3.5. The IMRR is 58 dB when the unwanted signals are 1 and 2 channels above (m=1) or below (m=−1) the nominal, respectively. The meanings of m, W and U are defined in Section 3.2.
53 54 55 56 57 58 59 60 61 62 6310
−4
10−3
10−2
10−1
100
W − U (dB)
m=+1m=−1
Bit
Err
or R
ate
IIP332---SFDF Nfloor 33 (dBm)–≈+=
CHAPTER 3 System Modeling and Circuit Requirements 25
tical application, however, some allowance must be provided to alleviate the problem. The bot-
tom line is to maintain an acceptable sensitivity level. Phase noise, on the other hand, is usually
not a problem in paging receivers where crystal oscillators are commonly used. Ultra low
phase noise below −100 dBc/Hz can be achieved at a few hundred hertz [30]. Reciprocal mix-
ing at this level is completely negligible.
Figure 3.6. Sensitivity degradation due to I/Q phase mismatch.
Figure 3.7. Sensitivity degradation due to LO frequency drift.
12 12.5 13 13.5 14 14.5 15 15.5 16
10−2
10−1
Phase Mismatch 0o 10o 20o 30o 40o 50o
Es/N0 (dB)
Bit
Err
or R
ate
11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 1610
−3
10−2
10−1
100
LO drift = ±1KHz
±500Hz
±300Hz
Es/N0 (dB)
Bit
Err
or R
ate
0 Hz
CHAPTER 3 System Modeling and Circuit Requirements 26
3.3.5 RF Front-End Budget
The sensitivity and desensitization simulation provides important information for the system
planning. Once the overall noise and nonlinearity requirements have been determined, a bud-
get can be given for the front-end including the LNA and the mixer. The 5.3 dB overall NF
which is required to achieve the −120 dBm sensitivity is actually a very stringent number. The
LNA must provide enough gain to suppress the noise contribution from the following stages.
As an example, assume the LNA gain is 16 dB and the mixer NF is 15 dB, the LNA NF is then
given by
(3.11)
Where Ftotal and Fmixer are the noise factors of the front-end and the mixer; GLNA is the LNA
power gain in linear scale.
Although 4 dB NF may seem to be an easy objective, it must be justified with caution
because the designers may want the LNA to be differential. In a superheterodyne receiver the
single-ended LNA is desired because of its superior NF. However, for a direct conversion
receiver like the one under discussion, the differential architecture may be more appropriate for
its excellent cancellation of the 2nd order distortion. In the case of low source impedance, the
equivalent input noise voltage of a differential pair is 3 dB higher than a single common emit-
ter amplifier when their transistors are biased at the same current [31]. The doubled equivalent
input noise power won’t push the NF by the same amount but its contribution is significant. A
straightforward calculation shows 1.4 to 1.8 dB increase in the NF when the original single-
ended value is somewhere between 2 and 3 dB. Taking other important factors like the nonlin-
earity, the input matching and the power consumption into account, the LNA gain and noise
budget is still feasible but may require extra efforts. We then assign 9 dB gain to the mixer so
that an overall gain of 25 dB could be obtained from the RF section. The 9 dB assignment is
somewhat arbitrary and may include a buffer stage.
Having done the gain and NF budget, we can determine the nonlinearity distribution by
using the polynomial approximation. Constant overall IIP2 and IIP3 curves of the front-end are
given in Figure 3.8 and Figure 3.9. The x and y variables are the intercept points of the LNA
and the mixer, respectively. With typical LNA and mixer IP values, the system nonlinearity
NFLNA 10 FtotalFmixer 1–
GLNA
---------------------– log 4.2 (dB)≈=
CHAPTER 3 System Modeling and Circuit Requirements 27
requirements should be satisfied without any difficulty. Table 3.1 summarizes the planning.
Some design margin has been deliberately made available.
Figure 3.8. Constant overall IIP2 curves.
Figure 3.9. Constant overall IIP3 curves.
10 15 20 25 30 35 4026
28
30
32
34
36
38
40
Overall IIP2 14 dBm 12 dBm 11 dBm 10 dBm
IIP2 of the LNA (dBm)
IIP
2 of
the
Mix
er (
dBm
)
−40 −35 −30 −25 −20 −15 −10−25
−20
−15
−10
−5
0
5
10
Overall IIP3 −26 dBm −30 dBm −36 dBm
IIP3 of the LNA (dBm)
IIP
3 of
the
Mix
er (
dBm
)
CHAPTER 3 System Modeling and Circuit Requirements 28
Table 3.1 RF Front-End Budget.
LNA Mixer Overall
Gain (dB) 16 9 25
NF (dB) 4 15 5.2
IIP2 (dBm) ≥ 25 ≥ 30 ≥ 12
IIP3 (dBm) ≥ −26 ≥ −12 ≥ −30
CHAPTER 4Circuit Design I
A prototype 4FSK direct-conversion receiver is designed and built on a 0.35µ CMOS process.
The design details are presented in this and the next chapter. This chapter starts with an over-
view of the receiver. A brief introduction of the RF front-end follows. The rest of this chapter
focuses on the AGC and filtering circuitry. Finally the problem of DC offset and flicker noise
is discussed.
4.1 Overview
The direct-conversion receiver diagram is shown Figure 4.1. Differential structures are used
throughout the design. To minimize the DC offset induced by the self-mixing process, har-
monic mixers are proposed to replace the conventional ones. For this reason, the two LO sig-
Figure 4.1. Block diagram of the receiver.
45°RF
Input
Demod.LO
LNA
HarmonicMixer LPFAGC
29
CHAPTER 4 Circuit Design I 30
nals driving the mixer pair have 45° phase difference rather than the 90° quadrature phase used
in standard direct-conversion structures.
The automatic gain control (AGC) circuit makes use of the differential variable MOS resis-
tors to construct the variable gain amplifier (VGA). The signal level is sensed by a peak detec-
tor and compared with a reference voltage. The control circuitry adjusts the VGA gain to
minimize the voltage difference.
The low pass filter is a cascade of a biquad and a 5th order gyrator-C filter. The gyrator fil-
ter simulates an LC ladder by using gyrators in place of inductors. LC ladder filters have low
sensitivity to parameter variations and good stability at high orders. These nice properties are
inherited by the gyrator filter. However, another characteristic, the 6 dB loss, that is not so
desired is also retained. This results in a higher input-referred noise level. The biquad provides
not only the filtering function but a certain amount of gain as well and thus reduces the noise.
Unfortunately only the gyrator filter is included in this fabrication due to the large amount of
capacitance required to implement the continuous-time active RC biquad.
Output signals of the low pass filters are processed by the demodulator which has been
introduced in Section 2.5 and is to be further discussed in Chapter 5.
4.2 LNA and Mixer
The RF front-end is designed by Mr. Louis Tsui (the LNA) and Mr. Zhaofeng Zhang (the
mixer) of the UMAN research group. Here only a very brief introduction is provided. For a
more specific and detailed treatment, please refer to their own publications [32] and future dis-
sertations.
4.2.1 The Differential LNA
To minimize the substrate coupling and the second order distortion which creates in-band error
components and corrupts the signal, the LNA is designed to be differential. The differential
input signal can be obtained by re-designing the input matching network which selects the sig-
nal of the desired band from what is collected by the loop antenna and delivers it to the LNA.
The cascoding structure improves the reverse isolation and the frequency response. When
directly connected to the mixer, the input capacitance of the latter resonates with the inductors
CHAPTER 4 Circuit Design I 31
LL at the desired frequency. The resistance RL sets the output common mode voltage to an
appropriate value. The inductor LS helps improve the common mode rejection ratio (CMRR).
4.2.2 The Harmonic Mixer
Unlike conventional mixers, a harmonic mixer utilizes one of the LO’s harmonics to mix down
the RF signal and is theoretically free of self-mixing, the main DC offset contributor. It has
been reported that a bipolar harmonic mixer is able to suppress the equivalent self-mixing
related DC offset to the noise level [33]. However, due to the much higher flicker noise and
other performance imperfections such as device mismatch and low transconductance, a CMOS
equivalent is more difficult to design and has not been found in the literature.
The CMOS harmonic mixer to be introduced here is shown in Figure 4.3 where the 2nd
order harmonic of the LO is generated by the MOS transistors M3 and M4 in their square-law
operation. The fundamental and odd harmonics are cancelled out at the node X. The desired IF
component is centered at |fRF − 2fLO| where fRF and fLO are the frequencies of the RF carrier and
the LO signal, respectively. About 37.5 dB offset cancellation is achieved and the input-
referred offset level is suppressed close to the noise level.
As the noise currents of M3 and M4 are combined at X and become a common mode sig-
nal, the only way they can appear at the output is through a modulation by the RF signal. While
part of their wide-band noise is down-converted to the base-band, the flicker noise is up-con-
Figure 4.2. The differential low noise amplifier.
LS
LLLL
RL
Bias
in+
in-
Vdd
out-
out+
CHAPTER 4 Circuit Design I 32
verted and will be rejected by the LPF in the following stage. Therefore, most of the noise is
contributed by the RF part, i.e. the transistors M1 and M2. To minimize the flicker noise, the
current injection technique is used in addition to the large transistor size. The injected current
I0 lowers the bias currents of M1 and M2 and drives them to the moderate or even weak inver-
sion region where the flicker noise coefficient can be orders of magnitude lower than that of
the same transistor working in the strong inversion region. This has be observed from the mea-
surement and is consistent with [34]. More than 20 dB noise figure improvement is achieved.
The overall noise figure at 10 kHz is about 24.5 dB.
4.3 VGA and AGC
In some FSK receivers like those given by [5] and [6], gain control may not be necessary
because most of the gain is provided by the limiting amplifier after low pass filtering and the
circuits preceding the filter stage are safe from overloading or saturation. Nevertheless, when
more gain is needed to boost the signal and suppress the noise contributed by the mixer and the
active channel selection filter, an AGC stage becomes essential to satisfy the dynamic range
and/or intermodulation requirements, as is the case in this design. Also, AGC prevents signal
clipping which is not allowed in the ZCI operation described in equation (2.6).
The AGC loop is shown in Figure 4.4. It consists of a VGA, a peak detector, a Gm-C inte-
grator and a level shifting network. The output signal level is sensed by the peak detector and
compared with a reference voltage. The difference is accumulated at the integrator which
Figure 4.3. The CMOS harmonic mixer with current injection.
I0RL RL
LO-LO+
RF+ RF-
Vdd
M3 M4
M2M1X
IF- IF+
CHAPTER 4 Circuit Design I 33
serves as the loop filter. The VGA gain is adjusted by the resultant voltage Vc via the level
shifting network to minimize the difference between the peak detector output Vpk and the ref-
erence voltage Vref and hence to keep the output level constant.
4.3.1 The Variable Gain Amplifier
The VGA is constructed as an inverting amplifier whose gain can be adjusted by tuning the
two differential variable resistors. The major advantage of this structure is that the gain of the
VGA is virtually independent of process parameters and thus immune to the substrate cou-
pling. Assuming (1) all the input and output nodes are biased at a common mode voltage Vcm;
(2) the two input nodes of the operational amplifier (opamp) holds at Vcm due to the virtual
ground effect; (3) all transistors in a differential variable resistor have the same process and
geometric parameters and work in the linear region, equivalent value of the differential vari-
able resistor can be derived by equating the gains of the two amplifiers in Figure 4.5. Neglect-
ing the resistance R0 for the time being, the drain current of M1 is
Similar expressions can be written for the other 3 transistors. The current Id1 + Id3 will be forced
through the top Rf and results in a voltage drop:
Figure 4.4. The AGC loop.
PeakDetector
Vc2 Vc3 Vc1 Vc4Vpk
Vref
OPAMP
Differential Variable Resistor
in-
in+
out+
out-
VcLevel Shifting Network Gm
Id1 µCoxWL----- V2 Vcm– Vth–( )vin
+ 12--- vin
+( )2–=
CHAPTER 4 Circuit Design I 34
Similarly, we have
The output voltage can then be expressed as
(4.1)
The gain can be easily shown to be
(4.2)
Therefore,
(4.3)
A negative (V2 − V1) value just implies a switched connection of the input terminals to the
opamp input nodes rather than a negative resistance. When the differential variable resistor is
used to provide the feedback, it yields the same equivalent value. Finally, gain of the VGA
shown in Figure 4.4 is
(4.4)
which is, to the first order, independent of process variations and substrate coupling.
The equivalent resistance Req given by (4.3) provides sufficient information for gain esti-
mation when the VGA is driven by a pure voltage source. However, as an intermediate stage of
a cascaded chain, its loading effect must be examined more carefully. This is necessary not
only because the finite input resistance can load down the gain of the preceding stage but also
because the input resistance has an expression which is different from Req. Under the same set
of assumptions we made at the beginning of this section and still neglecting R0, the resistance
looking into the positive input node of Figure 4.5 is
Id1 Id3+( )Rf vout-–=
Id2 Id4+( )Rf vout+–=
vout vout+ vout
-– Id1 Id3 Id2– Id4–+( )Rf= =
vout
vin
-------vout
+ vout-–
vin+ vin
-–--------------------- Rf µCox
WL----- V2 V1–( )⋅= =
Req1
µCoxWL----- V2 V1–( )
---------------------------------------=
GVc3 Vc2–Vc4 Vc1–--------------------=
CHAPTER 4 Circuit Design I 35
(4.5)
For differential input signals, vin+ = vin
− = vin/2, the total input resistance is
(4.6)
where vDSsat = (V1+V2)/2 − Vcm − Vth. In the case of small input signals, Rin depends only on vDSsat
and will be kept constant if V1 and V2 are differential to each other. This can be easily done
with the control circuitry which will be discussed in the next section.
The linear resistor R0 is used to improve the linearity. It takes part of the input voltage drop
such that the MOS resistors stay in the linear region even at relatively large inputs. An interest-
ing property of this linear resistor is that, when applied in both the input and the feedback
branches as shown in Figure 4.4, it doesn’t change the small signal gain. This can be derived
similarly as equation (4.4).
The OPAMP is of the simple two stage type with 80 dB small signal gain at DC.
4.3.2 The Control Circuitry and VGA Gain
Gain of the VGA is tuned by the control circuitry which is formed by the peak detector, the
Gm-C integrator and the level shifting network.
Figure 4.5. The MOS differential variable resistor (a) and its equivalent (b).
Rin+1
vin+∂
∂ Id1 Id2+( )-------------------------------- 1
2µCoxWL----- 1
2--- V1 V2+( ) Vcm– Vth– vin
+–
-------------------------------------------------------------------------------------------= =
Rin1
µCoxWL----- vDSsat
vin2
4vDSsat
---------------–
---------------------------------------------------------=
1V 2V
R f
R0
vin+
cm
R f
vin-
cm
vout+
cmV
vout-
cmV
cmV
R0
M2
M3
M4
M1
R f
R f
R eq
R eq
voutin
(a) (b)
CHAPTER 4 Circuit Design I 36
The peak detector is shown in Figure 4.6 [35]. When the voltage level of either input node
is lower than Vpk, the difference ∆V is sensed by the corresponding transconductance amplifier
and a current (gm ∆V - I0) is generated to discharge the capacitor C toward the lower level.
When both inputs are above Vpk, C is charged by the current source I0 toward Vdd. Thus this is
a negative peak detector with different tracking speed for positive and negative input transi-
tions. Consequently, the attack time and the release time of the AGC are also different, as will
be seen later.
The difference between Vpk and the reference voltage Vref is passed to the Gm-C integrator
which works as the loop filter. The resultant signal Vc is the control voltage of the VGA. To
obtain proper control voltages for the 2 differential variable resistors, a level shifting network
formed by 4 PMOS source followers is used, which tunes (Vc3 − Vc2) and (Vc4 − Vc1) in the
opposite directions while keeping (Vc3 + Vc2) and (Vc4 + Vc1) constant. In this way, the gain G
given by (4.4) can be adjusted to minimize the difference between Vpk and Vref whereas the
equivalent input resistance Rin will be fixed, and so does the gain of the preceding stage.
Figure 4.6. The peak detector.
Figure 4.7. The level shift network.
gm
gm
I 0
inV
inVpk
C
Vdd
Vc1
Vc3
Vc
V1+∆
V2+∆
Vc2
Vc4
V1+∆
V2+∆c-
kV
c+
kV
Source FollowersAttenuating
Buffer
+
_
Vc4
Vc1Vc2
Vc3V∆ 0
_
ckV
c+
kVV∆ 1
V∆ 2
CHAPTER 4 Circuit Design I 37
The source followers shift the attenuated control voltage kVc by either ∆V1 or ∆V2, depend-
ing on the transistors’ size, as shown in Figure 4.7. Here k is the gain of the attenuating buffer.
As a result,
(4.7)
And the gain becomes
(4.8)
where ∆V0 = ∆V2 − ∆V1. If Vc is small enough, i.e., Vpk is close to Vref, the gain can be approx-
imated by an exponential function of Vc:
(4.9)
Figure 4.8 shows the simulated and calculated G(Vc) − Vc curves with k ≈ 0.19, ∆V0 ≈ 435mV.
When the control voltage gets larger (positively or negatively), the calculated gain changes
much faster than the simulated value as the effective k, the gain of the attenuating buffer, starts
to saturate. This effect actually helps keep the gain linear in the dB domain.
4.3.3 Performance
The dB-linear gain control characteristic of the VGA is an essential requirement for a constant
loop settling time. In Figure 4.9 the loop response to a 2 kHz sinusoidal input decreasing from
2 Vpp by 6 dB every 10 ms is plotted. The settling time is approximate 8 ms and virtually inde-
pendent of the input signal level. This stays valid until the input goes beyond the dB-linear
region. Nevertheless, the situation is very different when the input signal has an increasing
level due to the unidirectional tracking characteristic of the peak detector. Figure 4.10 shows
the loop response to an signal whose amplitude is initially 1mV and has two 25 dB rising steps
Vc1 kVc+ ∆V1+=
Vc2 kVc - ∆V1+=
Vc3 kVc+ ∆V2+=
Vc4 kVc - ∆V2+=
G Vc( ) Vc3 Vc2–Vc4 Vc1–--------------------
∆V0 kVc+∆V0 kVc–------------------------
1kVc
∆V0
---------+
1kVc
∆V0
---------–-------------------= = =
G Vc( ) e2k
∆V0
----------Vc
≈
CHAPTER 4 Circuit Design I 38
at 5 and 10 ms respectively. At the first rising step, the output signal is small such that its neg-
ative peak is higher than the reference voltage, the loop settles very quickly. But at the second
step the output is so large that it is saturated. The peak detector output Vpk drops to its mini-
mum level almost immediately. This sets the VGA gain to the minimum and results in a very
small output. Now Vpk starts to increase at a slow speed as the capacitor C of the peak detector
is being discharged by the small current source I0 and so does the output signal. As Vpk
Figure 4.8. VGA gain as a function of the control voltage Vc.
Figure 4.9. Response of the AGC to a 2 kHz sinusoidal input decreasing from 2 Vpp by 6 dB every 10 ms.
−2 −1.5 −1 −0.5 0 0.5 1 1.5 2−20
−15
−10
−5
0
5
10
15
20
Vc [V]
G(V
c) [d
B]
Simulated Calculated
0 5 10 15 20 25 30 35 40 45 50−1
0
1
INP
UT
[V]
0 5 10 15 20 25 30 35 40 45 50−1
0
1
OU
TP
UT
[V]
0 5 10 15 20 25 30 35 40 45 50−2
0
2
Vc
[V]
TIME [ms]
CHAPTER 4 Circuit Design I 39
approaches Vref, the control voltage Vc at the integrator output starts to increase and finally
flips. The VGA gain and the output signal are then increased with Vc at a higher speed. There-
fore, the attack time or the settling time for a rising step of the signal amplitude can be reduced
by:
• choosing a smaller reference voltage which allows a higher output level,
• optimizing the VGA gain setting such that for the largest possible input the desired
output level is achieved at the minimum possible gain, and
• using larger I0/C ratio in the peak detector if possible;
At large input levels, the MOS transistors will be driven out of the linear region. And the
feedback path is changed to a feedforward path. To prevent this from happening, linear resis-
tors R0 is added to the differential variable MOS resistors. It improves the linearity greatly and
in theory does not change the gain. But it turns out that, by doing this, the opamp noise is
amplified by a large number which is approximately proportional to R0×µCOXW/L. Besides, the
cross-coupled input and feedback structure also degrades the noise performance. The simu-
lated input-referred thermal noise voltage density is about 250 nV/√Hz when the gain is about
18 dB. This is even comparable to that of the active low pass filter to be discussed in the next
Figure 4.10. Response of the AGC to a 4.8 kHz sinusoidal input increasing from 1 mVpp by 25 dB at 5 ms and 10 ms respectively.
0 5 10 15 20 25 30 35 40 45 50−0.4
−0.2
0
0.2
INP
UT
[V]
0 5 10 15 20 25 30 35 40 45 50−1
0
1
OU
TP
UT
[V]
0 5 10 15 20 25 30 35 40 45 50−2
0
2
Vc
[V]
TIME [ms]
CHAPTER 4 Circuit Design I 40
section. To lower the noise level, the R0COXW/L product should be minimized. In fact, increas-
ing the transistor length L (while W is fixed) results in similar effects as increasing R0, i.e. bet-
ter linearity and higher noise level. Although the linearity improving ability of the former is
not as powerful as the latter, the resultant noise level is moderate and acceptable. With R0 = 0
and W/L = 10µ/20µ, simulation shows about 50 nV/√Hz input-referred thermal noise and less
than 0.1% total harmonic distortion at about 600 mVpp output. The noise can be further reduced
by inserting a low noise fixed gain amplifier between the mixer and the AGC.
In the current design, as expected, very good linearity is achieved. At 800 mVpp output
level (the input signal can be over 2 Vpp), the simulated total harmonic distortion is less than
0.1%. Measurement data is presented in Chapter 6.
Another disadvantage of the AGC circuit is the dependency of the bandwidth on its gain.
This is due to the reduced effective feedback when the gain is increased. It is not a concern in
this design as the signal bandwidth is just at the order of 10 kHz.
4.4 Low Pass Filters
Being able to implement the filtering function on chip is essential to achieve the miniature of
electronic systems, especially the radio receivers due to the selectivity requirement. In the
audio to video frequency range, different techniques are available for the realization of the
same transfer function. Among them, switched-capacitor (SC) filters and Gm-C filters are of
the most popular. SC filters have gained the reputation of very high precision and stability over
process and environment variations and can be found in many receiver designs for channel
selection [35][36]. Without the need of clocking and anti-aliasing filtering, continuous-time
filters, especially the Gm-C type for its simplicity, also find their places in various applica-
tions. However, their transfer characteristics are defined by the absolute process or circuit
parameters (i.g. the transconductance of the Gm-C filter) and can therefore vary significantly
from process to process and from time to time. The remedy is an automatic tuning system
which is able to adjust the circuit parameters until they are locked to a certain reference [37].
The tuning loop usually consists of the reference source, a phase or other types of comparator,
a loop filter and a duplicate of the whole filter or a core element of it such as a resonator. The
overhead could thus be considerable.
CHAPTER 4 Circuit Design I 41
Besides the physical implementation, a logical, or “high-level”, synthesis approach must be
chosen to realize high-order filters. The most simple way is to decompose the transfer function
down to a product of several second-order ones (including the special case of one first-order
function when the filter is odd-order) and map each of them to a second-order building block,
or biquad in short. Cascading of these biquads restores the original high-order function. As
biquads are well understood and very easy to tune, this method offers great simplicity and flex-
ibility and is suitable for low to medium order systems. For very high order systems, however,
the pass-band characteristic could be too sensitive to component variations. Another approach
which is also based on the biquad technique is known as the multi-loop feedback method. Bet-
ter pass-band sensitivity is achieved by introducing coupling between biquads as the feedback
is applied. One example is the well known leapfrog structure. The best sensitivity performance
is found in filters belong to the LC ladder family. This property is preserved in active filters
which simulate LC ladders by element substitution or using the signal flow graph approach.
When compensated for temperature variations, it allows the automatic tuning system to be
omitted at the audio frequency band in some applications. The gyrator-C filters used in radio
paging receivers [6][38] fall into this category.
In this project, the channel selection is performed mainly by a 5th order gyrator-C filter. An
active RC biquad is also designed to compensate the 6 dB loss due to the matching property of
the LC ladder and to reduce the total input-referred noise and improve the dynamic range.
Nevertheless, as the process does not support large linear resistors and it is also not practical to
utilize MOS resistors, the total capacitance required for the cut-off frequency becomes too
large. Therefore, only the gyrator filter is included in the fabrication.
4.4.1 The Gyrator and Gyrator-C Simulated Inductors
A gyrator is a two-port network with the Y-parameters in the form of
(4.10)
This can be realized by connecting two transconductance amplifiers in a feedback manner as is
shown in Figure 4.11. It is straightforward to show that, with a grounded capacitor, a pure
inductive impedance of a grounded inductor or a floating one can be formed using one or two
Y[ ]0
gm1–
gm2
0=
CHAPTER 4 Circuit Design I 42
gyrators, respectively. The diagrams are depicted in Figure 4.12. In both cases the same imped-
ance is obtained:
with the equivalent inductance of
(4.11)
The active gyrator-C filter is formed by simply replacing the inductors of an LC ladder with
the simulated ones.
4.4.2 Simulation of The LC Ladder
The LC ladder with normalized parameters can be found in the design tables [40]. Frequency
scaling and impedance scaling are performed to de-normalize the component values. Given the
transfer characteristics, the capacitance is proportional to the termination resistance R0 while
the inductance is inversely proportional to it. In the gyrator-C implementation, for easy biasing
and layout, identical Gm cells with the differential transconductance gm are used. The termina-
tion resistors are also simulated by two Gm cells connected in the unity feedback form:
Figure 4.11. The gyrator and its small signal equivalent circuit.
Z s( ) sC
gm2
-----=
L C
gm2
-----=
V1
m1g
m2g
I 1I 2
V2
g Vm2 2 g V
m1 11V V2
I 2I 1
CHAPTER 4 Circuit Design I 43
Figure 4.12. Simulation of inductors using gyrators and capacitors.
Figure 4.13. The 5th order gyrator-C elliptic low pass filter and its LC ladder prototype.
gm
gm
C
VI
L
gm
gm
gm
gm
2V
V1
L
VC
CI
I
(a) Grounded Inductor
(b) Floating Inductor
in out
R0
R0
L 2 L 4
C1C2 C4C3 C5
outin
2R01gm
-----=
CHAPTER 4 Circuit Design I 44
Note that the differential structure doubles the termination resistance. Another Gm cell is
inserted at the input port to provide the Norton equivalent of the source termination.
Simulation of the two floating inductors is given in (4.11). The required capacitance is also
proportional to R0. Consequently, to minimize the capacitance area, it is desirable to use a large
termination resistance and thus a small gm. However, this can cause problems such as the
increased input referred noise. The differential transconductance value used here is 2.5 µS,
which is equivalent to a 5 µS single-ended gm or 200 kΩ R0.
Poly to poly capacitance is used. For a grounded capacitor like C1, C3 or C5, the bottom
plate parasitic capacitance is balanced by splitting the capacitor into halves and connecting
them in the opposite polarity. Parasitics of the floating capacitors also appear at the nodes of
the grounded ones. Thus, all parasitic capacitance can be absorbed by the grounded capacitors.
The total capacitance is about 1 nF.
4.4.3 The Linearized Transconductor
As the simulated inductance is directly related to the transconductance value, it is critical to
keep it constant over the whole input range. In other words, the transconductor should be as
linear as possible. Source degeneration is a simple yet effective linearization technique com-
monly used in amplifier designs. In a differential structure, it can be done by connecting a
resistor or MOS resistor between the source nodes of the input devices which are biased by two
identical but separate current sources. A modified scheme is shown in Figure 4.14 where the
degeneration is provided by two MOS transistors with their source and drain terminals con-
nected in the usual MOS resistor way but their gates connected to the input nodes [39]. Tran-
sistors Mc1 and Mc2 operate in the linear region to stabilize the common mode output.
For a small input signal, M21 and M22 are in the linear region and the whole circuit
behaves similarly to the conventionally degenerated one. Further increase of the input signal
amplitude will drive one of these two transistors into the saturation region and result in a dif-
ferent I-V transfer characteristic. Under this condition, additional output current is supplied by
M21 or M22 to compensate the transconductance degradation due to the non-saturate opera-
tion of M11 and M12. By sizing the transistors correctly, the large signal transconductance can
be kept very close to the small signal transconductance until no more additional current is
available. Authors of [39] have shown that the best linearity performance can be achieved
CHAPTER 4 Circuit Design I 45
when the ratio (µCoxW/L)1/(µCoxW/L)2 is around 7. Here subscripts 1 and 2 denote transistors
M11/M12 and M21/M22, respectively. With the ratio set to be 6.7 and VGS−Vth > 1 V, gm varia-
tion of ±2.5% over 80% output current range is typical.
4.4.4 Simulated Performance
In Figure 4.15, the differential output current and the transconductance of the linearized
transconductor are given. The nominal gm value is 2.5 µS. Over 800 mV differential input volt-
age range, the transconductance variation is within 1.5%.
Frequency response of the filter is given in Figure 4.16, together with that of the LC ladder
prototype. THD at 700 mVpp output is less than 1%.
The noise performance is shown in Figure 4.17. The pass-band output thermal noise spec-
tral density is between 300 to 400 nV/√Hz. When referred to the input, due to the 6 dB loss, it
is increased to about 700 nV/√Hz or −3 dBµV/√Hz. Although this is comparable to the −4
dBµV/√Hz input spectral noise voltage density reported in the similar work using the bipolar
technology [41], it is still a relatively high value even without the effect of the flicker noise. To
prevent the filter noise from dominating the overall receiver NF, the signal must be boosted
before it is filtered. If the front-end NF is 5 dB, more than 60 dB gain is required to suppress
the filter noise such that the NF degradation is about 1 dB. In this case, AGC becomes an
essential element to preserve the dynamic range.
Figure 4.14. The linearized transconductor (a) and its biasing circuit (b).
Vdd
out-M12M11
M21
M22
Mp1 Mp2
Mc2Mc1
MN1 MN2
out+
in-in+
bias2
bias1Iref
bias2
bias1
Vdd
(a) (b)
CHAPTER 4 Circuit Design I 46
4.5 The DC Offset Problem
In Chapter 1 we have a brief introduction of the DC offset problem. Besides the self-mixing
effect, the offset is also originated from other sources such as the device mismatch. Although
its impact can be minimized with the help of specific circuit design and layout techniques, mis-
match itself can never be eliminated. The input-referred offset voltage of a simple differential
pair with resistive load is
Figure 4.15. Differential output current and transconductance of the linearized transconductor.
Figure 4.16. Frequency response.
0
200n
400n
600n
800n
1u
1.2u
1.4u
1.6u
1.8u
2u
2.2u
2.4u
2.6u
-2u
-1.5u
-1u
500n
0
500n
1u
1.5u
2u
-1 -500m 0 500m 1
g m [
S]
I OU
T [
A]
Input Differential Voltage [V]
5 10 15 20 25 30−120
−100
−80
−60
−40
−20
0
Frequency [kHz]
|H(f
)| [d
B]
LC ladderGyrator−C
CHAPTER 4 Circuit Design I 47
(4.12)
A 10 mV level can be easily achieved. When a current mirror is used as the active load, the
equation will be
(4.13)
Here the subscript “L” denotes the loading devices. The additional threshold voltage mismatch
term and the usually worse (compared to the resistive load) active load dimension mismatch
term result in an even larger offset component.
In some applications the offset can be removed by means of AC-coupling. Unfortunately
this is not affordable for modulation schemes which contain significant DC and low frequency
energy. Specifically designed circuits are then required for the task of offset cancellation. Most
of them can be classified into two categories. The first kind of circuits work in a two-phase
manner. During the sampling phase, the offset is measured and memorized. There then comes
the cancelling phase during which the stored offset is subtracted from the signal. Most auto-
zeroing circuits belong to this class. Circuits in the second category avoid DC offset and low
frequency noise by up-converting the signal to a safer frequency band, amplifying it, and
down-converting it back to the base-band for further processing. Both solutions demand con-
Figure 4.17. Thermal noise
5 10 15 20 25 3010
−8
10−7
10−6
10−5
Frequency [kHz]
Output−Referred
Input−Referred
Noi
se V
olta
ge [
Vrm
s / H
z½]
VOS
VGS Vth–2
--------------------- ∆RL
RL
--------- ∆ W L⁄( )W L⁄( )
---------------------+ ∆Vth–=
VOS
VGS Vth–2
--------------------- ∆ W L⁄( )L
W L⁄( )L
----------------------- ∆ W L⁄( )W L⁄( )
---------------------+gm( )L
gm
------------ ∆Vth( )L– ∆Vth–=
CHAPTER 4 Circuit Design I 48
siderable amount of complexity and will inevitably raise the white noise floor. These are the
price to pay for the improved performance as the DC offset and flicker noise are now rejected.
But in many applications it can cost so much that people would choose the more conventional
and more mature superheterodyne architecture rather than direct-conversion. Moreover, as the
major offset could appear at very early stages (i.g. the mixer output), circuits that can only can-
cel their own offsets won’t help much. And there are still other issues which limit the use of an
offset cancelling approach. One example is systems where there are no idle time slots for offset
measuring. Thus, the high cost and feasibility problem of offset cancellation explain why most,
if not all, successful direct-conversion receivers are designed to handle only signals with negli-
gible frequency components near DC. And we can come to the conclusion that a decent offset
cancellation solution must be able to (1) cancel or reduce early offset; (2) minimize offset from
succeeding stags; (3) be compatible with the system protocol. Suppose the harmonic mixer
functions very well and the offset due to self-mixing becomes negligible, weak signals will
still be corrupted by the mismatch-induced DC offset. Therefore, the cancellation is not com-
plete. We also don’t want to follow the design example of the 2FSK receiver and make use of
AC-coupling or high-pass filtering as the 4FSK high speed signal does have important infor-
mation energy around DC (Figure 2.1). An alternative solution is thus necessary to fulfill the
task.
It’s easy to verify that for two equal-amplitude (sinusoidal) signals, the difference between
their DC levels is equivalent to the difference between their envelops. As the positive and neg-
ative components of a differential signal are equal-amplitude in nature, a peak detector has the
potential to function as an offset detector. The offset can then be subtracted off the signal eas-
ily. We call this technique differential peak alignment. But first of all, answers have to be given
for a number of questions.
The first concern is whether the peak detector is capable of working with signals that are
not DC-free. To answer this question, knowledge of the signal in the time domain will be help-
ful. In Figure 4.18 the waveform of a differential zero-IF 4FSK signal is given, together with
its positive and negative components. It is clear that the peak detector must be able to yield the
correct output even when the signal has only half sinusoidal cycles. A full-wave rectifier meets
this requirement but half-wave rectifiers could also be useful. The idea is, by tracking positive
(increasing) transitions and negative (decreasing) transitions at different speeds, it might be
possible to tolerate several consecutive data symbols each contains a half sinusoidal cycle.
CHAPTER 4 Circuit Design I 49
Take the one shown in Figure 4.19 for example, which is half of the peak detector used in the
AGC loop, the output voltage leakage at the absence of negative peaks is
Where N is the number of symbols and RS is the symbol rate. The effectiveness of offset can-
cellation depends on both the signal and the rectifier. Assume the rectifier itself does not intro-
duce any offset, ∆V will become a residual offset of the opposite polarity after the cancellation.
To limit ∆V to 10% of the signal amplitude A within 2 symbol intervals, a small I0/C ratio
should be used:
For A = 10 mV and RS = 3200 kbps, the value is 1.6. If the current is 80 nA, the capacitor
will be as large as 50 nF. If the input signal has an ideally constant envelop, the ratio can be
made arbitrarily small. Otherwise, the detector will fail to response to a fast amplitude drop. A
better solution, as just mentioned, will be a full-wave rectifier based approach. In this case, the
voltage leakage will be confined to a single symbol interval. A fast response to amplitude vari-
ation is thus allowed.
This approach is very similar to high-pass filtering but it is intrinsically a nonlinear process.
They both have the slow response problem due to the very low corner frequency or large time
constant requirement and both cause finite low frequency power loss. But due to the nonlinear
Figure 4.18. Waveforms of the zero-IF 4FSK signal.
∆VI0
C---- N
RS
-----⋅=
I0
C----
RS
2----- A
10------⋅≤
OS
VOS
CHAPTER 4 Circuit Design I 50
operation of the peak detector, a higher harmonic distortion is expected. Within one symbol
period, the location of zero-crossings will be more or less altered but the total number won’t
change. The distortion is therefore has only limited impact on the demodulation.
Another problem is the offset introduced by the peak detector and the subtractor them-
selves, which is a part of the final residual offset. As they can both be optimized for low mis-
match, the offset level can be lowered to several mili-volts or smaller. Here we see a conflict
on the gain applied to the signal: the gain should be as large as possible to overcome the distor-
tion and the residual offset while it can’t be so large as to saturate the circuit. This is a dynamic
range problem except that the offset level should also be considered. One strategy is an early
gain control at the LNA and AC-coupling between the LNA and the mixer.
Figure 4.19. A half-wave rectifier.
∆V
gm
I 0
Vout
in
C
Vdd
CHAPTER 5Circuit Design II
In last chapter, the RF and base-band building blocks including the LNA, mixer, AGC and the
channel selection filter are introduced. This chapter continues the discussion and deals with the
design of the demodulator. Digital logic designs are mainly involved but analog circuits are
also present in some important building blocks such as the zero-crossing interpolator and part
of the clock recovery circuitry.
5.1 The Overall Structure
The demodulator incorporates a modified version of the ZIFZCD described in Section 2.5 with
a clock recovery loop. According to the high-level simulation results presented in Chapter 3,
while the first level interpolation yields a BER slightly higher than that of the second level
Figure 5.1. The 4FSK demodulator.
DecisionDirectin
1I
1Q
PUL0
PUL1
ClockRecovery
NEG
POS
CounterPC Decision
Speed
direction
CounterNC
I
Qspeed
CLKx
CLK
ZCI
P0
N0
P1
N1
51
CHAPTER 5 Circuit Design II 52
interpolation, it saves nearly half of the demodulator hardware. Therefore, the interpolator
used here is of the first level. The incoming signals I and Q together with the derived signals I1
and Q1 are converted into the digital domain by four hard-limiters. Series of pulses are then
generated on the zero-crossings of the signals. Depending on the phase relationship of the I/Q
or I1/Q1 components, the pulses are delivered to either the positive channel POS or the negative
channel NEG and counted respectively by two counters PC and NC. The speed decision block
compares the outputs of the counters to a fixed threshold to determine the frequency offset of
the current symbol. The direction decision block, on the other hand, makes a comparison
between the two outputs and detects the I/Q phase difference and thus the phasor direction.
The clock recovery circuit provides clocks for the pulse generator and the decision stage.
CLK has a frequency of the symbol rate while the frequency of CLKx is 16 times higher.
5.2 Zero-Crossing Interpolator and Hard-Limiters
The ZCI is shown in Figure 5.2. Two identical adders are used to implement both the addition
and subtraction operations by simply altering the differential polarity of either input signals. To
achieve a good dynamic range, the adder is source-degenerated by Rs1 and Rs2. Resistors Rc1
and Rc2 provide the common-mode feedback (CMFB) and define the output impedance. The
circuit diagram and its DC transfer curve are given in Figure 5.3 and Figure 5.4, respectively.
The transfer curve is obtained by driving the two input ports with the same source. In other
words, the adder is in its adding mode, as shown in the lower-right corner of the curves. Over 1
Vpp differential input range, the gain variation is less than 0.5 dB.
The hard-limiter consists of 4 cascading stages. The first two stages AMP1 and AMP2 are
differential pairs. The third one AMP3 is a self-biased differential-in single-out amplifier [42],
followed by the fourth stage, a simple digital inverter. A total of about 80 dB gain is provided
by the first 3 stages, among which 24 dB is contributed by AMP1, 15 dB by AMP2 and 41 dB
by AMP3. As there is no offset compensation applied here, the DC offset originated from the
amplifiers themselves must be minimized. Special considerations are made at 3 aspects to
reduce device mismatch: passive resistive loading is provided in AMP1 which is the most crit-
ical stage in terms of offset; NMOS transistors, whose threshold voltage spread is better than
that of its PMOS counterparts in an N-well process, are used exclusively in the first two stages
CHAPTER 5 Circuit Design II 53
which define the overall offset level; input devices are biased at small (VGS−Vth) voltages to
further reduce other mismatches. Besides, the layout also makes use of the multi-finger struc-
ture and relatively larger WL products to average out process variations.
Figure 5.2. The first level zero-crossing interpolator.
Figure 5.3. The adder schematic.
Σ1
Q -
Q +1
Σ I +1
I -1
I x1
Q x1
Q-
I+
I-
Q+
Ix
Qx
Rc1 Rc2
Vdd
in 2
in 1
Rs2
CMFB
Rs1
out
CHAPTER 5 Circuit Design II 54
5.3 Zero-crossing Pulse Generator
In Figure 2.8 a conceptual diagram of the zero-crossing pulse generator is given. Here in Fig-
ure 5.6 is an implementation using digital logic gates and flip-flops. The idea is very much
similar to the demodulator in [6]. The combination of a D flip-flop and an exclusive-OR gate
forms a difference circuit which is the digital counterpart of the analog differentiator. For an
incoming signal IX or QX, the resulted signal I' or Q' is a pulse train with the pulse width equal
Figure 5.4. The transfer characteristic of the adder.
Figure 5.5. The hard-limiter.
-3
-2
-1
0
1
2
3
-1
500m
0
500m
1
-1 -500m 0 500m 1
Input Differential Voltage [V]
Out
put V
olta
ge [
V]
Gai
n [d
B]
+−
+ −+−input output
1 Vpp
0.5 dB
out
AMP1 AMP341 dB24 dB
AMP215 dB
in
Vdd
CHAPTER 5 Circuit Design II 55
to the period of CLKx. Each pulse is situated at a transition edge of the incoming signal.
Unlike the output of the differentiator, these pulses do not have a negative polarity to distin-
guish a falling edge from a rising one. Therefore, a different approach must be taken to extract
the relative phase information between IX and QX. Another XOR gate XS is used for this pur-
pose. Its output Sgn signs a “polarity” to each pulse of I' and Q' by delivering it to either the
positive channel POS or the negative channel NEG. If IX is 90° leading QX, Sgn will be “1” when
there is a transition in IX, or “0” when there is a transition in QX. The value is reversed when IX
lags. It is then a straightforward task to derive the following equations:
Figure 5.6. The zero-crossing pulse generator.
Figure 5.7. Signal waveforms of the pulse generator.
D Q
D Q
Q’
I’
XQ
XS
XIP0
N0
Qx
IxId
Qd
Sgn
’I
’Q
Sgn
POS
NEG
Qx
Ix
CHAPTER 5 Circuit Design II 56
This is accomplished by the NAND gates in Figure 5.6. Figure 5.7 shows the waveforms of the
input and output signals as well as the internal signals I', Q' and Sgn. The result can be com-
pared to the waveforms shown in Figure 2.5 or Fig. 7 of [6]. As the clock frequency goes
higher, the pulse width becomes narrower and the circuit performs more like the differentiator-
based analog system. Intuitively, a higher clock rate yields a better resolution and a better per-
formance. However, this comes with a hardware penalty, as will be seen in the discussion on
the clock recovery circuit. To choose an optimal clock rate, a high-level simulation is carried
out to compare the BERs under different clock rates. It is observed that a clock runs at 16 times
the symbol rate (16×3.2 kHz or twice the 25 kHz channel spacing) results in negligible degra-
dation from higher clock rates. Hence, CLKx is derived from the same source as the symbol
clock CLK in Figure 5.1 and is 16 times higher.
5.4 Direction and Speed Detection
The positive and negative pulse trains from the pulse generator are passed to the clock recov-
ery block and delayed by 1 symbol period there. The delayed pulses then enter the final detec-
tion stage which is mainly made up of counters and comparators, as shown in Figure 5.8. The
number of positive and negative pulses are counted respectively by two identical 5-bit counters
PC and NC. The outputs are named A and B. The counters are also clocked by the 16× clock
CLKx. A reset signal which is derived from the symbol clock CLK clears A and B at the begin-
ning of each symbol. Three comparators take the A and B from PC and NC to make the final
decision. The direction comparator DCMP compares A with B. Its output direction is “1” if A ≥
B, “0” if A < B. That is, if there are more positive pulses in one symbol interval than negative
ones, the phasor direction is said to be positive, and vice versa. When the number of positive
and negative pulses are equal, the direction is randomly set to be positive. The other two com-
parators, PSCMP and NSCMP, determine the phasor speed by comparing A and B with a preset
threshold. This threshold depends on the interpolation level and can be calculated from (2.7):
(5.1)
POS I′ Sgn⋅ Q′ Sgn⋅+=
NEG I′ Sgn⋅ Q′ Sgn⋅+=
Nth 2 i 1+( )an_AVGh 8= =
CHAPTER 5 Circuit Design II 57
where i = 1 is the interpolation level, an_AVG = (3+1)/2 = 2 is the average symbol value and h =
1 is the modulation index. Outputs of these two comparators will stay at the “low” level until
the current symbol has a high offset frequency (nominally 4.8 kHz). In that case, one compara-
tor will jump to the “high” level while the other keeps its output low, depending on the polarity
of the offset frequency or the rotation direction of the phasor. The right one is selected by the
direction signal.
5.4.1 The Dual-Input 5-Bit Counter
The simple asynchronous ripple structure is chosen to implement the counter. An important
drawback of this type of counters is that their outputs are not crisp. The undesirable glitches
may cause errors in the following stages. But this is not a problem here due to the globally syn-
chronous design. The combinational logic that reads the counters’ outputs is again followed by
a sequential logic stage. As the total delay of the counter and the combinational logic is orders
Figure 5.8. The final detection stage.
A4A3
A0B4B3B2
A2A1
B0B1
A4A3
A0B4B3B2
A2A1
B0B1
A4A3
A0B4B3B2
A2A1
B0B1
Q3Q2Q1Q0
Q4A
B
RESET
Q3Q2Q1Q0
Q4A
B
RESET
CLK
CLK
P0
P1
N0
Reset
N1
CLKx
B4B3B2
B0B1
A4A3
A0
A2A1
A>=B
A>=B
A>=B
SEL
0
1 speed
direction
Vdd
DCMP
NSCMP
PSCMP
PC
NC
CHAPTER 5 Circuit Design II 58
of magnitude smaller than the clock cycle, the outputs has more than enough time to settle. The
cost is an increased latency. But still, that is not a concern in a paging receiver.
What makes this counter different from the general binary ripple design is the dual-input
requirement. Due to the 1-level ZCI, the POS channel has 2 parallel pulse trains P0 and P1, and
so does the NEG channel. Pulses from both trains should be counted simultaneously. As a
result, the counter has 2 inputs A and B and 5 outputs Q4 to Q0. D flip-flops with reset terminals
are used as the memory elements. The circuit is shown in Figure 5.9. In fact, only the last 3
Figure 5.9. The dual-input 5-bit counter.
Table 5.1 State transition table of the counter.
A B Q1 Q0 D1 D0
0 0 0 0 0 0
Hold0 0 0 1 0 1
0 0 1 0 1 0
0 0 1 1 1 1
0 1 0 0 0 1
+1
0 1 0 1 1 0
0 1 1 0 1 1
0 1 1 1 0 0
1 0 0 0 0 1
1 0 0 1 1 0
1 0 1 0 1 1
1 0 1 1 0 0
1 1 0 0 1 0
+21 1 0 1 1 1
1 1 1 0 0 0
1 1 1 1 0 1
Q
D Q
RSTQ
D Q
Q
D Q
RST RSTQ
D Q
RSTQ
D Q
RST
D1A
B
Q1 Q2 Q4Q3Q0
DFF0 DFF1 DFF2 DFF3 DFF4
D0
RESET
CLKx
CHAPTER 5 Circuit Design II 59
flip-flops are connected in the ripple way. DFF0 and DFF1 operate in the synchronous manner.
A state transition table is written for these two elements. By inspection, their inputs D1 and D0
can be expressed as:
It can be further simplified to be:
This is exactly what is shown in the schematic.
5.4.2 The Direction Comparator
This comparator DCMP compares the two 5-bit outputs A and B of the counters PC and NC. If
A > B, or there are more pulses counted in the positive channel, the output is high meaning that
for the current symbol the phasor is rotating at the “positive” direction. If A < B, the output
goes low. The equal case is regarded the same as the larger case.
The comparison is performed on a bit to bit basis. The most significant bit (MSB) has the
highest priority. If A4 is not equal to B4, the result is obtained immediately, which is A4 or B4.
Otherwise, the result of the next bit will be used. The worst case is encountered when A4-1 =
B4-1 and the comparison result of A0 and B0, A0 + B0, have to be passed to the output. The delay
is harmless here, as is discussed in the last section.
Transmission gates are used to pass or block the results of the current and the next bit.
Doing this yields a very simple design.
5.4.3 The Speed Comparator
Outputs of the counters PC and NC are also sent to speed comparators PSCMP and NSCMP
for speed detection. Unlike the direction comparator, a speed comparator reads the input and
compares it to a fixed number, that is, the threshold 8 given by (5.1). Thus, it is much easier to
D1 ABQ1 A B⊕( ) Q1 Q0⊕( ) ABQ1+ +=
D0 ABQ0 A B⊕( )Q0 ABQ0+ +=
D1 A B⊕( )Q0 AB+[ ] Q1⊕=
D0 A B Q0⊕ ⊕=
CHAPTER 5 Circuit Design II 60
design. The truth table for Z = (A > 8) can be simply written as:
and the logic equation is
A simpler expression is resulted if Z = (A ≥ 8):
Figure 5.10. The direction comparator.
Table 5.2 Truth table of the speed comparator.
A4 A3 A2 A1 A0 Z
1 X X X X 1
0 1 A2 + A1 + A0 = 1 1
0 0 X X X 0
B2
A2
A1
B1
A3
B3
B0
A0
A4
B4
A>=B
Z A4 A3 A2 A1 A0+ +( )+=
Z A4 A3+=
CHAPTER 5 Circuit Design II 61
For more flexibility, another signal S is introduced to control whether the logic should just be
“greater than” or “greater than and equal to”:
And the final circuit is shown in Figure 5.11. The inverted signals are readily available from
the counters. It works well but a better design might distribute the four lower inputs A2, A1, A0
and S more symmetrically such that the critical path delay is reduced. With more external con-
trol signals, and hence more complex design and more bonding pads, the threshold can be
adjusted over a wider range. But the extra cost buys very little benefit.
5.5 Clock Recovery
In analog limiter-discriminator based FSK demodulators [43] or the digital 2FSK demodula-
tors [4-6][38], no timing signal is needed and clock recovery is a post-demodulation task of the
digital signal processing unit. This is because the demodulation is carried out by detecting the
instantaneous signal frequency or I/Q phase offset, rather than on a symbol by symbol basis. In
the ZIFZCD, however, the knowledge of all zero-crossings over each symbol period is
required. It then calls for an early clock recovery at the demodulation phase. The problem here
is that a proper timing signal must be provided before the correct data is extracted. Thus, a pre-
demodulation process becomes necessary to feed the clock recovery circuit with partially
demodulated data in which the precise clock information is borne. Such a data stream is avail-
able from the zero-crossing pulse generator. Ideally, pulses appear only in either the POS or the
NEG channel. As the symbol changes its sign, the phasor starts to rotate in the opposite direc-
Figure 5.11. The speed comparator SCMP.
Z A4 A3 S A+ 2 A1 A0+ +( )+=
A3
A4
A2
A1A0
S
Z
CHAPTER 5 Circuit Design II 62
tion. The pulse generator then closes the current channel and pumps pulses into the other one.
Thus, a data transition can be detected without a clock.
The clock recovery circuit consists of a transition detector TD, a phase detector PD, a
charge pump, a voltage-controlled oscillator (VCO) and two frequency dividers (pre-scalers).
The pulse clock CLKx and the symbol clock CLK are obtained by dividing the VCO output
frequency by 8 and 128, respectively. The reset signal which initiates the counters at the begin-
ning of each symbol is derived from CLK.
5.5.1 Transition Detector
The transition detector can be a simple trigger which is set and reset by the rising (or falling)
edges of P0 and N0 respectively. With some kind of trigger circuits, a data transition signal TD
can be generated and used directly for phase comparison. But the simplicity comes with a
price. As shown in Figure 5.13, when a noise induced pulse appears in a closed channel, the
trigger produces a transition by mistake. In response, an error signal will be generated by the
phase detector to tune the VCO. This can temporarily drive the loop off the locked state or
cause other locking problems.
This won’t be too problematic in those 2FSK demodulators because the data will be filtered
before any further processing and the noise can be greatly suppressed. Filtering should also be
applied here to either the pulse trains or the transition signal to minimize the chance of false
triggering. To align the data with the clock, the filtering delay must be compensated. A digital
implementation is thus preferred because its delay can be introduced to the data very accu-
Figure 5.12. The clock recovery circuit.
D Q
÷8÷16
TD
outf
INCP D Charge
Pump
CLK
CLKx
VCO
P0
N0T D
Reset
DEC
CHAPTER 5 Circuit Design II 63
rately while this is not true for analog filters. Nevertheless, a decent digital filter design may
require a complex structure and become very hardware intensive when compared to the
demodulator itself. Lee et al. proposed an alternative synchronization scheme for the ZIFZCD
[44]. Under the condition of Figure 5.14, a positive to negative transition is most likely
occurred between t4 and t5. The synchronization algorithm specifies the transition time tT with
the following relationship:
tT can then be calculated to be
It is reported that the performance degradation of the ZIFZCD with this algorithm is only 0.1
dB from a perfectly synchronized system at 1% BER. However, the precise computation
required here demands considerable complexity. At the current phase of design, only a very
simple scheme is used. That is, the transition detector produces a “1” if a pulse sequence of “−
1 −1 +1 +1” is detected and a “0” if “+1 +1 −1 −1” is detected. Thus, the false trigger due to
single noise pulse is eliminated.
Figure 5.13. Simple transition detection with a trigger.
Figure 5.14. Lee’s synchronization scheme.
noiseinduced
falsetrigger
N0
P0
Td
t3 t4–t5 t6–----------------
t4 tT–tT t5–---------------- k= =
tTt4 kt5+1 k+
----------------=
1t 2t 3t 4t5t
6t7t
8t9tt10
t11
t12t13
t14t15
t16
t
CHAPTER 5 Circuit Design II 64
A conceptual diagram describing the detector is shown in Figure 5.15. There are 4 types of
main building blocks: shift registers RP and RN, “11” detectors CP and CN, the combinational
decision logic and the output stage. RP and RN each has 16 taps and is thus 1 symbol long. The
pulses stored in RP and RN are examined by the decision logic. The signal XP is set when two or
more “1”s are found in RP and none is found in the same range of RN. Here “the same range”
refers to the shift register taps starting from P0D and extending toward P0 until both “1”s are
covered. XN is determined in a similar manner. The “11” detector is a simple Moore machine
which checks its input for two “1”s. It is cleared by the CLR signal which is the delayed pulses
in the opposite channel. The signal S sets the output stage while R resets it.
The pulses shown in Figure 5.14 can be used to explain how the detector works. Note that
there are two pulse trains. The positive pulses come from P0 and the negative ones from N0.
Suppose CP and CN are initially at their cleared states. At the time of t5, There are 4 “1”s stored
in RP and none in RN. Therefore, XP = 1, XN = YP = YN = S = R = 0, TD keeps its initial value.
Several clocks later, the pulses at t1 and t2 are detected by CP and YP is set. As there are pulses
in both RP and RN, they reset each other so that XP = XN = 0. TD remains unchanged. When the
positive pulse at t4 is shifted to CP, RP is empty (no pulses), XN becomes “1” and R = YP∙XN = 1
resets TD. The example is also demonstrated graphically in Figure 5.16.
The actual circuit block diagram is shown in Figure 5.17 except the output stage. Part of the
decision logic is merged with the shift register and forms the AC block. The rest is the AOA
block which absorbs the R/S NAND gate. The following paragraphs explain the function and
working principle of each block including the output stage.
The AC Block and AOA Block. The AC block is named after the signals it produces.
Remember that the decision logic checks whether there are two “1”s in one register while the
other register is empty over the same range. The information is provided by signals A and C.
With the auxiliary signal B, the example given in Figure 5.18 helps make things more clear. B
and C can be expressed by:
BQi Qn
n 0=
i
∑=
CQi Qi Qm
m 0=
i 1–
∑
=
CHAPTER 5 Circuit Design II 65
where Q is just a place holder which should be replaced by P or N and the summation symbol
stands for the “OR” operation. If a register is empty up to the i-th tap, BQ1 to BQi are all “0”.
Thus, B can be used as an “empty indicator”. On the other hand, CQi = 1 means there are two
“1”s detected from Q1 to Qi. As a result, the condition “there are at least two ‘1’s in register RP
while RN is empty over the same range” is equivalent to the statement “there exists an index i
such that CPi = 1 and BNi = 0”. In logic expressions, we have
Figure 5.15. Model of the transition detector.
Figure 5.16. Waveforms of the transition detector model.
1 symbol
PR
CP
CLR
"11" detector
IN
Td
RN
XP
XN
CN
"11" detector
CLR
IN
YP
YN
DP0 (P0 Delayed)
DN0 (N0 Delayed)
Decision Logic
P0
N0
StageOutput
R
S
PX
NX
PY
NY
DP0
DN0
T
R
S
P0
N0
CLKxtransition
D
CHAPTER 5 Circuit Design II 66
The signal A is nothing but the inverse of B, i.e.
XP and XN can then be re-written as
It follows that
Figure 5.17. Block diagram of the transition detector, the output stage excluded.
A15
A14
A13
A12
A11
A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C15
A15
A14
A13
A12
A11
A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
C14
C13
C12
C11
C10
C15 C9
C8
C7
C6
C5
C4
C3
C2
C1
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C15
C14
C13
C12
C11
C10
C15 C9
C8
C7
C6
C5
C4
C3
C2
C1
AOA S
AOA R
AC P
AC N
Y
Y
CLK
IN
IN
CLK
CPIN
CLK
CLR Y
N0 D
P0 D
CNIN
CLK
CLR Y
Y P
Y N
CLKx
P0
N0
R
S
XP CPiBNi
i
∑=
AQi BQi=
XP CPiANi
i
∑=
XN CNiAPi∑=
CHAPTER 5 Circuit Design II 67
(5.2)
Circuit diagram of the AC block is given in Figure 5.19. The AOA block which generates the
R/S signal is shown in Figure 5.20. Formed by a pseudo-NMOS AND-OR-AND-NOT gate
and a static inverter, it implements the function given by (5.2).
The “11” Detector. This is a 3-state Moore machine. Its out is set when two or more “1”s, suc-
cessive or not, are found in the IN signal. A synchronuous reset signal CLR resets the output
and the current state. Both the IN and CLR can be treated as input signals but the state transi-
tion diagram will be much simplified by just considering IN first. The state transition diagram
and state transition table are shown in Figure 5.21 and Table 5.3. Using two D flip-flops as the
memory element, their inputs will be:
Figure 5.18. Working principle of the AC block.
R YPXN YP CNiAPi
i
∑ = =
S YNXP YN CPiANi
i
∑ = =
N3 N2 N1 N0
B
BN2CN3
CN2
CN1
D=N0
BN1
01 0 1
=1
=0
=1
=1
=0
=1
CP1
P0P1P2P3
CP2
CP3
BP2
BP3
D=P0
BP1
0 000
=0
=0
=0
=0
=0
=0
NX = 1PX = 0
CHAPTER 5 Circuit Design II 68
Now the reset signal can be inserted into the logic equations:
The output Z can be directly taken from Q0. The circuit diagram is shown in Figure 5.22.
The Output Stage. Function of this block is to combine R and S to form a single data transi-
tion signal. The truth table of a D flip-flop implementation is shown in Table 5.4. Input to the
flip-flop is simply
Figure 5.19. Circuit diagram of the AC block.
Figure 5.20. The AOA block.
Q
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
A12
C12
A13
C13
A1
C1
A2
C2
A3
C3
X
A14
C14
A15
C15
CLKx
IN
Z
Vdd
Y
C3
A3
C2
A2
C4
A4
C1
A1
C14
A14 A15
C13
A13
C15
D0 Q0 INQ1+=
D1 IN Q1+=
D0 CLR Q0 INQ1+( )=
D1 CLR IN Q1+( )=
CHAPTER 5 Circuit Design II 69
The circuit diagram is given in Figure 5.23.
Transition detection does not happen at the precise transition point tT and therefore intro-
duces offset and jitter. But these effects don’t seem to cause serious problems.
Figure 5.21. State transition diagram and state transition table of the “11” detector.
Figure 5.22. Circuit diagram of the “11” detector.
Table 5.4 Truth table of the output stage.
R S D
0 0 Q
0 1 1
1 0 0
1 1 X
00
01 1X
1/0
0/0
1/1
X/1
input/outputTable 5.3 State transition table of the “11” detector.
Q0 Q1 IN Q0+ Q1
+ Z+
X X 0 Q0 Q1 Z
0 0 1 0 1 0
0 1 1 1 X 1
1 X 1 1 X 1
Q
D Q
Q
D QD0D1 Q1 Q0
INZ
CLR
CLKx
D R S Q+( )=
CHAPTER 5 Circuit Design II 70
Recall that in a FLEX signal structure, a synchronization signal at 1600 bps is provided at
the beginning of each frame. This signal should be more than 100 bits long. Although the clock
recovery circuit designed here is for 3200 bps data rate, it can be easily modified to accommo-
date the low bit rate signal.
5.5.2 Phase Detector
Inputs of the phase detector are the transition detector’s output TD and the system clock fout. As
TD is a non-return-to-zero (NRZ) signal, an edge detector is necessary to “double” its fre-
quency such that it contains a strong component at the symbol rate. The output signals INC and
DEC are connected to the charge pump. The VCO frequency is increased when INC is active or
decreased when DEC is active. The phase error between fin and fout results in an error signal E:
But it is its complement E that is actually generated:
Figure 5.23. Output stage of the transition detector.
Figure 5.24. The phase detector.
Q
D Q TdSR
Q
QD INC
D
Efin
EdgeDetectorDT
foutD
DEC
E finfout=
E fin fout+=
CHAPTER 5 Circuit Design II 71
As the error signal produced by an XOR phase detector would be
E can be considered as a “half XOR” of fin and fout and the phase detector has a characteristic
similar to that of an XOR gate except a lower gain. An undesired feature of the XOR phase
detector is the dependence of its output on input duty cycle. The problem is more severe here
because it can result in a large dead zone where the output is zero even with a non-zero phase
error as illustrated in Figure 5.25. To avoid this effect, both inputs need to be 50% duty cycle.
This is hard to achieve because neither cycle is constant. But if the pulse width of fin is kept
exactly half the fout cycle, the requirement can be finally satisfied when the loop is locked. The
edge detector shown in Figure 5.24 is used for this purpose, where TD is first delayed by half
fout cycle and then combined by an XOR gate with the original signal to create the fin signal. A
certain amount of correlation is introduced between fin and fout through the delay process. The
effect will be discussed in Section 5.5.4.
Another problem appears as transitions are absent in the input data stream. This is due to
the random nature of the data. It can also happen to the synchronization signal when the SNR
is not high enough. In a full XOR operation, missing transitions will be mistakenly regarded as
phase errors and result in a continuously accumulated error voltage and finally cause serious
lock problem. The half XOR operation is a strategy to handle possible absent data transitions.
As shown in Figure 5.25 (b), the error signal E is allowed to be set only when fin is active.
When there are no transitions, fin stays at the low level and so does E.
Figure 5.25. Dependence of the error signal on input duty cycle (a) and data transitions (b).
EXOR finfout finfout+=
f
f
in
E
data transitionsabsence of fin
fout
E XOR
E
out
(a) (b)
CHAPTER 5 Circuit Design II 72
The signal D is used to determine whether the VCO should raise its frequency. The idea is
to minimize the distance between the neighboring rising edges of fin and fout in the time axis. It
follows the following rule: at each rising edge of fin, if fout is “1”, then its frequency should be
decreased (D = 1) such that its next rising edge will be delayed and hopefully closer to that of
fin; otherwise its frequency should be increased (D = 0). Now logic expressions can be written
for INC and DEC in terms of E (fin and fout) and D:
Working principle of the phase detector can be explained by Figure 5.26. Initially, fout is slower
than and lags fin. This results in a negative E pulse and a zero D in the first fin cycle. Conse-
quently, INC becomes active and pushes the VCO toward a higher frequency. In the following
several cycles, the frequency error is reduced but the phase error is still accumulated. As a
result, D stays at “0” and INC is activated in each cycle until the frequency of fout is slightly
higher than that of fin. As fout is now leads fin, D becomes “1” and the DEC signal is activated.
Both the frequency error and the phase error are reduced considerably from their initial values.
This is a sign that the loop is on its way to lock.
Figure 5.26. Waveforms of the phase detector.
INC finfoutD ED= =
DEC finfoutD ED= =
fout
fin
TD
E
INC
DEC
D
CHAPTER 5 Circuit Design II 73
5.5.3 VCO and Charge Pump
The core element of the VCO, as shown in Figure 5.27, is a source-coupled multivibrator. The
transistors M1 and M2 are turned on and off alternatively. As the switching frequency is
directly related to the bias current I, it makes more sense to describe the vibrator as a current
controlled oscillator (ICO) rather than a VCO. Depending on the biasing conditions, the “ON”
mode can either be a saturation mode or linear mode. As the nominal center frequency is only
409.6 kHz, the latter is chosen for the low frequency operation. Analysis of the oscillator cir-
cuit can be done following the bipolar example given in Chapter 10 of [31]. Ideally, the voltage
change over the capacitor C in each half cycle can be approximated by
(5.3)
where
The subscript “1” stands for transistors M1 and M2, “3” for M3 and M4. The output frequency
is easily derived as
(5.4)
Due to the subthreshold conduction and parasitic capacitance (including gate capacitance), ∆V
is about 200 to 300 mV smaller than what is estimated by (5.3). Accordingly, the actual fre-
quency is almost 30% higher. Despite the discrepancy, (5.4) does predict the ICO gain with
high accuracy. In Figure 5.28, the frequencies calculated using (5.4) are compared with simula-
tion results at different bias currents. In both cases the ICO gain KICO is around 32 kHz/µA over
the interested frequency range.
Besides the multivibrator, the complete VCO also consists of a Gm cell, a current mirror
and an output buffer which also serves as a differential to single-ended converter. The Gm cell
∆V ∆VGS3 Vth1 ∆VGS3 Vth1–( )2 4∆VGS1+–+=
∆VGS12I
µCox W1 L⁄ 1( )---------------------------------=
∆VGS32I
12---µCox W3 L⁄ 3( )------------------------------------=
f1
2∆V----------- I
C----=
CHAPTER 5 Circuit Design II 74
is of the same type as the one used in the gyrator filter except that here its output is single-
ended. The transconductance gm is about 6.5 µS. Thus, the overall VCO gain is
The charge pump circuit is shown in Figure 5.29. By assuming the average current charging
the capacitor to be Ipφe/(2π) where φe is the phase error, natural frequency and damping factor
of the loop will be [45]
Figure 5.27. The complete VCO.
Figure 5.28. Multivibrator frequency vs. bias current.
Gm multivibratormirror
I 0
I∆
Vdd
Vc
Vref
VbI
outputA
C
I
M3 M4
M2M1
8 8.5 9 9.5 10 10.5 11 11.5 12250
300
350
400
450
500
I [uA]
f [k
Hz]
CalculationSimulation
KVCO
gmKICO
scale ratio------------------------ 6.5µ 32k×
8 16×--------------------------≈ 1.625 kHz/V= =
CHAPTER 5 Circuit Design II 75
Given the current source and VCO gain, passive components can be determined by choosing
ωn and ζ properly:
This results in 16 nF Cp and 86 kΩ Rp at 10 µA Ip when ωn = 1000 rad/s and ζ = 0.7.
5.5.4 Loop Behavior
In normal PLL or clock recovery circuit designs, the reference signal or the incoming data is
independent of the signal whose frequency is to be tuned. But in this one, as presented in above
sections, all timing signals are derived from the same VCO output. As a result, input and out-
put of the clock recovery circuit are highly correlated. This is of course not imperative as the
clock can be generated from an independent source with more stable and accurate frequency
characteristics. But such a signal source will, almost inevitably, be off-chip and a complicated
frequency divider must be designed to obtain the required reference frequency. Making use of
Figure 5.29. The charge pump.
ωn
Ip
Cp
-----KVCO=
ζ Rp
2----- IpCpKVCO=
CpIpKVCO
ωn2
---------------=
Rp2ωnζ
IpKVCO
---------------=
INC
I p
I p
Vdd
Vc
DEC C
R
p
p
CHAPTER 5 Circuit Design II 76
the VCO output changes the loop behavior in an unknown manner but also eliminates the need
of the additional hardware.
To study the impact of the fout-dependent delay which is introduced in the edge detector of
the PD, the acquisition process is simulated and shown in Figure 5.30 (b), together with that of
the ideal case where fin is independent of fout (a). Both cases have the same initial conditions
and share the same 50% duty cycle 1.6 kHz TD signal. The only difference lies in the way the
edge detector delays TD. In the ideal case (a) TD is delayed by half of its own cycle while in (b)
it is delayed by half the fout cycle, or 8 pulse clock (CLKx) cycles.
Figure 5.30. Impact of the fout-dependent delay on the acquisition process: fin and fout are (a) uncorrelated and (b) correlated.
TD
f out
f inV
CT
Df ou
tf in
VC
(a)
(b)sec
sec
CHAPTER 5 Circuit Design II 77
Very similar loop dynamics are given by the figures. Initially, fout is about 550 Hz slower
than the 3.2 kHz nominal symbol rate and the phase error is larger than π. In both cases the fre-
quency of fout is further lowered to adjust the phase error such that the loop gain is maintained
at a negative value. Loop (a) then exhibits the behavior of a typical slightly under-damped
PLL. Loop (b) basically repeats this process but with noticeable difference. As shown in the
figure, fin has a variable duty cycle which depends on the instantaneous fout frequency. We can
examine how the duty cycle varies and how this variation affects the loop dynamics in three
aspects:
1. When the frequency of fout is to be increased, as is the case in the 1 to 4.5ms range of the
figure, the duty cycle variation won’t change the error signal and hence the loop behav-
ior. This is because fin is leading fout and the phase error is calculated from the rising edge
of fin to the rising edge of fout. These two points are virtually independent of the duty
cycle of fin.
2. When fout is to be decreased, the phase error is calculated from the falling edge of fout to
that of fin. Depending on the loop parameters and the initial conditions, the duty cycle of
fin could be either stretched or suppressed. In general, the duty cycle is proportional to the
initial phase error and reversely proportional to the initial frequency error (fout − fin). Its
variation changes the average charging current and can be regarded as a variation of the
charge pump current source. As a result, the loop tends to be momentarily under damped
at small phase errors and finite frequency errors while over damped at small frequency
errors and finite phase errors. Both effects can lead to longer settling time.
3. As a special case of condition 2, if TD is not aligned with CLKx, the time that fin stays
high will be less than half fout cycle. At small phase errors, this can lead to a state of false
lock where there is no error signal generated. The situation persists and causes a
permanent static phase error as long as the loop is frequency locked. Otherwise, the
phase error will continue to accumulate and finally break the false lock state. The
waveforms after 6.5 ms demonstrate such a situation.
At the time of 10 ms, loop (a) has reduced its phase error to 2.5° and frequency error to about 4
Hz. Meanwhile, comparable results of 2.24° and −23.5 Hz are achieved by loop (b).
CHAPTER 5 Circuit Design II 78
One method to eliminate the false locking state described in condition 3 is to synchronize
TD with CLKx. This is what happens in the zero-crossing pulse generator and the transition
detector. But the synchronization has its own problems. In the pulse generator, a pulse has to be
shifted from the actual zero-crossing position by a certain distance. At the same time, the pulse
width and the spacing between pulses have to be integer multiples of the pulse clock period.
This causes the position and spacing of the pulses to vary with the clock rate. In the transition
detector, as the shift register is also clocked by CLKx, the resultant TD signal has a strong cor-
relation to the clock too. As a result, the TD cycle will be forced to follow that of fout tempo-
rarily until it deviates from the nominal value by more than 1 clock cycle. The error is then
reduced by inserting or removing 1 clock cycle from TD. This, together with the similar effect
found in the pulse generator, causes jitter-like but output-dependent errors to appear in fin and
results in longer loop settling time.
5.6 An Overall Simulation
To conclude this chapter, waveforms from an overall simulation is given in Figure 5.31. The
original data is a series of alternate “+3/−3” symbols. The I and Q components of the down-
converted zero-IF signal are shown in the top row. Ix and Qx are the same set of signals after
amplification and low-pass filtering. The amplitude ramp is caused by the AGC during set-
tling. Its impact on the demodulation process can be neglected. Operation of the clock recovery
circuit is presented by the signals fin, fout and Vc as discussed in the last section. The initial fre-
quency error is 440 Hz or about 1.4%. As all nodes are initially set to zero volt, the transition
detector doesn’t have an output until the shift registers are full. The zero initial condition also
results in unequal positive and negative pulses in Vc. Although this does not cause any serious
problems here, it can disable the charge pump when fout is faster than fin. Several methods are
available to solve this problem. By tuning the reference voltage, fout can always be set to a
slightly higher frequency when Vc is zero. Making use of a differential charge pump or a pre-
charge circuit can also help out. The latter sets Vc to a intermediate voltage between ground
and the power supply during the power on process. The demodulation outputs are direction and
speed. The errors at the first 2 or 3 symbols are also resulted from the initial condition.
CHAPTER 5 Circuit Design II 79
Figure 5.31. An overall simulation of the demodulator.
I/Q
Ix/Q
xf in
f out
dire
ctio
nV
Csp
eed
CHAPTER 6Measurement Results
Having discussed the design of the AGC, LPF and the demodulator, we report the detailed
measurement results of the base-band circuitry in this chapter. The performance of the RF
front-end as well as that of the whole receiver are also summarized. The die photo is depicted
in Figure 6.1. Please also refer to Appendix B for details on the base-band testing setup.
6.1 AC Transfer Curves
Figure 6.2 shows the simulated and measured transfer curves of the AGC at its maximum gain.
The measured gain is slightly higher at low frequencies and decreases earlier when the fre-
quency increases. This implies that the equivalent feedback resistance of the VGA is relatively
larger in the measurement. It can be caused by a 2 to 3 mV error in the control voltage (Vc4−
Vc1) as shown in (4.4) and Figure 4.7 on page 36.
Figure 6.1. The die photo of the whole prototype receiver.
80
CHAPTER 6 Measurement Results 81
Figure 6.3 is the transfer curves of the LPF. The matching between the measurement and
the simulation demonstrates the excellent sensitivity property of the LC ladder. The pass-band
is about 9 kHz with a nominal gain of −6.2 dB and a ripple smaller than 0.5 dB. The stop-band
starts from 17.8 kHz. The stop-band attenuation is larger than 63 dB.
In Figure 6.4 the transfer curves of the offset cancellation stage is given. The measured
gain over 1 to 10 kHz is about −2.5 dB, 0.5 dB higher than the simulated value. This is proba-
bly because the charging current I0 is smaller in the real circuit (see Figure 4.19 on page 50). It
can also be seen that when there is an input signal, the harmonic distortion slows down the roll-
off of the transfer curve at low frequencies.
6.2 Noise Performance
Cascaded output noise voltage spectral densities of the AGC, the LPF and the offset cancella-
tion stage are plotted in Figure 6.5. Figure 6.6 shows equivalent input noise spectral densities
of the AGC and LPF, when referred from the LPF output and the AGC output, respectively.
The flicker noise coefficient KF is estimated using the curve-fitting method. It turns out that
KF’s at the order of 10−28 to 10−27 V2F match the simulation well to the measurement. The
results are shown in Figure 6.7 where KFNMOS = 10−27 V2F and KFPMOS = 10−28 V2F are used.
Figure 6.2. Simulated and measured AGC transfer curves at the maximum gain.
102
103
104
105
17
17.5
18
18.5
19
19.5
20
Frequency [Hz]
Gai
n [d
B]
SimulatedMeasured
CHAPTER 6 Measurement Results 82
These numbers are much lower than the typical value quoted in the literature. This should be
due to the near weak inversion operation of the transistors.
Figure 6.3. Simulated and measured transfer curves of the LPF.
Figure 6.4. Simulated and measured transfer curves of the offset cancellation stage.
0 5 10 15 20 25 30−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Frequency [kHz]
Gai
n [d
B]
Measured Simulated (LC Ladder) Simulated (Gyrator Filter)
101
102
103
104
105
−25
−20
−15
−10
−5
0
5
Frequency [Hz]
Gai
n [d
B]
Simulated AC Transfer Curve Measured without Input Signal Measured with 100 mV Chirp Input
CHAPTER 6 Measurement Results 83
6.3 Harmonic Distortion
Harmonic distortions of these stages are also measured in the cascaded way. The input signal is
a sin wave with the frequency and differential amplitude of 3.2 kHz and 200 mV (206 mV
actually). The AGC gain is set to be 6 dB. Under these conditions, the outputs of the AGC, the
Figure 6.5. Cascaded noise voltage spectral densities at the output of the AGC, the LPF and the offset cancellation stage.
Figure 6.6. Input-referred noise spectral densities.
101
102
103
104
105
10−7
10−6
10−5
10−4
Frequency [Hz]
Vrm
s/sq
rt(H
z)AGC Output
Offset Cancellation Output
LPF Output
101
102
103
104
105
10−7
10−6
10−5
10−4
10−3
10−2
Frequency [Hz]
Vrm
s/sq
rt(H
z)
(a)
(b)
(c)
(d)
(a) LPF input noise, referred from LPF output(b) AGC input noise, referred from LPF output(c) AGC output noise(d) AGC input noise, referred from AGC output
CHAPTER 6 Measurement Results 84
LPF and the offset cancellation stage are read as A0, G0 and O0, respectively. The input signal
vin is then changed to −vin by switching its differential terminals. The output signals are
recorded again in order as A1, G1 and O1. Doing so makes it easier to calculate the 2nd order
harmonic distortion parameter, as will be discussed shortly. The spectra of these signals are
depicted in Figure 6.8 and Figure 6.9. It can be seen that the input signal itself contains a cer-
tain amount of harmonic components. These components will be processed by each stage and
Figure 6.7. Noise simulation that estimates the flicker noise parameters by curve fitting.
101
102
103
104
105
10−6
10−5
10−4
Frequency [Hz]
Vrm
s/sq
rt(H
z)Thermal Noise Only
Flicker Noise Included
Measurement
101
102
103
104
105
10−8
10−7
10−6
10−5
10−4
Frequency [Hz]
Vrm
s/sq
rt(H
z)
Thermal Noise Only
Flicker Noise Included
Measurement
101
102
103
104
105
10−8
10−7
10−6
10−5
10−4
Frequency [Hz]
Vrm
s/sq
rt(H
z)
Thermal Noise Only
Flicker Noise Included
Measurement
CHAPTER 6 Measurement Results 85
appear at the output. To accurately compute the distortion characteristics, their effects should
be minimized.
The 3rd order polynomial is again used to model the nonlinearity. And the function of a
building block can be generally expressed in the time domain as
where x(t) and y(t) are the input and output signals and a1, a2 and a3 are three constants. As the
input already contains 2nd and 3rd harmonics, it may be written as
The 2nd and 3rd harmonics at the output are then approximated by
Figure 6.8. Signal spectra of the harmonic distortion measurement.
0 5 10
−100
−80
−60
−40
−20
0
[kHz]
[dB
V]
0 5 10
−100
−80
−60
−40
−20
0
[kHz]
[dB
V]
0 5 10
−100
−80
−60
−40
−20
0
[kHz]
[dB
V]
0 5 10
−100
−80
−60
−40
−20
0
[kHz]
[dB
V]
LPF Output G0Offset Cancellation
Input Signal +vin AGC Output A0
Output O0
y t( ) a1x t( ) a2x2 t( ) a3x3 t( )+ +=
x t( ) A ωt( )cos B 2ωt α+( )cos C 3ωt β+( )cos+ +=
CHAPTER 6 Measurement Results 86
(6.1a)
(6.1b)
(6.1)For simplicity, here we use the subscripts “2” and “3” to denote the 2nd and 3rd harmonics
respectively. For example, the 2nd harmonic of the signal A0 is A02. From (6.1) we can see that
an output harmonic component such as H2 or H3 consists of two major parts: the one which is
linearly amplified from the corresponding harmonic of the input and the one which is gener-
ated from the fundamental component due to the nonlinearity. There is usually a phase differ-
ence between them and the summation should also result in a finite phase term. Therefore all
these components are better expressed in the complex domain and (6.1) can be re-written in a
general way as
(6.2)
Figure 6.9. Signal spectra of the harmonic distortion measurement, with the input inverted.
0 5 10
−100
−80
−60
−40
−20
0
[kHz]
[dB
V]
0 5 10
−100
−80
−60
−40
−20
0
[kHz]
[dB
V]
0 5 10
−100
−80
−60
−40
−20
0
[kHz]
[dB
V]
0 5 10
−100
−80
−60
−40
−20
0
[kHz]
[dB
V]
LPF Output G1Offset Cancellation
Input Signal −vin AGC Output A1
Output O1
H2 a1B 2ωt α+( )cos12---a2A2 2ωt( )cos+≈
H3 a1C 3ωt β+( )cos14---a3A3 3ωt( )cos+≈
Hk a1vink Xk+=
CHAPTER 6 Measurement Results 87
where the subscript k = 2 or 3 is the harmonic order, vink and Hk are the input and output har-
monic components respectively, Xk is the generated harmonic due to nonlinearity. In a specific
case such as the 2nd harmonic of the AGC we have
(6.3a)(6.3b)(6.3)
for the normal and inverted inputs. Because of the square operation in (6.1a), the generated
term AX2 keeps unchanged in these two cases. It can be derived by adding (6.3a) to (6.3b) and
rearranging the result:
(6.4)
The summation eliminates the need to measure the 2nd harmonic of the input signal and hence
avoids the measurement errors. The magnitude of the generated 2nd harmonic is thus
As A02 and A12 in this equation are complex numbers and their phases are not easy to be mea-
sured accurately, we only make use of their amplitudes:
(6.5)
This is, obviously, of the worst case and applies to the other two generated 2nd harmonics, i.e.,
GX2 and OX2. It is then a straightforward task to calculate the harmonic distortion.
The 3rd harmonic, however, should be treated differently because the polarity of the gener-
ated component changes with the input. Again, take the AGC stage for example, the output 3rd
harmonics under the normal and inverted inputs are
(6.6a)(6.6b)(6.6)
As the amplified input 3rd order components in these two cases can’t be cancelled out and
won’t be exactly the same due to noise, offset and measurement errors, they are identified by
A02 aA1vin2 AX2+=A12 a– A1vin2 AX2+=
AX2A02 A12+
2---------------------=
AX2A02 A12+
2------------------------=
AX2
A02 A12+2
---------------------------≤
A03 aA1vin3( )0 AX3+=A13 aA1vin3( )1– AX3–=
CHAPTER 6 Measurement Results 88
the additional subscripts “0” and “1”, the same method for defining the output signals. Either
equation can be used to calculate AX3 and its worst case magnitude is
Taking the average we have
(6.7)
Based on equations (6.5) and (6.7), the worst case cascaded 2nd and 3rd harmonic distortion
performance is calculated from the measured data. The results are listed in Table 6.1, together
with simulation results of the cascaded 3rd harmonic distortions. The simulation is reasonably
close to the measurement.
It can be seen that excellent 2nd harmonic distortion performance is achieved. The 3rd har-
monic distortion is also satisfactory. The offset cancellation stage increases the nonlinearity
only slightly.
6.4 AGC Gain and Dynamics
AGC gain is measured at different input levels and frequencies. The results are shown in Fig-
ure 6.10. A close match between the measurement and the simulation is observed. Figure 6.11
shows the output level of the AGC under the same input conditions.
In Figure 6.12 and Figure 6.13, the measured and simulated AGC responses to a 1.6 kHz
input signal whose amplitude switches between 100 and 200 mV are plotted. A longer settling
Table 6.1 Cascaded harmonic distortions of the AGC, the LPF and the offset cancellation stage.a
a. As the LPF has a 2 dB attenuation at the 3rd harmonic (9.6 kHz), the measured output components at this fre-quency are compensated accordingly.
Input Level (dBV)
Cascaded Gain or Worst Case Harmonic Distortion
AGC LPF Offset Cancellation
Fundamental −13.72 6.03 dB (Gain) −0.314 dB (Gain) −2.76 dB (Gain)
2nd Harmonic −87.41 73.87 dBc, 0.020% 72.39 dBc, 0.024% 69.61 dBc, 0.033%
3rd Harmonic −91.88 59.46 dBc, 0.106% 49.30 dBc, 0.343% 48.63 dBc, 0.370%
Simulation (3rd) 65.90 dBc 47.85 dBc 45.88 dBc
AX3 A03 aA1vin3( )0+≤ or AX3 A13 aA1vin3( )1+≤
AX3
A03 A13 aA1vin3( )0 aA1vin3( )1+ + +2
-------------------------------------------------------------------------------------------≤
CHAPTER 6 Measurement Results 89
time is observed in the measurement, especially when responding to the rising input amplitude.
This can also be explained by a smaller charging current I0 of the peak detector (Figure 4.6 on
page 36), the same reason given in Section 6.1 when discussing the gain discrepancy of the
offset cancellation stage.
Figure 6.10. AGC gain at different input levels.
Figure 6.11. AGC output levels at different input levels.
−35 −30 −25 −20 −15 −10 −5 0 5−10
−5
0
5
10
15
20
Input Signal Amplitude [dBV]
AG
C G
ain
[dB
]
Simulated at 3.2 kHz Measured at 3.2 kHz Measured at 10.24 kHz
−35 −30 −25 −20 −15 −10 −5 0 5−16
−15
−14
−13
−12
−11
−10
−9
−8
−7
Input Signal Amplitude [dBV]
AG
C O
utpu
t [dB
V]
Simulated at 3.2 kHz Measured at 3.2 kHz Measured at 10.24 kHz
CHAPTER 6 Measurement Results 90
6.5 Clock Recovery
In Figure 6.14 the locking process of the clock recovery circuit is given. The test is done by
changing the reference voltage Vref of the VCO (Figure 5.27 on page 74) and observing the
output voltage VC (Vpmp here) of the charge pump. Vref is a square wave with 224 mV peak to
Figure 6.12. Measured AGC response to input amplitude variations. The input signal is at 1.6 kHz and has an amplitude switching between 100 and 200 mV.
Figure 6.13. Simulated AGC response to the input signal given in Figure 6.12.
10 20 30 40 50 60 70 80 90 100
−0.2
−0.1
0
0.1
0.2IN
PU
T [V
]
10 20 30 40 50 60 70 80 90 100
−0.5
0
0.5
OU
TP
UT
[V]
TIME [ms]
10 20 30 40 50 60 70 80 90 100
−0.2
−0.1
0
0.1
0.2
INP
UT
[V]
10 20 30 40 50 60 70 80 90 100
−0.5
0
0.5
TIME [ms]
OU
TP
UT
[V]
CHAPTER 6 Measurement Results 91
peak amplitude, which is equivalent to about 360 Hz frequency change. The uneven response
to the rising and falling steps of Vref is resulted from the fact that Vpmp (or VC) is initially at an
unknown voltage, most likely 0 volt. Therefore, to achieve a quick setting after power-on, Vref
is set to be relatively low. The momentary absolute voltage drop over the resistor of the charge
pump is thus different during charging and discharging. Also, as discussed in Section 5.5.4, the
correlation between the input and output of the PLL results in an non-ideal damping property.
Figure 6.15 shows the spectra of the clock signal, before and after it is locked.
6.6 Demodulation
In figures 6.16 to 6.20, measured input and output signals of the demodulator are given. Due to
the limited bandwidth of the SR780 FFT network analyzer, transition edges of the digital sig-
nals are not crisp enough. But this is not a critical issue as the signal frequency is very low. For
a comparison, the waveforms from the simulation are also depicted in Figure 6.21.
In Figure 6.19 we see a number of glitch-like pulses in the asynchronous direction signal.
These can be explained by the simulation results shown in Figure 6.22. As the transition detec-
tion reads only the pulse trains P0D and N0D (Figure 5.17 on page 66), errors could occur in the
alignment of the clock and the interpolated signals P1D and N1D (Figure A.18 on page 118).
Figure 6.14. Locking process of the clock recovery circuit.
0 10 20 30 40 50 60 70 80 90 1000
0.5
1
TIME [ms]
Vre
f and
Vpm
p [V
]
0 10 20 30 40 50 60 70 80 90 1000
0.1
0.2
0.3
0.4
Vre
f [V
]
CHAPTER 6 Measurement Results 92
When this happens, as shown in Figure 6.22, one pulse of N1D is mistakenly counted as a pos-
itive pulse after the reset signal (not shown in the figure) and results in the temporarily high
output level of the asynchronous direction. To solve this problem, the transition detection
should also take the interpolated pulses into account. Doing this the complexity will be
increased by a limited amount.
Figure 6.15. Spectra of the clock signal, before and after lock.
Figure 6.16. AGC I/Q input and LPF output waveforms.
1.5 2 2.5 3 3.5 4 4.5 5−120
−100
−80
−60
−40
−20
0
20
Frequency [kHz]
Mag
nitu
de [d
BV
]Free Runnning
Locked
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
1
1.1
1.2
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
1.8
1.9
2
AGC
I/Q In
put
LPF
I/Q O
utput
TIME [ms]
CHAPTER 6 Measurement Results 93
Figure 6.17. Signal Q1 (hard-limited version of the Q1 in Figure 5.1 on page 51).
Figure 6.18. Signal N1 (see also Figure 5.1 on page 51).
Figure 6.19. The asynchronous/synchronized direction signal.
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
Q1
CLO
CK
TIME [ms]
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
N1
CL
OC
K
TIME [ms]
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
CL
OC
K
TIME [ms]
Asyn
chro
nous
Dire
ctio
nC
LO
CK
Sync
hron
ized
Dir
ectio
n
CHAPTER 6 Measurement Results 94
6.7 Summary
Measurement results of the base-band circuits are summarized in Table 6.2. In Table 6.3 the
front-end performance is reported. For more information on the design and measurement of the
RF front-end please refer to [17] and [32]. The overall performance of the receiver is given in
Table 6.4.
Figure 6.20. The asynchronous/synchronized speed signal.
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
CLO
CK
TIME [ms]
Asyn
chro
nous
Spe
edC
LO
CK
Sync
hron
ized
Sp
eed
CHAPTER 6 Measurement Results 95
Figure 6.21. Simulated demodulator input and output waveforms in a 5 ms interval.
LPF Output I
LPF Output Q
Cloc
kQ1
N1Di
recti
on(A
sync
hrono
us)
Spee
d(A
sync
hrono
us)
Dire
ction
(Syn
chron
ized)
Spee
d(S
ynch
ronize
d)
CHAPTER 6 Measurement Results 96
Figure 6.22. The incomplete transition detection and its effect on the demodulation.
Table 6.2 Performance summary of the base-band circuit.
AGCMax.: 18.6 dB, Min.: N/A
HD2 ≤ 0.02%, HD3 ≤ 0.106%
LPF
Pass-band: gain −6.2 dB, ripple ≤ 0.5 dB (≤ 9 kHz)
Stop-band: attenuation ≥ 63 dB (≥ 17.8 kHz)
HD2 ≤ 0.024%, HD3 ≤ 0.343% (cascaded)
Offset Cancellation
Gain: −2.5 dB
Output offset < 2 mV (under ±100 mV input offset)
HD2 ≤ 0.033%, HD3 ≤ 0.37% (cascaded)
Input Referred Noise 600 nV/√Hz at 10 kHz
Clock Recovery Capture range > 550 Hz
Power Dissipation 5.4 mW (including all buffers)
Table 6.3 Performance summary of the front-end.
with off-chip matching inductor with on-chip matching inductor
Gain 51.1 dB 43.3 dB
Noise Figure at 100kHz 5.8 dB 15.0 dB
IIP3 −26.0 dBm −20.7 dBm
P0d
N0d
P1d
N1d
Cloc
kDi
recti
on(A
sync
hrono
us)
TIME
a mis-counted pulse
CHAPTER 6 Measurement Results 97
IIP2 −10 dBm −5.6 dBm
Operating Frequency 930 MHz
LO Frequency 465 MHz
I/Q Gain Mismatch < 0.3 dB
I/Q Phase Mismatch < 5°
Self-mixing Rejection > 54 dB
Input Matching (S11) < −20 dB
Power Dissipation 52.76 mW
Table 6.4 Summary of the whole receiver (off-chip matching inductor).
Process 0.35 µm 2P4M N-well CMOS
Die Size 1128 × 3955 µm2 (including pads)
Power Supply 3.0 V
Maximum Gain 62 dB (excluding the hard-limiter stage)
Noise Figure at 10 kHz 14.5 dB (including the loss of the balun)
IIP3 > −38.0 dBm
IIP2 > −11.0 dBm
Power Dissipation 58 mW
Table 6.3 Performance summary of the front-end.
CHAPTER 7Future Work and Conclusion
In the first two chapters, the backgrounds of high speed paging systems, the concept of direc-
tion-conversion and the FSK modulation format as well as different demodulation techniques
are introduced. A high-level analysis is then presented in the third chapter, followed by two
chapters of discussions on the design of the prototype circuit.
In chapter 3, the high-level analysis is preformed under the assumption that the receiver
performance is determined only by the RF front-end while the base-band circuit is ideal and
the demodulator is nearly perfectly synchronized. It thus provides an upper bound of the per-
formance. When mapped to a real circuit, the high-level model has to be revised to accommo-
date imperfections of the base-band. Problems come mainly from the following aspects:
1. the DC offset caused by device mismatch,
2. raised noise floor and lowered linearity due to the active implementation of the originally
passive channel selection filter,
3. further degradation of the signal to noise ratio contributed by the flicker noise.
The situation is especially serious in the CMOS technology as it is not optimized for analog
applications. Although these imperfections can never be eliminated, their impacts can be mini-
mized by means of receiver architecture optimization and circuit design techniques. In the fol-
lowing sections some possible improvements are first discussed, which are also the directions
of our future work. The whole dissertation is then concluded by a summary of the design.
98
CHAPTER 7 Future Work and Conclusion 99
7.1 Possible Improvements
Based on the experience gained from and the mistakes made in the design of the prototype
receiver, we believe that there are considerable space left for the performance improvement.
Some of the possible approaches are described below.
7.1.1 DC Offset Cancellation
The DC offset problem is still the first concern in the design of a direct-conversion receiver. It
is not simply a circuit issue but also a system-related problem. Therefore, besides the discus-
sion in Section 4.5, a more comprehensive consideration which includes the analysis of the sig-
nal structure is necessary.
Although at its highest data rate of 6400 bps the FLEX signal goes to 4FSK and contains
significant DC and low frequency spectral components, it does sometimes run at only 1600
bps, in the form of binary FSK. Recall the FLEX signal structure given in Section 1.1.2, this
actually occurs at the synchronization portion of each data frame. The synchronization portion
is used for frame lock but is potentially useful in offset cancellation.
As the modulation index of a 2FSK 1600 bps signal is 6, it doesn’t have any power at DC.
The shape of its spectrum is comparable to the that of the 1200 bps POCSAG signal. Thus it
can be safely demodulated with AC-coupling. And it is possible to perform the offset cancella-
tion frame by frame. This can be done in a two-path operation mode. The first path is a DC
path where all the stages are DC-coupled such that the low frequency energy of the signal is
preserved. In the second path AC-coupling is used to block DC and low frequency compo-
nents. The operation proceeds in two steps. At the beginning of a frame, the synchronization
signal will go through both paths. The outputs are compared to each other to calculate the
effective offset level. The result is then stored for future reference. If the data blocks are also at
1600 bps, the DC path can be shut down for power saving. Otherwise, the AC path is shut
down and the signal is processed in the DC path, with the stored offset level subtracted. This
scheme should work very well with the mismatch-induced static offset. However, as each
frame lasts for 1.875 seconds long, it may not be effective enough to handle the dynamic or
time-varying offset produced by the mixing process. This is where the harmonic mixer or
adaptive mixers can help.
CHAPTER 7 Future Work and Conclusion 100
7.1.2 System Noise Figure and Gain Distribution
The noise contributed by the base-band circuits, especially the active channel selection filter,
can dominate the system noise figure. Therefore the noise and gain distribution of the filter
section must be optimized [46]. Suppose the total input referred noise voltage spectral density
of the AGC and the channel selection filter is 50 nV/√Hz after the optimization and the overall
gain and NF of the RF front-end are 40 dB and 6.2 dB respectively, the system noise figure will
be about 7.3 dB. This is about 2.1 dB higher than the expected value given in chapter 3 but is
still a decent number.
It would also be interesting to have a look at a possible gain distribution plan. If the LNA
gain can be switched between 0 and 20 dB according to the input signal level, the AGC pro-
vides 0 to 40 dB gain range and the filter has 20 dB fixed gain, the output signal amplitude at
different input levels is given in Table 7.1.
7.2 Conclusion
In this dissertation the design of a direct-conversion radio receiver for high speed paging is
described. The system architecture and circuit design issues are discussed and a prototype
receiver is built. Our motivations come from the wide acceptance of the new high speed radio
paging protocol FLEX and the successful implementation of the direct-conversion scheme in
the POCSAG paging system. Advantages of direct-conversion are apparent: very high integra-
tion level, less components to tune and possible low complexity and low power consumption.
DC offset is a problem every direct-conversion receiver designer has to face. It can be sim-
ply removed by AC-coupling, just like what is usually done in discrete circuit designs, as long
as the loss of the signal energy is negligible or affordable. This is the scheme applied in the
direct-conversion POCSAG receiver. Because of the upgraded data rate and hence lowered
modulation index, it is not a practical option in the high speed system. To solve this problem,
Table 7.1 Possible gain distribution and signal levels.
Input LevelGain Distribution Output
AmplitudeFront-End AGC Filter
-120 dBm +40 dB +30 dB +20 dB 10 mV
-80 dBm +40 dB +10 dB +20 dB 100 mV
-40 dBm +20 dB −10 dB +20 dB 100 mV
CHAPTER 7 Future Work and Conclusion 101
the harmonic mixer is proposed to minimize the self-mixing-related offset. About 37.5 dB off-
set cancellation has been achieved and the input-referred offset level is close to the noise level.
More complicated structures are needed to cancel static offset which is caused by device mis-
match. The differential peak alignment method is developed for this purpose. With an accept-
able amount of distortion and attenuation, the output offset level is limited to the rectifier’s
own mismatch and is no more than several mili-volts, which is about the equivalent input off-
set of a simple differential pair. Based on the analysis of the FLEX signal structure, a more sys-
tematic offset cancellation approach is also proposed in this chapter as an option. It is thus a
reasonable assumption that the DC offset can be suppressed to a safe level such that the
demodulation can be done without taking it into consideration.
A high level simulation is carried out to evaluate the performance of the zero-IF zero-cross-
ing (ZIFZCD) demodulator and to derive circuit requirements of the direct-conversion
receiver. The ZIFZCD is designed for demodulating zero-IF digital frequency-modulated sig-
nals. With the zero-crossing interpolation (ZCI) technique, it is capable of processing signals
with low modulation indices. According to the simulation, 1% BER can be achieved at about
13.8 dB ES/N0 ratio if 1-level interpolation is used. That is an improvement of 1.5 dB when
compared to the case of zero interpolation. If all the noise and nonlinearites are lumped to the
RF front-end, a −120 dBm sensitivity can be achieved with about 5.2 dB noise figure. When
deriving appropriate circuit requirements, official specifications on radio paging receivers are
followed and design margins are reserved.
The prototype receiver is fabricated in a 0.35 micron CMOS process. All major building
blocks are included. The LNA and the harmonic mixer are designed by two of my colleagues.
An AGC stage and a gyrator filter are responsible for the base-band amplification and
channel selection. As an option, the rectifier-based offset detector is also added. The AGC has
about 40 dB gain range and very high linearity. However, due to the cross-coupled structure
used in the VGA, its input-referred noise voltage spectral density is about 250 nV/√Hz. This
can be alleviated by a pre-amplifier stage. The main problem of the low pass filter is also high
input-referred noise, which is about 700 nV/√Hz, mainly due to the inherent 6 dB loss of the
LC ladder from which the gyrator filter is derived. An optimization of gain and noise distribu-
tion is necessary to tackle this problem. Other filter structures may also be considered as alter-
natives.
CHAPTER 7 Future Work and Conclusion 102
The demodulator consists of a 1-level zero-crossing interpolator, decision logics and a
clock recovery loop. Zero-crossings of the I and Q components of the zero-IF signal are
detected and converted to (nominally) positive and negative pulses according to their phase
offset. These pulses are counted and compared by the decision logic circuit to recover the data.
Timing of the demodulator is provided by the clock recovery circuit which detects data transi-
tions by observing the change of pulses’ polarities.
The prototype receiver verified the function of the design at the same time showed us the
ways to further improvements.
References
[1] Motorola, Inc., “FLEX Technologies” [On line]. Available: http://www.mot.com/MIMS/MSPG/FLEX/ [2000, April 10].
[2] Motorola, Inc., “FLEX Signal Overview”, MC68181 Technical Data Sheet, Appendix A. May, 1998.
[3] B. Razavi, “Design Considerations for Direct-Conversion Receivers,” IEEE Tran. Circuits Syst. II, Vol. 44, No. 6, pp. 428-35, June 1997.
[4] I.A.W. Vance, “An Integrated Circuit V.H.F. Radio Receiver”, The Radio and Electronic Engineer, Vol. 50, No. 4, pp. 158-64, Apr. 1980.
[5] I.A.W. Vance, “Fully Integrated Radio Paging Receiver”, IEE Proc., Vol. 129, Pt. F, No. 1, pp. 2-6, Feb. 1982,.
[6] John F. Wilson, Richard Youell, Tony H. Richards, Gwilym Luff, and Ralf Pilaski, “A Single-Chip VHF and UHF Receiver for Radio Paging”, IEEE J. Solid-State Circuits, Vol. 26, No. 12, pp. 1944-1950, Dec. 1991.
[7] Masaya Saitou, Mika Kawabata and Yoshihiko Akaiwa, “Direct conversion receiver for 2- and 4-level FSK signals”, 4th IEEE international conference on universal personal communications, pp. 392-396, 1995.
[8] M. Mimura, K. Abe, M. Hasegawa and H. Katayama, “The direct-conversion receiver for a fast multilevel FSK”, IEICE Japan national spring convention B-448, Mar. 1995.
[9] Kazuaki Takahashi, et al., “A direct conversion receiver utilizing a novel FSK demodulator and a low power consumption quadrature mixer”, Vehicular Technology Society 42nd VTS Conference. (1992) p910-15 vol.2.
[10] Christopher Dennis Hull, Joo Leong Tham and Robert Ray Chu, “A direct-conversion receiver for 900 MHz (ISM band) spread-spectrum digital cordless telephone”, IEEE J. Solid-State Circuits, Vol. 31, No. 12, pp. 1955-1963, Dec. 1996.
[11] J. Craninckx, et. al., “A Fully-Integrated Zero-IF DECT Transceiver,” 2000 IEEE International Solid-State Circuits Conference, Feb. 2000.
103
References 104
[12] A. Jayaraman, et. al., “A Fully-Integrated Broadband Direct-Conversion Receiver for DBS Applications,” 2000 IEEE International Solid-State Circuits Conference, Feb. 2000.
[13] A.A. Abidi, “Direct-Conversion Radio Transceivers for Digital Communications”, IEEE J. Solid-State Circuits, Vol. 30, No.12, pp1399-410, Dec. 1995.
[14] H. M. Kwon and K.B. Lee, “A Novel Digital FM Receiver for Mobile and Personal Communications”, IEEE Tran. Commun, Vol. 44, No. 11, pp. 1466-1476, Nov. 1996.
[15] Zhiheng Chen, Jack Lau, “Direct Conversion for FLEX Paging Receivers—A Feasibility Study,” 1998 IEEE RFIC Symp. Dig., Baltimore, MD, pp. 293-296.
[16] Zhiheng Chen, Jack Lau, “Circuit Requirements of A Direct Conversion Paging Receiver,” IEEE Tran. Circuits Syst. II, Vol. 46, No. 6, pp. 802-807, June 1999.
[17] Zhaofeng Zhang, Zhiheng Chen, Louis Tsui and Jack Lau, “A 930MHz CMOS DC-Offset-Free Direct-Conversion 4-FSK Receiver,” to be presented on the 2001 IEEE International Solid-State Circuits Conference (ISSCC).
[18] Zhaofeng Zhang, Zhiheng Chen and Jack Lau, “A 900MHz CMOS Balanced Harmonic Mixer for Direct Conversion 4-FSK Pager Receiver,” submitted to the IEEE J. Solid-State Circuits.
[19] Zhiheng Chen, Zhaofeng Zhang and Jack Lau, “A Novel CMOS Digital 4FSK Demodulator for Direct-Conversion High Speed Radio Paging Receivers,” submitted to the 2001 IEEE Custom Integrated Circuits Conference.
[20] Sergio Benedetto, Ezio Biglieri and Valentino Castellani, Digital Transmission Theory, pp. 232-239, Prentice Hall, 1987.
[21] J.G. Proakis, Digital Communications, 3rd ed. pp. 301-13, McGraw-Hill, 1989.
[22] B. Sklar, Digital Communications: Fundamentals and Applications, pp. 150-52, Prentice-Hall, 1988.
[23] Paul. H. Young, Electronic Communication Techniques, 3rd ed. pp. 368-70, Merril.
[24] E.A. Richley, “Design of Quadrature Detectors”, RF Design, pp. 68-72, May 1991.
[25] E.K.B. Lee, “Zero-Crossing Zero-IF Demodulator”, Electronics Letters, Vol. 31, No. 15, pp. 1218-19, July 1995.
[26] OFTA Hong Kong, Performance Specification for VHF Transmitters and Receivers for Use in the Public Paging Service, HKTA 1004, Issue 3, July 1993. URL: http://www.ofta.gov.hk/transdoc/hkta1004.doc.
[27] The Ministry of Post and Telecommunications of China, Specifications and Their Testing Methods of Radio Paging Receivers, in Chinese, Beijing: The Standards’ Publishing House of China, Aug. 1998.
[28] Philips Semiconductors, Pager Application Handbook, 1995, pp. VI-41 to 42.
[29] T.L. Fu, “Optimize The Performance of Pager Antennas,” Microwaves & RF, Aug. 1994, pp. 141-147.
References 105
[30] Q. Huang and P. Basedau, “Design Considerations for High-Frequency Crystal Oscillators Digitally Trimmable to Sub-ppm Accuracy,” IEEE Trans. VLSI Syst., Vol. 5, No. 4, pp. 408-416, Dec. 1997.
[31] P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd edition, New York: Wiley, 1993.
[32] Zhaofeng Zhang, Zhiheng Chen and Jack Lau, “A 900 MHz CMOS Balanced Harmonic Mixer for Direct Conversion Receivers,” IEEE Radio and Wireless Conference, Sep. 2000.
[33] Takafumi Yamaji, Hiroshi Tanimoto, “A 2GHz Balanced Harmonic Mixer for Direct-Conversion Receivers”, Proc. of IEEE Custom IC Conf., pp193-6, May, 1997.
[34] J. Chang, A. Abidi and C. Viswanathan, “Flicker Noise in CMOS Transistors from Subthreshold to Strong Inversion at Various Temperatures,” IEEE Trans. Electron Devices, Vol. 41, No. 11, pp. 1965-1971, Nov., 1994.
[35] Sergio A. Sanielevici et al., “A 900-MHz Transceiver Chipset for Two-Way Paging Applications”, IEEE J. Solid-State Circuits, vol. 33, No. 12, Dec 1998.
[36] Paul J. Chang, Ahmadreza Rofougaran and Asad A. Abidi, “A CMOS Channel-Select Filter for a Direct-Conversion Wireless Receiver,” IEEE J. Solid-State Circuits, vol. 32, No. 5, pp. 722-729, May 1997.
[37] Yannis P. Tsividis, “Integrated Continuous-Time Filter Design — An Overview,” IEEE J. Solid-State Circuits, vol. 29, No. 3, pp166-176, March, 1994.
[38] K. Yamasaki, et al., “Compact Size Numeric Display Pager with New Receiving System,” NEC Research and Development, vol. 33, No. 1, pp. 73-81, Jan 1992.
[39] F. Krummenacher and N. Joehl, “A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning,” IEEE J. Solid-State Circuits, vol. 23, No. 3, pp. 750-758, June 1988.
[40] Arthur B. Williams & Fred J. Taylor, Electronic Filter Design Handbook: LC, Active, and Digital Filters, 2nd edition, New York: McGraw-Hill, 1988.
[41] P.A. Moore, “High-Performance Integrated Audio-Frequency Gyrator Filters,” IEE 1985 Saraga Colloquium on Electronic Filters, pp. 6/1-6, London: IEE, 1985.
[42] M. Bazes, “Two Novel Full Complementary Self-Biased CMOS Differential Amplifiers,” IEEE J. Solid-State Circuits, vol. 26, No. 2, pp. 165-168, Feb., 1991.
[43] Sony Electronics Inc., CXA1994AM/BM M-ary FSK Demodulating Comparator, data sheet, Rev. E96428-TE.
[44] E.K.B. Lee, C. Powell and H. Kwon, “A Novel Wireless Communication Device and Its Synchronization Scheme,” IEEE GLOBECOM’95, vol. 1, pp 659-63, 1995.
[45] B. Razavi, “Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits—A Tutorial,” Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design, New York: IEEE Press, 1996.
References 106
[46] A. Rofougaran, et. al., “A Single-Chip 900-MHz Spread-Spectrum Wireless Transceiver in 1-mm CMOS—Part II: Receiver Design,” IEEE J. Solid-State Circuits, Vol. 33, No. 4, pp. 535-547, April 1998.
APPENDIX ACircuit Details
Detailed schematics of the prototype receiver are included in this appendix in a hierarchical
way. At the top level, there are the AGC loop, the low pass filter, the demodulator with clock
recovery, as well as biasing and buffering circuits. After the introduction of each block, its sub-
circuits will then be given. This process continues until the transistor level or the gate level is
reached. In some cases, parameters of a sub-circuit could be variables for the sake of flexibil-
ity. Real values should then be provided when the sub-circuit is called.
All the schematics are created in the Analog Artist environment while the simulation is
done using HSPICE for higher efficiency. To keep the consistency between the schematic and
the generated netlist, characters “x” and “_” are used to replace the signs “+” and “−” of a dif-
ferential signal. For example, the differential signal in is expressed as the signal pair (inx, in_)
instead of (in+, in−). But the signs are still used in most of the symbol views.
107
APPENDIX A Circuit Details 108
A.1 The AGC Loop
The schematic of the AGC loop is shown in Figure A.1, the whole structure is the same as
what is described in Section 4.3 except that another differential variable resistor Rin2 is included
for testing purpose. All the components/sub-circuits are listed in Table A.1.
Figure A.1. The AGC loop.
APPENDIX A Circuit Details 109
A.1.1 The Differential Variable MOS Resistor (DiffRes)
A.1.2 The OPAMP (Opamp1)
Figure A.2. The differential variable MOS resistor.
Figure A.3. The OPAMP.
APPENDIX A Circuit Details 110
The Common-Mode Feedback Circuit (CMFBa)
The Buffer Used in The CMFB Circuit (Buffer1)
Figure A.4. The CMFB circuit used in the OPAMP.
Figure A.5. The CMFB buffer.
APPENDIX A Circuit Details 111
A.1.3 The Peak Detector (Rect2)
A.1.4 The Attenuator (LinAmp)
Figure A.6. The negative peak detector.
Figure A.7. The attenuator and the source follower used in the AGC loop.
APPENDIX A Circuit Details 112
A.2 The Low Pass Filter (Gyt5)
A.2.1 The Gm Cell (Gm)
A.3 Offset Cancellation
Figure A.8. The 5th order gyrator-type elliptic filter.
Figure A.9. The linearized Gm cell.
Figure A.10. A simple offset cancellation method making use of a peak detector and an adder.
+
−
+
−Rect2
+
−
+
−Iadd_2
+
−
−
input output
APPENDIX A Circuit Details 113
A.4 The Demodulator
Figure A.11. The demodulator.
APPENDIX A Circuit Details 114
A.5 Zero-Crossing Interpolators and Pulse Generators
Figure A.12. The zero-crossing interpolator, hard-limiters and zero-crossing pulse generators.
APPENDIX A Circuit Details 115
A.5.1 The Adder (Iadd_2)
A.5.2 The Limiter (Limiter)
Figure A.13. The adder.
Figure A.14. The limiter.
APPENDIX A Circuit Details 116
The First 2 Stages of The Limiter: Amp_L1, Amp_L2
The Self-biased Amplifier (AmpS)
Figure A.15. The first 2 stages of the limiter.
Figure A.16. The self-biased amplifier.
(a) Amp_L1 (b) Amp_L1
APPENDIX A Circuit Details 117
A.5.3 The Zero-Crossing Pulse Generator (PUL_Gen)
Figure A.17. The zero-crossing pulse generator.
APPENDIX A Circuit Details 118
A.6 Clock Recovery
Figure A.18. The clock recovery block.
APPENDIX A Circuit Details 119
A.6.1 The Delay Element (CRC_delay)
A.6.2 The Transition Detector (CRC_RS)1
Figure A.19. The delay element.
Figure A.20. The transition detector (the output stage excluded).
1. The output stage excluded.
APPENDIX A Circuit Details 120
The AC Block of The Transition Detector (CRC_AC)
The AOA Block Of The Transition Detector (CRC_AOA)
The “11” Detector of The Transition Detector (CRC_c2)
Figure A.21. The AC block of the transition detector.
Figure A.22. The AOA block of the transition detector.
Figure A.23. The “11” detector.
Mp: 1/15Mn0: 1/1
others: 1/0.4
APPENDIX A Circuit Details 121
A.6.3 The Phase Detector (CRC_PD)
A.6.4 The Charge Pump Circuit(CRC_pump)
Figure A.24. The phase detector.
Figure A.25. The charge pump circuit.
APPENDIX A Circuit Details 122
A.6.5 The VCO (CRC_v2i and CRC_ico)
A.7 The Decision Logic (DEMOD)
Figure A.26. The VCO circuit.
Figure A.27. The decision logic of the demodulator.
APPENDIX A Circuit Details 123
A.7.1 The Zero-Crossing Counter (Counter)
A.7.2 The Direction Comparator
A.7.3 The speed comparator
Figure A.28. The zero-crossing counter.
Figure A.29. The direction comparator.
Figure A.30. The speed comparator.
APPENDIX A Circuit Details 124
A.8 Building Blocks Using The Transmission Gate Logic
The transmission gate (TG) logic is used in some of the basic logic gates, flip-flops and multi-
plexors. Schematics and symbols of these building blocks are shown in the following figures.
Figure A.31. Transmission gate based logic gates and their symbols.
Figure A.32. The basic D flip-flop.
Figure A.33. The resetable D flip-flop.
AA X=ABB
AA X=A+BB
AA X=A⊕BB
(a) AND gate (b) OR gate (c) XOR gate
CLK
CLKb
D Q
DFF-0
Qb
CLK
D Q
R-DFF
QbRESET
APPENDIX A Circuit Details 125
A.9 Biasing Circuits and Buffers
Operation points of the AGC and the low pass filter are set by the threshold voltage referenced
current source, as shown in Figure A.35. The bias current can be tuned by an external resistor
at the RX node. Circuits of the demodulator, i.g. the ZCI, the limiters and the VCO, are biased
separately by a simple circuit which consists of only two gate-drain connected transistors.
Again, the bias current is controlled by an external resistor connected between vp and vn. The
schematic is given in Figure A.36.
All output signals, analog or digital, are buffered before going off chip. The analog buffer is
formed by two source followers and their biasing circuit. The digital buffer is a cascade of two
inverters with increasing driving power.
A.10 List of Components
Table A.1 serves as a complete list of the components used in the design. In the first two col-
umns the parent cell and its components are given. In the third column the sub-circuit name of
the components can be found. A sub-circuit may have one or more parameters to fill in when it
is used as a component. If the component is an MOS transistor, the third column is empty and
there are two types of parameters: the W/L ratio in microns and the element multiplier M.
Figure A.34. The 2 to 1 multiplexor (MUX21) and the 4 to 2 multiplexor (MUX42).
APPENDIX A Circuit Details 126
Figure A.35. The threshold voltage referenced current source (cell: iRefVth).
Figure A.36. The simple circuit for biasing the demodulator (cell: iRefSimp).
APPENDIX A Circuit Details 127
Figure A.37. The analog buffer (cell: follow).
Figure A.38. The digital buffer (cell: driver).
APPENDIX A Circuit Details 128
Table A.1 List of components.
Cell Components Sub-circuit Parameters Notes
AGC
Rin1, Rin2, Rf DiffRes_R=20kΩ, _w=10µm, _l=4µm
linear resistors
OPAMP Opamp1
Rect2 Rect2 peak detector
sh1, sh2 psh _w=10µm, _l=2µm source followers
sh3, sh4 psh _w=10µm, _l=9µm source followers
Gm Gm
LinAmp LinAmp attenuator
Amp_L1
R1, R2 30 kΩ
M1, M2 W/L=10/2, M=10 NMOST
Mn W/L=10/2, M=6 NMOST
Amp_L2
ML1, ML2 W/L=5/15, M=1 NMOST
M1, M2 W/L=10/2, M=8 NMOST
Mn W/L=10/2, M=2 NMOST
AmpS
M1, M3 W/L=3/2, M=1 PMOST
M2, M4 W/L=3/2, M=1 NMOST
M5 W/L=4.8/2, M=2 PMOST
M6 W/L=3/8, M=1 NMOST
Buffer1
Mb W/L=10/2, M=1 PMOST
M1, M2 W/L=4/1, M=1 PMOST
M3, M4 W/L=2/10, M=1 NMOST
CMFBa
abuf1, abuf2 Buffer1
R1, R2 60 kΩ
Mb, Mb0 W/L=10/2, M=1 PMOST
Ma1, Ma2 W/L=10/1, M=1 PMOST
Ma3, Ma4 W/L=5/5, M=1 NMOST
MC0 W/L=3/7.2, M=1 NMOST
CRC
CRC_RS CRC_RS transition detector
DP1, DN1 CRC_delay
CRC_PD CRC_PD phase detector
Pump CRC_pump charge pump
CRC_v2i CRC_v2itransconductor+ current mirror
CRC_ico multi-vibrator
MUX21 MUX21 clock selection
APPENDIX A Circuit Details 129
CRC_delay see schematic
CRC_ico
C0 10.15 pF
M1, M2 W/L=5/1, M=2 NMOST
M3, M4 W/L=1.6/6.4, M=1 NMOST
M5, M6 W/L=10/2, M=1 NMOST
AmpS AmpS self-biased amplifier
CRC_PD see schematic
CRC_pump
MP W/L=9.2/2, M=1 PMOST
MP1 W/L=1/0.4, M=1 PMOST
MN1 W/L=1/0.4, M=1 NMOST
MN W/L=10/2, M=1 NMOST
CRC_RS see schematic
CRC_v2i
Mbp1, Mbp2 W/L=4/2, M=1 PMOST
M11, M12 W/L=4/4, M=1 PMOST
M21, M22 W/L=2/12, M=1 PMOST
Mn1, Mn2 W/L=4/2, M=1 NMOST
Mbp3 W/L=10/2, M=1 PMOST
M3 W/L=4/4, M=1 PMOST
Mbn W/L=10/2, M=1 NMOST
DEMOD see schematic
DEMOD_PN
add0, add1 Iadd_2
LI0, LQ0, LI1, LQ1 Limiter
PUL0, PUL1 PUL_Gen
Demodulator
DEMOD_PN DEMOD_PN ZCI + pulse generator
CRC CRC clock recovery circuits
DEMOD DEMOD decision logic
DiffResR1, R2 resistance = _R
M1, M2, M3, M4 W/L=_w/_l, M=1 NMOST
driver (digital buffer)
Mp0 W/L=3/0.4, M=2 PMOST
Mp1 W/L=3/0.4, M=10 PMOST
Mn0 W/L=1/0.4, M=2 NMOST
Mn1 W/L=1/0.4, M=10 NMOST
Table A.1 List of components.
Cell Components Sub-circuit Parameters Notes
APPENDIX A Circuit Details 130
follow (analog buffer)
Mbp1, Mbp2, Mb1, Mb2
W/L=5/1, M=1 PMOST
Mbn W/L=3/1, M=1 NMOST
M1, M2 W/L=5/1, M=4 PMOST
Gm
Mc1, Mc2 W/L=4/4, M=1 PMOST
Mp1, Mp2 W/L=10/1, M=3 PMOST
M11, M12 W/L=10/10, M=1 PMOST
M21, M22 W/L=3/18, M=1 PMOST
MN11, MN12 W/L=10/20, M=1 NMOST
Iadd_2
MBP1, MBP2, MBP3, MBP4
W/L=10/2, M=2 PMOST
M11, M12, M21, M22 W/L=5/2, M=1 PMOST
MN1, MN2 W/L=10/7, M=1 NMOST
Rs1, Rs2 20 kΩ
Rc1, Rc2 20 kΩ
iRefVth
M01, M02 W/L=10/1, M=10 NMOST
M03, M04 W/L=10/2, M=1 PMOST
M1 W/L=5/5, M=1 PMOST
M2, M4 W/L=10/20, M=1 NMOST
M3 W/L=4/4, M=1 PMOST
M5 W/L=10/1, M=3 PMOST
M6 W/L=10/10, M=1 PMOST
M7 W/L=2.4/20, M=1 NMOST
M8 W/L=5/5, M=10 PMOST
Limiter
Amp1 Amp_L1
Amp2 Amp_L2
Amps AmpS
LinAmp
Mp1, Mp2 W/L=10/2, M=1 PMOST
M11, M12 W/L=4/4, M=1 PMOST
M21, M22 W/L=2/14, M=1 PMOST
Mc1, Mc2 W/L=3/12, M=1 NMOST
MN11, MN12 W/L=5/10, M=1 NMOST
Table A.1 List of components.
Cell Components Sub-circuit Parameters Notes
APPENDIX A Circuit Details 131
Gyt5
C1 54.66 pF
C2, C2_ 7.06 pF
CL2 55.96 pF
C3 85.0 pF
C4, C4_ 19.25 pF
CL4 49.41 pF
C5 49.38 pF
Gm Gm
MUX21 see schematic
MUX42 see schematic
Opamp1
M7, M82, M9 W/L=10/2, M=2 PMOST
M1, M2 W/L=10/2, M=4 PMOST
M3, M4 W/L=10/5, M=1 NMOST
M5, M6 W/L=10/2.5, M=1 NMOST
Rc1, Rc2 6.4 kΩfor compensation
Cc1, Cc2 1.0 pF
CMFBa CMFBa
pshMb W/L=10/2, M=2 PMOST
Mp W/L=_w/_l, M=1 PMOST, VBS=0
PUL_Gen see schematic
Rect2
M1, M18 W/L=10/2, M=2 PMOST
M2, M3, M16, M17 W/L=20/2, M=2 PMOST
M4, M5, M14, M15 W/L=20/2, M=1 NMOST
M6, M9 W/L=5/5, M=1 PMOST
M7, M8, M77, M88, M10, M11, M12, M13
W/L=10/2, M=1 NMOST
Table A.1 List of components.
Cell Components Sub-circuit Parameters Notes
APPENDIX BBase-band Testing
This appendix provides information on the testing of the base-band circuitry. The pin assign-
ment is first described. A testing circuit is then given with the layout of its printed circuit board
(PCB). The equipments and testing setup used in the measurement are also introduced. And
finally the typical DC operation points are tabulated for reference.
B.1 Pin Assignment
A total of 53 pins are occupied by the base-band circuitry. Among them the last four (50-53)
are bonded to four internal pads which connect the mixer and the AGC. The bonding was done
with the RF front-end sliced off. The name and description of each pin are listed in Table B.1.
Figure B.1. Pin assignment diagram of the base-band circuits.
121
29 49
53
28
AGCI
AGCQ
Bias(iRefVth)
LPFI
LPFQ
OffsetCancel.
OffsetCancel.
Bias(iRefSimp)
MU
X42
MU
X42
Zero
-cro
ssin
gIn
terp
ola
tion
ClockRecoveryMUX21
Deci
sion
clock
50
22
RF
front-endbase-band
133
APPENDIX B Base-band Testing 134
B.2 The Testing Circuit
Figure B.2 is a suggested testing circuit diagram. All the external resistors and capacitors and
their values are listed in Table B.2. The size of 1206 is used for capacitors and fixed resistors.
A 2-layer printed circuit board is designed for the testing circuit. Figure B.3 shows the layout
of the PCB. On the top side, devices VDD, VDC, CLKEXT, INPUTS, OUTPUTS0,
OUTPUTS1, OUTPUTS2, DIGIOUT0, DIGIOUT1 are all connectors. Notice that the node
Table B.1 Pin assignment of the base-band circuits
Pin Number(s) Pin Name(s) Description
1, 2, 49, 48 vpxi, vp_i, vpxq, vp_qextra input ports to the AGC, for testing purpose only, normally biased at 1.1 V DC voltage.
3, 4 Axi, A_i differential output of the I-channel AGC stage
5, 45 Vrefi, Vrefq AGC reference voltages
6, 44 Vpki, Vpkq external capacitors for AGC peak detectors
7, 8, 43, 42 int_i, inxi, int_q, intxq external capacitors for AGC integrators
9, 19, 32, 41 vdd! 3 V power supply
10, 29, 33, 40 gnd! ground
11, 12, 39, 38 gxq, g_q, gxi, g_i differential outputs of the low pass filters
13, 14, 37, 36 p_q, pxq, p_i, pxi external capacitors for offset cancellation peak detectors
15 SS offset cancellation selection
16 Vrefd reference voltage of the VCO (clock recovery PLL)
17 Vpmp charge pump output
18 Fo clock recovery output
20 CLKExt external clock input
21 SelExt external clock enable
22 Q1 one of the hard-limited ZCI outputs
23 N1 one of the zero-crossing pulse trains
24 S minor adjustment of the speed comparator
25, 26 spd, dir speed and direction output, synchronous
27, 28 Adir, Aspd speed and direction output, asynchronous
30, 31 vn1!, vp1! external biasing resistor
34, 35 o_i, oxi I-channel offset cancellation output
46 bp1! stabilization capacitor for biasing circuit iRefVth
47 Rx external biasing resistor
50, 51, 52, 53 qinx, qin_, iin_, iinx differential I/Q inputs, zero-IF
APPENDIX B Base-band Testing 135
Figure B.2. The testing circuit.
iinx
iin_
qinx
qin_
Vdc
Rrefa
Rxa1
Cbp1
Rxa2
vdd
Cpkq
Cintq
Cpq+
Cpq−
vdd
Cpki
Cinti
Cpi+
Cpi−
vdd
Rxd1
Rxd2
Rs1
Rs2
Rs3
Rs4
exte
rnal
cloc
k
CL
KE
xtS
elE
xtS S
S
vdd
CLKExtSelExt
VrefdSS
S
Q1
N1
spd
dir
Adi
rA
spd
o_ioxi
pxi
p_i
g_i
gxi
switc
hes
A_iAxi
pxq
p_q
g_q
gxq
CpmpFo
Rpmp1
Rpmp2
Vrefa
Rra
RrefdRrd
Vre
fdV
refa
APPENDIX B Base-band Testing 136
Va, which is the via close to the connector OUTPUTS0, is the abbreviation of Vrefa, the refer-
ence voltage for both AGCI and AGCQ.
Figure B.3. The PCB designed for the base-band testing circuit. The size is 98.5mm×123.6mm.
(a) The top layer (b) The bottom layer
(c) Devices on the top side (d) Devices on the bottom side
the die
APPENDIX B Base-band Testing 137
B.3 Testing Setup
Depending on the purpose of the measurement, different signal sources should be used and dif-
ferent signal analyzers may be needed. This section is about the using of testing equipments in
the signal generation and analysis of the base-band testing. All input signals (not the reference
voltages) are biased at 1.1 V DC and all output signals (not the intermediate signals such as
peak detectors’ outputs) are buffered.
B.3.1 Power Supplies, Signal Sources and Analyzers
Besides the 3-V Vdd, a second 1.1-V power supply Vdc is used to bias unused input terminals
such as vpxi, vp_i, vpxq and vp_q.
The major signal sources are two DS345 300MHz synthesized function and arbitrary wave-
form generators. Their signals can be synchronized to each other and the signal phase can be
tuned in a fine resolution. These features make it very easy to simulate the zero-IF I/Q signals
or differential sine waves. Another important feature of this signal generator is the ability to
create arbitrary waveforms. This, together with the phase tuning function (not for an arbitrary
waveform), allows the simulation of an down-converted FSK signal, as will be discussed later.
The SR780 two-channel FFT network analyzer is a versatile equipment which can do a
number of tasks in both the time domain and the frequency domain. Examples are noise and
distortion measurements. It can handle both single-ended and differential signals. Although it
is not designed for digital signal analysis and its maximum frequency is only 102.4 kHz, it can
still be used to capture digital outputs as the data rate here is much lower.
A general purpose two-channel oscilloscope is also necessary for signal monitoring.
In the following several paragraphs, the generation of various input signals using the above
equipments are described.
Table B.2 External components list.
Resistors Variable Resistors Capacitors
Rpmp1 50 kΩ Rpmp2 50 kΩ Cbp1 1 nF
Rs1-Rs4, Rra, Rrd 33 kΩ × 6 Rrefa, Rrefd 20 kΩ × 2 Cinti, Cintq 100 pF × 2
Rxa1 20 kΩ Rxa2 50 kΩ Cpi+, Cpi−, Cpq+, Cpq−, Cpki, Cpkq
10 nF × 6
Rxd1 100 kΩ Rxd2 50 kΩ Cpmp 15 or 22 nF
APPENDIX B Base-band Testing 138
Differential Signal Generation
As the circuit is designed to be fully balanced, differential input signals are required when
measuring the harmonic distortion performance. Usually only single-ended signals are avail-
able from a signal generator. Some kind of single-to-differential conversion circuit is thus
needed to obtain a differential signal. But an easier way is to synchronize two signal generators
such that their signals are out of phase. Setting these two signals as the X and Y axes of the
oscilloscope, an 135° straight line will be observed when their phase difference is 180°. Thus,
they can be considered as a differential signal.
I/Q Components Generation
The quadrature components of an down-converted sine wave can be simulated similarly except
that the phase difference is 90° and only single-ended signals can be obtained with two genera-
tors. The latter is acceptable in a function verification. On the oscilloscope two quadrature sig-
nals depict a circle.
FSK Signal Generation
To verify the function of the demodulator, two 1.6 or 4.8 kHz sine waves with +90° or −90°
phase differences are enough. However, signals in which symbol transitions are embraced are
necessary to enable the operation of the clock recovery circuit. Such a quadrature signal pair is
shown in Figure B.4. The I-signal is a pure sine wave while the Q-signal is an arbitrary wave-
form which is created using 25 evenly distributed data points in the vector mode. In this mode
additional points, 9 here, can be inserted between every two neighboring data points by linear
interpolation. The total number of data points per cycle is therefore 250. Table B.3 gives the
addresses and values of the 25 data points. At 800 kHz (sampling) frequency, the waveform
repeats at the symbol rate of 3.2 kHz.
The waveforms in Figure B.4 is derived under the assumption that the LO signal is in phase
with the RF input. As the demodulator is non-coherent, the same result will be obtained when
there is a random phase error.
The Chirp Signal Source
The SR780 network analyzer can also be used as a signal source. Its chirp signal has a flat
spectrum and is suitable for measuring the transfer function of a circuit. However, as the chirp
signal contains no DC offset, an additional voltage must be provided to bias the input.
APPENDIX B Base-band Testing 139
B.3.2 Input Setup
In different types of measurements, different signal sources are required and thus the input ter-
minals should be configured differently. Figure B.5 shows the input setups for 4 types of mea-
surements, where all DC voltage sources are 1.1 V.
Figure B.4. The zero-IF quadrature components of the FSK signal of the “+3−3” symbol series.
Table B.3 Data points of the arbitrary waveform. Frequency = 800 kHz.
Addresses Values Addresses Values Addresses Values
0 0 90 −509 180 986
10 754 100 −1203 190 1577
20 1401 110 −1728 200 1947
30 1852 120 −2011 210 2043
40 2043 130 −2011 220 1852
50 1947 140 −1728 230 1401
60 1577 150 −1203 240 754
70 986 160 −509 249 77
80 257 170 257
Figure B.5. Input setups for different types of measurement. The DC voltage is 1.1V.
−3 +3 −3
I
Q
Data
iin+
iin−
qin−
qin+
iin+
iin−
0°
180° iin+
iin−
Chirp
DS
34
5
220nF
100kΩ
DS
34
5
iin+
iin−
qin−
qin+
DS
34
5
DS
34
5
0°
90°
SR780
(a) Noise (c) Transfer function(b) Gain/distortion (d) Demodulation andclock recovery(I-Channel)(I-Channel)
APPENDIX B Base-band Testing 140
B.4 Operation Points
Typical DC operation voltages of several testing points at 3 V supply are given in Table B.4.
Table B.4 Typical DC operation points. Vdd=3.0V, Vdc=1.1V.
Voltage Drop over Biasing Resistors
Node Voltages (V) Node Voltages (V)
Rxa1 (20 kΩ) 200 mV Vrefa 0.9Axi, A_i, gxi, g_i, oxi, o_i, gxq, g_q
1.98Rxd1 (100 kΩ) 1 V Vrefd 0.35
Vbp1 2.0
APPENDIX CList of Publications
[1] Zhiheng Chen, Zhaofeng Zhang and Jack Lau, “A Novel CMOS Digital 4-FSK Demodulator for Direct-Conversion High Speed Radio Paging Receivers,” submitted to the 2001 IEEE Custom Integrated Circuits Conference.
[2] Keqiang Shen, Zhiheng Chen, Jack Lau, Wallace Wong, Frankie Hui, Philip C. H. Chan, Ping K. Ko, “A Three Terminal SOI Gated Varactor for RF Application”, IEEE Trans. Electron Devices, Feb. 2001
[3] Zhaofeng Zhang, Zhiheng Chen and Jack Lau, “A 930 MHz CMOS DC-Offset Free Direct Conversion 4-FSK Receiver,” IEEE International Solid State Circuit Conference, San Francisco, Feb. 2001
[4] Zhiheng Chen, Jack Lau, “Circuit Requirements of a Direct Conversion Paging Receiver,” IEEE Trans. Circuits Syst. II, vol. 46, no. 6, June 1999, pp.802-827.
[5] Wallace Wong, Frankie Hui, Zhiheng Chen, Keqiang Shen, Jack Lau, Philip C. H. Chan, Ping K. Ko, “A Wide Tuning Range Gated Varactor,” IEEE J. Solid-State Circuits, vol. 35, no. 5, May 2000, pp.773-779.
[6] Zhaofeng Zhang, Zhiheng Chen and Jack Lau, “A 900 MHz CMOS Balanced Harmonic Mixer for Direct Conversion Receivers,” the 2000 IEEE Radio and Wireless Conference, Sep. 2000.
[7] Wallace Wong, Frankie Hui, Keqiang Shen, Zhiheng Chen, Jack Lau, Philip C. H. Chan, Ping K. Ko, “A 2 GHz 300 MHz Tuning Range 200 MHz/V Gain Voltage-Controlled Oscillator Using Gated Varactor in 0.35 µm CMOS,” IEEE Symp. VLSI Circuits, June 1999, Kyoto, Japan.
[8] Frankie Hui, Keqiang Shen, Zhiheng Chen, Jack Lau, Margaret Huang, Mansun Chan, Gongjiu Jin, Ping K. Ko, Philip C. H. Chan, “High-Q SOI Gated Varactor for use in RF ICs,” Proc. IEEE Int. SOI Conf., pp 31-32, Oct. 1998.
[9] Zhiheng Chen, Jack Lau, “Direct Conversion for FLEX Paging Receivers — A Feasibility Study,” Digest of IEEE RFIC Symp., pp293-296, June, 1998.
[10] Tony Yeung, Alan Pun, Jack Lau, Zhiheng Chen, Francois J.R. Clement, “Noise Coupling in Heavily and Lightly Doped Substrate from Planar Spiral Inductor,” Proc. IEEE Int. Symp. Circuits Syst., vol.2, pp. 1405-1408, June, 1997.
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