1

A Digitally Enhanced 1.8-V 15-b 40-Msample/s CMOS Pipelined ADC

Eric Siragusa1 and Ian Galton

University of California, San Diego

1 Now with Analog Devices, San Diego, California

Outline

• Conventional PADC Example

• Digitally Enhanced PADC Prototype

• System-Level Design Details

• Circuit-Level Design Details

• Measured Results

• Conclusion

2

A Conventional Pipelined ADC Example

• Seven stages• Each resolves slightly more than 3 bits• 1-b of redundancy per stage

• Ideal DACs and gains � accuracy is just over 15b

9-levelPipeline

Stage

9-levelPipeline

Stage

9-levelPipeline

Stage

9-levelPipeline

Stage

9-levelPipeline

Stage

9-levelPipeline

Stage

9-levelPipeline

Stage

9-levelFlashADC

Vin(t)

xout[n]

AnalogDigital

Delays not shown

×4

8 1-bDACs

9-levelFlashADC

Conventional Switched Capacitor PADC

• Interstage gain error:– Sources: capacitor mismatch, finite open-loop amplifier

gain, incomplete amplifier settling– Effect: “leakage” of quantization noise into PADC output

• DAC Noise:– Source: capacitor mismatch– Effect: introduction of signal-dependent errors

• Conventional solutions: – Large capacitors, high-gain op-amps– Foreground calibration techniques– Analog-intensive calibration techniques– Trimming

3

Digitally Enhanced PADC Prototype

1. E. J. Siragusa, I Galton, IEE Electronics Letters, March 30, 2000 2. I. Galton, IEEE TCAS-II, March, 20003. A. Fishov, E. Siragusa, J. Welz, E. Fogleman, I. Galton, IEEE ISCAS, May 2002.

• Analog performance limitations are mitigated by background digital signal processing:– Gain error correction (GEC) 1– DAC noise cancellation (DNC) 2– Segmented mismatch-scrambling DACs 3

• Demonstrated in a 0.18 μm CMOS prototype:– 1.8 V, 15 bit, 40 Msamples/s, 400 mW– 90 dB SFDR, 72 dB peak SNR, 88 dB THD

IC Prototype – High-Level Architecture

DEMEncoder

9-levelFlashADC

18119

9-levelPipeline

Stage

9-levelFlashADC

9-levelPipeline

Stage

9-levelPipeline

Stage

9-levelPipeline

StageVin

DNC/GECLogic

19

DNC/GECLogic

19

DNC/GECLogic

1916

16 16 16

Unc

orre

cted

AD

C O

utpu

t

CorrectedADC Output

9-levelPipeline

Stage

9-levelPipeline

Stage

9-levelPipeline

Stage

Enhancements

10 1-bDACs

×4

PRN Generator

4

Dynamic Element Matching OverviewWhen DAC mismatches are present:

• DEM alone improves SFDR …but not SNDR!

However DEM causes the noise to have “structure”:– Noise was “manipulated” with known pseudo-random

sequences and digital logic in the encoder – DNC technique will exploit the structure to remove the noise

DEMEncoder

10 1-bDACs

10 1-bDACs

Dynamic Element Matching DAC

DEM Encoder uses pseudo-randomization to convert 1-b DAC mismatches, ehi and eli, into a constant gain, α, a constant offset, β, and white DAC noise, eDAC[n].

1

1

1

1

/ 2 , if [ ] 1/ 2 , if [ ] 0

h

l

x nee x n

' ­®�'

��¯

10

10

10

10

/ 4 , if [ ] 1/ 4 , if [ ] 0

h

l

x nx n

ee

' ­®�'

��¯

[ ] [ ] [2

]DACy n x n e nD E' � �DEM

Encoder

x1[n]

x2[n]

x3[n]

x4[n]

x5[n]

x6[n]

x7[n]

x8[n]

x9[n]

x10[n]

x[n] {�������������}

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

5

DEM DAC Example for x[n] = 1

• α and β are independent of x[n] and pseudo-random choice• eDAC[n] depends on pseudo-random choice

[ ]2 DACe nD E'� �

DEMEncoder

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

x[n] = �or

0

1

0

1

0

1

0

1

1

1

0

1

0

1

0

1

1

1

0

0

or

1

0

1

0

1

0

1

0

1

1

etc.

Chosen pseudo-randomly once per sample period���

1-b DAC r'��

The DEM Encoder: A Closer Look

• sseg[n] and sj,k[n] are independent pseudo-random 0, ±1 sequences• sseg[n] and sj,k[n] are known by the digital logic

, ,[ ] [ ]2

k r k rx n s n�

Sk,r, ,[ ] [ ]

2k r k rx n s n�

, [ ]k rx n

Sseg

1 [ ]segs n�

[ ]inx n

S1,1

S1,2

S1,3

S1,4

S1,5

S2,1

S2,2

S3,1

Sseg

DEM Encoder

18 ^ `3,1 1,5[ ], [ ], , [ ]segs n s n s n"

,,

0 if [ ] evenand [ ]

1 elsek r

k r

x ns n

­ ®r¯

[ ] 8 [ ]2

in segx n s n� �

0 if [ ] evenand [ ]

1 elsein

seg

x ns n

­ ®r¯

where:

6

The DEM Encoder: ExampleOne example set of choices for x[n] = 2:

, ,[ ] [ ]2

k r k rx n s n�

Sk,r, ,[ ] [ ]

2k r k rx n s n�

, [ ]k rx n

Sseg

1 [ ]segs n�

[ ]inx n

S1,1

S1,2

S1,3

S1,4

S1,5

S2,1

S2,2

S3,1

Sseg

DEM Encoder

18^ `0, 1, 0, 1, 1, 1, 1, 0, 1� � � �

,,

0 if [ ] evenand [ ]

1 elsek r

k rx n

s n ­

®r¯

[ ] 8 [ ]2

in segx n s n� �

0 if [ ] evenand [ ]

1 elsein

segx n

s n ­

®r¯

where:

2 51

23

11

1001011110

12

Structure of the DAC Noise

eDAC[n] is like a spread spectrum signal:• Δk,r and Δseg are the unknown (constant) “message signals”• sk,r[n] and sseg[n] are the known “spreading codes”

> @ > @ > @, ,DAC k r k r segk

s gr

es n se nn �' '¦¦

Known,independent,

pseudo-random 0,±1 Sequences

Unknownconstants that

depend only onthe 1-b DACmismatches

Can Show:

DEMEncoder

x[n]

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

1-b DAC r'��

[ ] [ ] [2

]DACy n x n e nD E' � �

7

The DNC Technique

The DNC logic is a spread spectrum “receiver” that:

• correlates the digitized residue against sk,r[n] and sseg[n] to estimate Δk,r and Δseg

• uses the DAC noise equation to cancel eDAC[n]

The DAC noise directly corrupts the uncorrected ADC output:

Vin

DNC/GECLogic

1916

16

Unc

orre

cted

AD

C O

utpu

t

9-levelPipeline

StagePipeline

Stages 2-7

DigitizedResidue

First Stage Calibration Logic - DNC

• 9 simple spread-spectrum “receivers” • Requantization:

– reduces DNC logic size– dithered to avoid corrupting correlations

7-LevelRequantizer

11

yDNC

PNGenerator

14 15 3

DigitizedResidue

ErrorEstimate

DitheredRequantizer

yGEC

DNC Logic

Average Correlator #1

3

�

a

GEC Logic

Average Correlator #9

3

�'3,1a

�'seg sseg[n]� 'sega

s3,1[n]� '3,1a

sseg[n] sseg[n]

s3,1[n] s3,1[n]

8

Interstage Gain Error

• ε = interstage gain error• Causes imperfect cancellation of ADC quantization noise• Reduces SFDR and SNDR

Conventional PADC:

9-levelFlashADC

8 1-bDACs

PipelineStages 2-7

'��

'

�

× ���H�

Digitized Residue

'��

�

�'��

'��

'

�

'��

'

�

�'��

SignalQuantization Noise

����H�

The GEC Technique (1)

• A pseudo-random ±Δ/4 sequence is introduced to the DAC path• It occupies a portion of error headroom created by redundancy• It follows the same path and sees the same gain as the quantization

noise

DEMEncoder

9-levelFlashADC

10 1-bDACs

PipelineStages 2-7

'��

'

�

× ���H�

'��

'

�

�'��

Digitized Residue

'��

�'�� '��

�

�'��

'��

'

�

SignalQuantization NoiseGEC Signal

����H�

9

The GEC Technique (2)

DEMEncoder

9-levelFlashADC

10 1-bDACs

PipelineStages 2-7

'��

'

�

× ���H�

'��

'

�

�'��

Digitized Residue

'��

�'�� '��

�

�'��

'��

'

�

�

��× (Digitized Residue)Average of:

� (Digized Residue) / (Correction Factor) =

Ideas behind GEC Technique:

SignalQuantization NoiseGEC Signal

����H�

Correction Factor

First Stage Calibration Logic -GEC

Instead of dividing the digitized residue by the gain estimate:

• a linear Taylor series approximation is used:

• the resulting correction signal is added directly to outputAny linear contribution to gain error is corrected!

7-LevelRequantizer

11 yDNC

PNGenerator

14 15 3

DigitizedResidue

ErrorEstimate

DitheredRequantizer

rgec

AverageCorrelator

3

1

yGEC

GEC Logic

pause

�

DNC Logic

1( )H�� � H� �

1 1(1 ) HH | ��

��

10

Circuit-Level Details

• Distributed input sampling4

• Separate input and DAC sampling capacitors• DNC&GEC => no special attention to cap matching

4. I. Mehr and L. Singer, IEEE Journal of Solid State Circuits, March 2000

DEMEncoder

PassiveSamplingNetwork

Thermometerto BinaryEncoder

4

Vin+

Vin�

yout

Vout+

Vout�×4

PassiveSamplingNetwork

8

82

Distributed InputSampling Network

18

1rgec[n]

bk

ck

PRN Generator

9-levelFlashADC

19To DNC/

GEC Logic

ResidueAmplifier

s[n]

10 1-b DACs

Bootstrapped Switch Circuitry1.8V

Thick-Oxide Devices

SamplingSwitch

Vin Vout

C

II

TrackSample

Switch Off,Charge C

I

I

5. M. Dessouky and A. Kaiser, IEE Electronics Letters, January 1999

• Modified version of circuitry presented in [5]– Thick-oxide devices to avoid exceeding technology limits

• Uses a single 1.8V clock

11

Residue Amplifier (1)

P2

P1

OTA P1P1

P1Vcmoi

Voutp

Voutn

Vinn

Vinp

P2

P1

Vcmoo

Vcmoo

1.8V1.8V1.8V 1.8V

VCMFB

VinpVinn Vbn2

Vbn1

Vbp2

Vbp1

CcRc

Vbp3

Voutp

• Closed loop gain of 4 • Two-stages for high gain and wide output swing

Residue Amplifier (2)

• Conventional PADC:– Open-loop gain requirement >100dB– Gain-boosting is typically required– Simulated gain: >125dB with gain-boosting, 85dB

without

• Prototype IC:– Gain-boosting with enable/disable circuitry is included– As expected, measured PADC performance with GEC

enabled and gain-boosting disabled does not change!

• Scaled down once and used in the remaining stages without further scaling

12

DEM Encoder and GEC Adder Implementation

• Control logic block presets paths • Critical path is 1 T-gate delay• Encoder & adder implemented

together to minimize latency

1 T-gate delay

Control Logic(Timing not critical)

72

LSB SegmentSwitch

2 NAND-gatedelays

1 Layer of 72T-gates

8yFADC[n]

c0[n]

c1[n]

b7[n]b6[n]b5[n]b4[n]

19fz

b3[n]b2[n]b1[n]b0[n]

MSB

s[n], rgec[n]

DEMEncoder 8

218

1rgec[n]

bk

ck

PRN Generator

19To DNC/

GEC Logic

s[n]

8yFADC[n]

DAC Sampling Network

• 10 1-b DACs:– 8 step-size Δ– 2 step-size Δ/2

• References are “double sampled”– Capacitor sizes halved– Reduces kT/C noise

Vcmoi

Cd

CdP1

P1Vref+

Vref-

P2�bk

P2�bk

P2

P2

P1

P1

P2�bk

P2�bk

To ResidueAmplifier

Vcmoi

Cd /2

Cd /2 P1

P1Vref+

Vref-

P2�ck

P2�ck

P2

P2

P1

P1

P2�ck

P2�ck

1 of 8

1 of 2

Vo+

Vo-82

bk

ck

10 1-b DACs

To ResidueAmplifier

From DEMEncoder

Vo+

Vo-

13

Process, Layout and Packaging Overview

• Process– 0.18μm CMOS – MiM capacitors, deep Nwells, thick-oxide devices, low-

VT devices• Layout

– Deep Nwells and multiple supply domains– No special attention to capacitor matching– ESD protection circuitry on all pads

• Packaging– 56-pin QFN package with exposed die paddle– Down-bonding of all grounds to exposed paddle– Double-bonding of critical supply pins

Measured SFDR and THD vs. Input Frequency

• DNC and GEC enabled

0 2 4 6 8 10 12 14 16 18 2080

82

84

86

88

90

92

94

96

98

100

MHz

dB

SFDR

THD

14

Measured PSD with a 19 MHz Input

With DNC and GEC disabled With DNC and GEC enabled

SFDR 64.8 dBSNDR 54.7 dB

SFDR 90.9 dBSNDR 71.6 dB

0 2 4 6 8 10 12 14 16 18 20-120

-100

-80

-60

-40

-20

0

MHz

dB

0 2 4 6 8 10 12 14 16 18 20-120

-100

-80

-60

-40

-20

0

MHz

dB

Measured DNL (fin = 1 MHz )

With DNC and GEC disabled With DNC and GEC enabled

DNL = 2.3 LSB DNL = 0.25 LSB

0 0.5 1 1.5 2 2.5 3 3.5

x 104

-0.5

0

0.5

1

1.5

2

2.5

Code

DN

L (L

SB

))

0 0.5 1 1.5 2 2.5 3 3.5

x 104

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Code

DN

L (L

SB

))

15

Measured INL (fin = 1 MHz )

0 0.5 1 1.5 2 2.5 3 3.5

x 104

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

Code

INL

(LS

B)

0 0.5 1 1.5 2 2.5 3 3.5

x 104

-30

-20

-10

0

10

20

30

Code

INL

(LS

B)

With DNC and GEC disabled With DNC and GEC enabled

INL = 25 LSB INL = 1.5 LSB

Fabrication and Measurement SummaryResolution 15 bSample Rate 40 MHzInput Voltage Range 2.25 Vp-p differentialSFDR 90 dBTHD 88 dBPeak SNR 72 dBDNL 0.25 LSBINL 1.5 LSBSFDR Improvement with DNC and GEC enabled

> 20 dB

SNDR Improvement with DNC and GEC enabled

> 12 dB

Total Power 400 mWAnalog Power 343 mW (1.8 V)Digital Power 51 mW (2.1 V)Output Drivers Power 6 mW (1.8 V)

Technology 0.18μm 1P6M CMOSDie Size 4mm x 5mm (including pads)Package 56-Pin QFN with

ground downbonding

16

Die Photo

Digital LogicClk

Buf

f/Gen

Stages 2-7Se

rial

Port

Stage 1

Bias

Conclusion

• The silicon implementation of two digital signal processing background calibration techniques has been presented– DNC to compensate for DAC mismatch noise– GEC to compensate for interstage gain errors

• Together they drastically reduce analog circuit requirements required to achieve high performance

• They have been shown to be enabling components in a high-resolution pipelined ADC

17

Acknowledgements

• The authors are grateful to Erica Poole for digital schematic capture and verification, Sudhakar Pamarti and Ashok Swaminathan for digital layout and technical advice, Eric Fogleman for technical advice, and Andrea Panigada for test board design and technical advice.