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D I S S E R T A T I O N
Simulation of Ion Implantation for ULSI Technology
ausgefhrt zum Zwecke der Erlangung des akademischen Grades
eines Doktors der technischen Wissenschaften
eingereicht an der Technischen Universitt Wien
Fakultt fr Elektrotechnik
von
Andreas Hssinger
Aspangstrasse 53/31
Wien III.
Matrikelnummer 8727546
geboren am 16. September 1969 in St. Plten
Wien, im Juli 2000
Link:
http://www.iue.tuwien.ac.at/phd/hoessinger/diss_html.htmlAbstract
In modern semiconductor technology ion implantation has turned out to be the mostimportant technique to introduce dopant atoms into semiconducting materials. Themajor advantage of the ion implantation technique is the high controllability and
reproducibility of the process parameters influencing the doping distributions.Furthermore, very shallow doping profiles can be formed, which are a prerequisite forULSI (ultra large scale integration) technology.
Since it is mainly ion implantation which determines the distribution of the dopantsand thereby the electrical properties of the semiconductor devices highly accuratesimulation methods for ion implantation processes are required to be able to predictand optimize the behavior of integrated circuits. In recent years successively shrinking
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device dimensions and new design concepts have shown the necessity of a full three-dimensional treatment of simulation problems, e.g. the simulation of MOS transistorswith narrow gates, or vertical transistors.
Three-dimensional simulations obviously require large computation times and a lot of
memory. Therefore, it is a waste of computational resources if a three-dimensionalsimulation would be applied to all applications. Several problems, like the buriedlayer or the well formation of an MOS transistor can be analyzed as accurate bysimpler two-dimensional or even one-dimensional simulations. Since it should be easyto switch the dimension of the simulation without recalibrating a simulator, it is notdesirable to use different simulators, which eventually use different models, for thesimulation of one-dimensional, two-dimensional and three-dimensional problems.
The goal of this work was to further improve a Monte-Carlo ion implantationsimulator developed over the last fifteen years within the scope of several PhD theses.
As part of this work several new models and methods have been developed andimplemented to improve the accuracy and the efficiency of the simulator, in order tobe applicable to modern ULSI technology. Besides an enhancement of the models, thesimulator has been redesigned in a way to cover one-dimensional, two-dimensionaland three-dimensional problems. Thereby the simulator has been made adaptable tothe specification and requirements of a certain problem, which allows to avoid a wasteof computational resources.
The functionally of the simulator and the theoretical background is presented in detail,especially focused on methods and algorithms developed as a part of this work. Worth
mentioning among them is first the Follow-Each-Recoil method which allows a veryaccurate simulation of the implantation induced damage. By using the Follow-Each-Recoil method it is possible to provide very accurate input data for the simulation ofrapid thermal annealing processes. As well the precise distribution of point defectsand the formation of amorphous areas can be simulated. Furthermore the full and thesimplified molecular methods have been developed and implemented. These methodsenable to treat the implantation of molecular ions and atom clusters and thus the
implantation of BF , which is a widely used for the doping with boron atoms. Byproviding two methods for the simulation of molecular ions the functionality of the
simulator can be adapted to the problem requirements. While the simplified molecularmethod needs less computation time, the full molecular method provides more preciseresults.
Another part of this work was the design and the implementation of a point responseinterface method. It allows to interface Monte-Carlo simulation results to an analyticalion implantation simulator. Thereby the flexibility and the accuracy of an analytical
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simulator can be significantly improved, because the calibration of an analyticalfunction for certain process conditions is not necessary.
For the reduction of the simulation time two new methods have been developed. Onthe one hand side the Trajectory-Reuse method, which enables a significant speed up
of the simulation. Especially in case of three-dimensional simulation problems and ifthe simulation domain consists of large amorphous areas the reduction in computationtime is remarkable. On the other hand side the simulator has been parallelized in away to be able to perform the simulation on a cluster of workstations which is thetypical TCAD (technology computer aided design) environment. If the load of theworkstations participating in the simulation is approximately constant an almost linearperformance gain could be achieved by the parallelization method, even if a fairlyslow network connects the workstations.
Finally, the developed Monte-Carlo ion implantation simulator is applied to a set of
examples making use of some of the special features of the simulator. Additionally asmall operating manual for the simulator is included in the appendix.
1. Introduction
y 1.1 Semiconductor Process Technology o1.1.1 Lithography o1.1.2 Etching o1.1.3 Deposition o1.1.4 Chemical Mechanical Polishing o1.1.5 Oxidation o1.1.6 Ion Implantation o1.1.7 Diffusion
2. Ion Implantation Technology
y 2.1 Implanter Techniques y 2.2 Ion Implantation Process Parameters
o2.2.1 Dopant Species o2.2.2 Ion Beam Energy o2.2.3 Implantation Dose o2.2.4 Tilt and Twist Angle
y 2.3 Target Materials Properties o2.3.1 Crystalline Silicon o2.3.2 Polycrystalline Silicon
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o2.3.3 Silicon Dioxide
1. Introduction
At the end of the 20-th century microelectronics has moved into almost all areas of life. Theworld semiconductor sales have reached an order of 130 billion US$ consisting mainly of fiveproduct fields (automotive electronics, computer, consumer electronics, industrial electronics,telecommunication).
The multitude of applications and the strong competition in the market require fast, cheap andefficient methods for the development and optimization of new technologies and designs. Duringthe last years Computer-Aided Design (CAD) methods have been introduced because they meet
all these requirements. They simplify the developing process and therefore the time to market fornew products.
Electronic CAD (ECAD) tools are used to design integrated circuits (IC) in terms of behavioraldescriptions, net lists, schematics, and layout. ICs are modeled as a whole or as a set offunctional blocks. In contrast the development and optimization of new technologies mainlyconcentrates just on a single device (transistor, diode, etc.). A deep insight into the workingbehavior of a single device is necessary, and it is important to know how certain productionprocesses influence this behavior. Technology CAD (TCAD) covers this field by providing toolsfor the simulation of production processes and of the electrical behavior of devices. Bycombining process and device simulation in a TCAD frameworks the influce of process
parameters on the electrical characteristics can be analyzed and optimized.
Nowadays one-dimensional and two-dimensional process simulators are used in industry, butwith increasing computer performance three-dimensional simulations become more important,especially since shrinking device dimensions bring up more and more three-dimensional effectswhich cannot be investigated by two-dimensional simulations.
Subsections
y 1.1 Semiconductor Process Technology o 1.1.1 Lithography o 1.1.2 Etching o 1.1.3 Deposition o 1.1.4 Chemical Mechanical Polishing o 1.1.5 Oxidation o 1.1.6 Ion Implantation
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o 1.1.7 Diffusion
1.1 Semiconductor Process TechnologyThe fabrication of an ICrequires hundreds of sequential process steps containing [19] [70] :
y Lithographyy Etchingy Depositiony Chemical Mechanical Polishingy Oxidationy Ion Implantationy Diffusion
Starting with a uniformly doped silicon wafer the production process can be subdivided intothree phases.
y The generation of the active devices (front-end processing).y The definition of the contacts and interconnects (back-end processing).y The packing of the IC.
For each production phase several process steps are applied.
1.1.1 Lithography
A lithography step is used to transfer layout information to the wafer. The layout is a collectionof masks which define specific patterns for the generation of the IC, for instance the definition ofthe active area of a transistor, or the gate area of a MOS transistor. During a lithography step thepatterns defined by one mask are recorded on a radiation sensitive material named photo-resist,which has been deposited on top of the wafer. The resist changes its physical propertiesaccording to the dose of radiation. There are several lithographic methods which mainly differ inthe type of radiation and thereby in the resolution of the patterns. Normally visible andultraviolet light is applied, but advanced technologies like extreme ultravioletlithography (EUV), X-ray lithography (XRL), electron projection lithography (EPL) and ionprojection lithography (IPL) have moved from the research and development phase intocommercial development for applications down to 35 nm feature size([72]). However, thesetechniques still suffer from serious technological problems concerning especially the maskgeneration, the mask lifetime and the wafer throughput.
To improve the quality of the shape of the pattern on the wafer a post-exposure bake step isapplied after the exposure to the radiation. Thereby especially standing wave effects are reduced.Afterwards the resist is developed, either by a wet chemical etching process, by dry plasma
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etching or by conversion to volatile compounds through the exposure radiation itself. Dependingon the type of the resist (positive or negative resist) the pattern defined by the mask is eitherremoved by or remains after the development process.
1.1.2 Etching
An etching process is either used to remove complete material layers from the wafer (e.g.remove an oxide layer after ion implantation) or to selectively remove certain parts of amaterial (e.g. transferring patterns form the a resist layer into underlying materials). There arevarious applications for etching processes in all phases of the production process of an IC.Etching can be performed by a chemical attack (wet etching), by physical damage (dry etching)or by a combination of both [19].
Wet etching is performed by applying liquid etching agents to the wafer. This chemical processprovides an isotropic etch rate and a high selectivity. High selectivity means that the etch ratestrongly depends on the etched material. Additionally the crystalline structure of an attacked
semi-conducting material like silicon is almost maintained also in the vicinity of the surface.
The major drawbacks are the poor reproducibility, especially because the etching time can becontrolled very difficulty. Furthermore the wet etching process suffers from the excessivecontamination of the semi-conducting device by the etching agents. Finally the strong isotropy ofthis process limits its applicability. The wet etching process is used for total or partial removal ofwhole layers. Due to the so-called under-etch effect, which can lead to a full detaching of themask from the underlying material, wet etching is not suited to transfer patterns with sub-micronfeature size.
Physical or dry etching is on the contrary a highly anisotropic etching process and thus capable
of transferring small structures also below sub-micron feature size. In this technique material isremoved by momentum transfer between particles in a plasma chamber and the target material.The etching characteristics mainly depends on the pressure in the plasma chamber. The lower thepressure, the better the achievable resolution is. For very low pressures the process is called ionmilling [16]. The drawback of the dry etching technique is the low selectivity which can beincreased by raising the chamber pressure and accelerating thereby the chemical reaction rate.Reactive ion etching [24] is a good compromise between resolution and selectivity.
1.1.3 Deposition
During the production process of an integrated circuit several layers of different materials have
to be deposited on the surface of the wafer. These layers become part of the integratedcircuit (e.g. polysilicon gate) or serve as intermediate layers (e.g. resist for a lithography step).The deposited materials include doped semiconductors, metals, insulators, dielectrics andorganic compounds. Mainly two techniques are applied for the deposition process. On the onehand side physical vapor deposition (PVD) and on the other hand side chemical vapor deposition(CVD) is used.
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Physical vapor deposition is performed in a low pressure plasma chamber, where accelerated gasions sputter particles from a sputter target. Thereby atoms of a well defined composition leavethe sputter target towards the deposition target where they cover the surface. Alternatively theparticle for deposition can be generated by vaporizing the particle source instead of sputtering it.The drawbacks of the PVD technique is that it has reduced step coverage and therefore reduced
capability to uniformly cover arbitrary surface topologies. It is mainly applied to deposit metalsfor interconnects.
Chemical vapor deposition denotes the precipitation of amorphous, polycrystalline or monocrystalline films on a substrate, from gas phase. It is based on a chemical reaction of a gasmixture on the substrate surface at high temperatures. The gas molecules are converted into asolid which combines with the substrates surface and into a volatile part which is removed fromthe surface by convection. The most critical aspect of this technique is the requirement of hightemperatures, which is sometimes not tolerable. To avoid this problem plasma enhancedchemical vapor deposition can be used, where the chemical reactions are enhanced by radiofrequency discharges instead of higher temperatures.
1.1.4 Chemical Mechanical Polishing
Due to the fact that several process steps which modify the topography of the wafersurface (etching, deposition, oxidation) are necessary to generate an IC, the surface becomesseverely non-planar. This creates several problems especially for the lithography process,because non-planar surfaces require a high depth of focus which is incompatible with therequirement of a high numerical aperture of the imaging systems, which is necessary toguarantee a small minimum feature size.
Chemical mechanical polishing CMPis used as a planarization technique. A chemical slurry
with etchant agents and abrasives is applied to the wafer surface.
1.1.5 Oxidation
Oxidation is used to generate silicon dioxide layers as insulators (e.g. field oxide betweendevices), as scattering layers or masks for ion implantation. In the oxidation process oxygen (dry
oxidation) or H O (wet oxidation) molecules convert silicon layers on top of the wafer tosilicon dioxide. To enhance the oxidation this is performed at elevated temperatures. Beside thetemperature the oxidation process is influenced by the pressure.
Compared to deposited silicon dioxide, thermally grown silicon dioxide has excellent mechanicaland electrical properties and especially a very good sticking coefficient with the underlyingsilicon. The high quality and the properties of the silicon dioxide is the most important reasonwhy silicon is still the dominating material in ICfabrication.
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1.1.6 Ion Implantation
Ion implantation is the most widely used technique to introduce dopant impurities intosemiconductors. A beam of ionized particles is accelerated through an electric field and aimed ata semiconductor target. The particles penetrate into the target until they come to rest due to
interactions with the atoms of the target material. The penetration depth of the dopants dependson the kinetic energy of the ions, which can be controlled very accurately. But not only thepenetration depth but also the absolute concentration of the dopants influences the electricalbehavior. The concentration can be adjusted quite accurately by varying the implantation dose.
One drawback of the ion implantation technique is that the crystal structure of a semiconductor isdamaged by the implanted particles, which impairs the electrical properties of the semiconductor.Additionally the implanted dopants are electrically inactive because they reside on interstitialsites after the implantation. To repair the crystal damage and to activate the dopants a thermalactivation step is necessary after an ion implantation step.
1.1.7 Diffusion
The movement of doping atoms according to a dopant gradient in a semiconductor material iscalled diffusion. It occurs during any high temperature processing step, either as an intentional oras a parasitic effect. Due to the requirement of very shallow junctions in modern semiconductortechnology diffusion is mainly a parasitic effect of the annealing step after ion implantation or ofan oxidation step which is performed at high temperatures. Nevertheless there are stillapplications in the well formation in complimentary metal oxide semiconductor (CMOS)technologies or in the in-diffusion of dopants from a chemical vapor source.
There are strong variations in the diffusivity of different dopant species and the diffusivity can
depend on the concentration of atoms of the own and other species. Besides, diffusion can beenhanced by oxidation or retarded by nitridation, because these processes generate point defectsat the surface. These surface generated point defects as well as implantation induced pointdefects can have a strong influence on the diffusivity because they facilitate complex diffusionmechanisms like transient enhanced diffusion (TED). At high concentration levels the dopantscan form non-mobile clusters or precipitates which decreases the average diffusivity. The exactcontrol of all diffusion mechanisms is a very critical issue during the manufacturing of asemiconductor device, because each redistribution of the dopants significantly influences theelectrical characteristics.
2. Ion Implantation TechnologySubsections
y 2.1 Implanter Techniques y 2.2 Ion Implantation Process Parameters
o 2.2.1 Dopant Species o 2.2.2 Ion Beam Energy
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o 2.2.3 Implantation Dose o 2.2.4 Tilt and Twist Angle
y 2.3 Target Materials Properties o 2.3.1 Crystalline Silicon o 2.3.2 Polycrystalline Silicon o 2.3.3 Silicon Dioxide
2.1 Implanter Techniques
Ion implantation has turned out to be the best suited technique to selectively introduce dopantsinto semiconductor materials. To perform ion implantation a focused ion beam containing justone particle species (atom, molecule or atom cluster) with a well defined energy is required.Ionized particles are used because they can be easily accelerated and there is an efficient way forthe separation of ionized particle species.
The ions are generated in an ion source which consists of an oven where the particles arevaporized, and the arc chamber, where the particles are ionized mainly by the bombardment ofthe atoms or molecules with electrons but also by atom/atom and atom/molecule collisions. Dueto a well designed magnetic field in the arc chamber, which increases the path length of theelectrons, and by the external generation of electrons, the electron/atom collision probability isincreased, enabling a larger ion density. Fig. 2.1 shows one example of an ion source, aschematic description of a Harwell Freeman ion source [91].
Figure 2.1: Schematic of a Harwell Freeman ion source.
There are various types of ion sources differing in the design of the arc chamber and in theelectron generation method.
y Harwell Freeman ion sourcey Penning ion sourcey Bernas ion sourcey Radio-frequency gas ion sourcey Duoplasmatron ion sourcey Microwave ion source
The ion beam which leaves the particle source is divergent. It is focused by an electric ormagnetic field lens to avoid ion loss to the wall of the beam line and to ensure that the ion beamreaches the wafer in a reasonably well defined focus. After leaving the ion source the beam
contains a lot of atom and molecule species in several charge states. Fig. 2.2 shows a typical ionsource beam spectrum.
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Figure 2.2: Spectrum from an SiF ion source spectrum [91].
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Figure 2.3: Schematic of the Eaton NV8200 medium current implanter [91].
The desired dopant is separated from the remaining elements by an analyzing magnet. Thereby itis made use of the physical effect that charged particles trace circular orbits with a radius
proportional to the ratio of the mass and the charge, when passing through a uniform magneticfield. An initial beam containing various particle species can thereby be split into several singlespecies beams with different beam directions, so that a small aperture placed behind theanalyzing magnet can absorb all but one particle species. The remaining ions are accelerated tothe required energy, before they reach the process chamber where one or several wafers arelocated.
Due to the fact that the area covered by the ion beam has a size of typically some cm the beamhas to be scanned across the wafer to guarantee a uniform implantation dose for the whole waferwhich has a diameter of up to 300 mm. Electrostatic beam scanning, magnetic beam scanning,linear mechanical beam scanning, spinning disk techniques or a combination of these techniques
are applied [91]. Even if electrostatic or magnetic beam scanning are technically lesscomplicated they usually suffer from the problem that the angle of incidence of the ion beam (tiltangle) on the wafer varies across the wafer up to some degrees. This results in non-uniformdoping profiles across the wafer, because the penetration depth of the ions is very sensitive to thetilt angle. Recently electrostatic scanning systems have be developed which compensate these tiltangle variations.
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As an example for an implanter a schematic description of the medium current implanter EatonNV8200 is shown in Fig. 2.3. The ions are generated in the ions source, a single particle speciesbeam is extracted by the beam analysis magnet and focused by a quadrupole double lens [91]. Bythe scanning electrodes the ion beam is scanned horizontally (x-axis) into a fan-shaped pattern,which is subsequently angle corrected into a ribbon shaped pattern by the beam parallelizing
lens. Finally the ion beam is accelerated to the required implantation energy in the accel-decelcolumn and deflected towards the wafer surface by the final energy filter which guarantees amono-energetic ion beam. A mechanical scanning system performs the y-axis scanning.
2.2 Ion Implantation Process Parameters
An ion implantation process is mainly determined by five process parameters.
y Dopant speciesy Ion beam energyy Implantation dosey Tilt and twist angle
2.2.1 Dopant Species
In modern semiconductor technology several impurity species with different applications areused. The most important ones are atoms of the third and the fifth group of the periodic table.They are used to generate positively (p-type) or negatively (n-type) doped regions in thesemiconductor. For p-type doping mainly boron and indium are used while the preferred speciesfor n-type doping are phosphorus, arsenic and antimony. The implantation of nitrogen is used toinfluence the diffusion behavior of boron in silicon dioxide and polysilicon. Sometimes also
silicon, germanium and carbon are implanted to destroy the crystalline structure of the substrate(pre-amorphization) before the implantation of a dopant species. Thereby shallower dopantprofiles can be generated because the channeling effect is suppressed (Sec. 5.2). Recently thereare also investigations on the implantation of oxygen to form buried silicon dioxide layers, forthe generation ofsilicon-on-insulator (SOI) devices. This technique is called: Separation byIMplanted OXygen (SIMOX) [91].
The impurities are implanted by single atomic ion beams or by molecular ion beams, whichfacilitate shallower doping profiles. The disadvantage of the molecular ion implantation is that
additional impurities are introduced. The most widely used molecular species are BF and
recently also B H for the implantation of boron and N for the implantation of nitrogen.Tab. 2.1 summarizes some properties of the most important dopant species.
Table 2.1: Physical properties of some impurity species.
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Species Atomic numberMass (amu)
Antimony 51 120.903820
Antimony 51 122.904210
Argon 18 39.962383
Arsenic 33 74.921596
Beryllium 4 9.0121822
Boron 5 10.012937
Boron 5 11.009305
Carbon 6 12.000000
Carbon 6 13.003354
Fluorine 9 18.998403
Gallium 31 68.925580
Gallium 31 70.924707
Germanium 32 69.924249
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Fig. 2.4 - Fig. 2.9 show experimentally determined projected ranges of some species in varioustarget materials [2], [26], [52], [53], [92]. The projected ranges are extracted from profilesmeasured by secondary ion mass spectrometry (SIMS). Only amorphous target materials whereused for the measurements.
Figure 2.4: Projected ranges in silicon of various ion species as a function of the implantation energy.
Figure 2.5: Projected ranges in silicon dioxide of various ion species as a function of the implantation
energy.
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Figure 2.6: Projected ranges in silicon nitride of various ion species as a function of the implantation
energy.
Figure 2.7: Projected ranges in aluminum of various ion species as a function of the
implantation energy.
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Figure 2.8: Projected ranges in the photo resists KTFR of various ion species as a function of the
implantation energy.
Figure 2.9: Projected ranges in the photo resist AZ-7500 of various ion species as a function of the
implantation energy.
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Figure 2.10: Comparison of the functional behavior of the stopping power in the low ion energy regime
of two ion species.
According to Fig. 2.4 - Fig. 2.9 generally the projected range of an ion is all the higher the lowerthe mass of the implanted particle. Therefore boron has the largest projected range from theanalyzed particle species, while antimony has the shortest projected range.
An exception of this rule can be observed at low energies. Below 20 keV the projected range ofantimony is slightly lower than the projected range of arsenic for the target materials silicon,
silicon dioxide and the photo-resist AZ-7500. For all other target materials the projected rangesof antimony and arsenic are approximately equal. This effect can be explained by the fact thatthe stopping of the ions is dominated by nuclear stopping in the lower energy regime while it isdominated by electronic stopping in the high energy regime as will be explained in Sec. 3.3.1.The stopping power due to electronic stopping is proportional to the charge of the ion. Thereforethe projected range decreases with increasing ion charge. In principle the stopping power due tonuclear stopping also increases with increasing ion charge, but the nuclear stopping powerreaches a maximum at a certain energy and this maximum moves to higher energies if the ioncharge is increased. For low ion energies the stopping power can therefore be inverselyproportional to the charge of the ion as illustrated in Fig. 2.10.
Another interesting effect is that the difference in the projected ranges becomes smaller also forvery high ion energies as can be seen especially in Fig. 2.8 for the ion species boron andphosphorus, and in Fig. 2.9 for the ion species phosphorus and arsenic. The reason for this effectis that also the electronic stopping power reaches a maximum. The position of this maximum isall the lower the lower the mass of the ion.
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2.2.3 Implantation Dose
The implantation dose determines the number of ions which hit the implantation target. It ismeasured by counting the electrons that are necessary to neutralize the charge on the waferintroduced by the positively charged ions. These electrons are introduced into the system by
connecting the wafer to an electron source, but also electron flood guns and plasma floodguns [91], which shoot electrons through the surface into the wafer. Thereby also isolatingmaterials can be neutralized and a charge-up of insulating surfaces can be avoided.
A critical parameter for the definition of the implantation dose is the implant area, because thedose is defined as concentration per area. When simulating ion implantation often two definitionsof the implantation dose are applied, which differ if the ion beam is not incident perpendicular tothe wafer surface. One definition refers to an area perpendicular to the ion beam, the otherdefines the implantation area as being parallel to the wafer surface, which we use throughout thistext.
2.2.4 Tilt and TwistAngle
The angle between the wafer surface normal and the ion beam is the tilt angle. A non zero tiltangle is used to avoid channeling effects in crystalline silicon, to introduce dopants into thesidewalls of a trench or to implant dopants underneath a mask edge by large tilt angel implantslike large tilt angle implanted drain (LATID) orlarge tilt angle implanted punch-throughstopper (LATIPS).
Additionally the twist angle is necessary to completely describe the direction of incidence of theion beam. It is the angle between the plane containing the ion beam and the wafer normal, andthe plane perpendicular to the primary flat of the wafer containing the wafer normal (Fig. 2.11).
The primary flat defines the orientation of the silicon crystal. It is aligned to a [011] direction in
a 100 oriented wafer. Besides the primary flat a secondary flat is used to definitely identifya wafer type, differing by crystal orientation and background doping (Fig. 2.12).
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Figure 2.11: Definition of the tilt and the twist angle of the ion beam (blue).
Node 24
Figure 2.12: Wafer types identified by the orientation of the primary and the secondary flat. The name
of the wafer type indicates the background doping and the orientation of the wafer normal.
2.3 Target Materials Properties
For ion implantation it is very important to distinguish between single crystalline materials, poly-crystalline materials, which consist of small crystals, called grains and amorphous materials,because the isotropy of the material has a strong influence on the penetration depth of theimplanted particles. A semiconductor device consists of several materials, a crystallinesemiconductor substrate (in this work only silicon is considered), poly-crystalline semiconductorlayers, amorphous isolation layers (silicon dioxide, silicon nitride) and amorphous metallayers (aluminum, copper). The following sections summarize the physical properties related to
ion implantation of the most important materials.
2.3.1 Crystalline Silicon
In semiconductor devices mainly two layers are made of crystalline silicon. On the one hand theinitial wafer substrate. It is produced either by the Czochralski crystal pull method [19] or by thefloating-zone crystal growth technique [19]. Impurities (dopants) are added to the silicon in orderto set the resistivity of the wafer in a range from 0.1 cm - 50 cm. On the other hand often
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an epitaxial layer (same crystal structure as the underlying wafer) is grown on the substrate by ahigh temperature CVD process. These epitaxial layers are used to form buried layers or to put alightly doped layer on top of a heavily doped substrate [19].
The atoms in crystalline silicon are arranged in a diamond lattice structure with a lattice constant
of 5.4307. Fig. 2.13 and Fig. 2.14 show a model of the silicon crystal seen along the 110
and the 100 directions [45]. Along these crystalline directions the lattice atoms formchannels with a diameter of approximately 3.3(0.6 of the lattice constant) and 1.6(0.3 of thelattice constant). These channels can be used by implanted ions to penetrate rather deep into thetarget (channeling effect), because the scattering probability is reduced for a particle movingalong a channel.
Along a random direction, for example by tilting the wafer by 7 no channel can berecognized. Therefore these ion beam directions are preferred to generate shallow dopingprofiles.
Node 26
Figure 2.13: Model of a silicon crystal seen along the 110 direction.
Figure 2.14: Model of a silicon crystal seen along the 100 direction.
The most important physical properties relevant for ion implantation are presented in Tab. 2.2and discussed in depth in [19], [25], [66], [83].
Table 2.2: Physical properties of silicon at 25 C
Atomic number 14
Lattice constant 5.4307
Atom radius 1.18
Atomic density 5.02 1022cm-3
Density 2328kg/m-3
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Thermal conductivity 0.46W/cm K
2.3.2 Polycrystalline Silicon
Polycrystalline silicon (polysilicon) has found many applications in integrated circuits.Depending on the doping concentration it is used as conductor (gate in metal oxidesemiconductor field effect transistors (MOSFET)[20]) or as a resistor (high value resistor inmemory cells [3]). Polysilicon is deposited on the wafer by low pressure chemical vapor
deposition (LPCVD) making use of the decomposition of silane (SiH ). It consists of smallcrystallites called grains separated by thin regions called grain boundaries. The grain sizeincreases with an increase in the deposition temperature [48] and it depends on the in-situ(dopants are added during the deposition process) doping concentration. The average grain size
ranges from 0.3 m to 1.0 m while the grain boundaries (interface between two grains with
different crystal orientation) are only 0.5 nm to 1 nm wide.
2.3.3 Silicon Dioxide
Table 2.3: Physical properties of silicon dioxide [19]
Atomic number
Silicon 14
Oxygen 8
Atom radius
Silicon 1.18
Oxygen 0.65
Molecular density (thermal) 2.3 1022cm-3
Density (thermal dry oxidation) 2270kg/m-3
Density (thermal wet oxidation) 2180kg/m-3
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Thermal conductivity 3.2 10-3W/cm K
Silicon dioxide (SiO ) is used as an insulator between semiconductor devices or as a high quality
dielectric for MOSFETgates. Whenever silicon is exposed to air a small film of silicon dioxide (native
oxide) with a thickness of approximately 1 nm is formed on the surface. Two types of processes are used
to build thicker SiO layers. On the one hand side thermal oxidation of silicon is performed which
generates high quality interfaces between silicon and silicon dioxide, and on the other hand side oxide
films can be deposited by a chemical vapor reaction. This technique is preferred to fill trenches, to
create a thin insulator between layers, or to build a diffusion source or getterer. For these applications
the oxide is doped during deposition. The thermally grown as well as the deposited silicon dioxide is
amorphous, the average length of a silicon oxide bond is 0.162 nm and the distance between the oxygen
ions is 0.227 nm. Some properties ofSiO are summarized in Tab.2.3, where also some differences
between thermal grown and deposited SiO are emphasized.