A CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications (ISSCC2006 paper 14.8)A CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications (ISSCC2006 paper 14.8)

Speaker: Bing-Yu Hsieh

MediaTek Inc.,

Hsin-Chu, TaiwanAuthors:

Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang, Benjamin Chiu, Alex Ho

Outline Outline

Overview

System Architecture

Solutions for Low Power Issue

Performance Comparison

Summary

Overview Overview

Highly Integrated Commercial Application Integrated Analog Front-End Built-in 1.5Gb/s SATA PHY On-Chip Write Strategy Generator PRML Read Channel Low Power Control

Supports Multiple Format of Discs CD/DVD-dual/DVD-RAM Record/Playback

Operation Speed up to 56xS/18xS/16xS

MCU

AnalogFront-End

SATAPHY

BufferManage DRAM

TXRX

FMSOCWriteStrategy

Generator4 LVDSChannel MOD RS

Encoder

ClockGen.

RFEQServoDSP

MotorDriver

AudioAmp.

Audio

DEM RSDecoderDVD-RAM Ctl.

PRML6bA/ D

System Architecture of FMSOC System Architecture of FMSOC

Pick-upSpindle

ARCHITECTUREARCHITECTURE

RTLRTL

BACK-ENDBACK-END

Optimization Efficiency

Solutions for Low Power Issue Solutions for Low Power Issue

Efficient DRAM Access

Adaptive Clock Control

Multiple Clock Design

Clock Suppression and Gating

Voltage Partition

Reduce Clock Buffer

Efficient DRAM Access - Bandwidth Efficient DRAM Access - Bandwidth

Large DRAM B.W. Requirement DRAM is shared to multiple functions

DRAM Access Efficiency Performance Index: Ave. cycle # to access each word Dominated by the times of DRAM Row Addr. Change

)]Efficiency(Access clock) (DRAMB.W.) (DRAM [

PI Enc/ Dec

PO Enc/ Dec

HOST inteface

uP Access

ExternalDRAM

BufferManagement

Efficient DRAM Access - Recursive EncodeEfficient DRAM Access - Recursive Encode

DRAM(ECC Data)

jikB ),*16(

512BSRAM

Paritygenerator

jikR ,1

jikR ,

512BSRAM jiR ,

11

Access on-chip SRAM Col-by-Col

Access off-chip DRAM Row-by-Row

16ro

ws

32 cols

B0,0 B0,31

B15,0 B15,31

16ro

ws

32 cols

B0,0 B0,31

B15,0 B15,31

Adaptive Clock Control - Background Adaptive Clock Control - Background

Data Rate of Optical Storage Varies with: Rotation Speed Radius of the Access Point

Numerical Controlled Oscillator Adaptive Control with Linear Steps

6.4X 16X

clo

ckfr

eq

.

Throughput Rate

Adaptive sys. clock

Fixed clock freq.

Min. required frequency

Adaptive Clock Control - Architecture Adaptive Clock Control - Architecture

Automatically adjust system clock with linear increments according to a throughput rate indicator

En/DecodeData Path

indicator

Digital LPFThroughput Rate

Detector

Minimum FrequencyDetection Loop

dn

up

NCO

Adaptive Clock Control - Performance Adaptive Clock Control - Performance

9.2DVD Read Speed (unit: xS)

12.5 16Sys

tem

Clo

ck F

req.

(uni

t: M

Hz)

30

40

50

60

15.3

70

42MHz

56MHz

67MHz73MHz

AdaptiveFreq.

Fixed Freq.

(70.4mA)

(81.5mA)

(90.1mA)(94.4mA)

(Digital Core Current)

Chip Micrograph Chip Micrograph

Chip Specification Chip Specification

Technology 0.18 m CMOS 1P6M

Supply Voltage 1.8V Core, 3.3V Analog & I/O

Core Area 27.5 (5.4x5.1) mm2

Transistor Counts ~10M

Max. Working Freq. 471MHz

Package 216 LQFP

Power Consumption

874mW DVD-R/RW/RAM 16xS W

772mW DVD-R/RW/RAM 16xS R

692mW CD 56xS W

664mW CD 56xS R

Comparisons of the Chip PerformanceComparisons of the Chip Performance

MediaTek(ISSCC 2005)

Tech.(um)

MediaTek(ISSCC 2005)This Work (FMSOC)

0.22

Area(mm2)Area

(mm2) (mW)Bitrate(Mbps)

Power* AFEBuilt-in

0.18

30.7

27.5

966

772

RAMWrite

242

471

Yes

Yes

No

Yes

MediaTek(ISSCC 2005) J. Kim, ICCE 2005 0.18 46 1400 209 No Yes

*The power is measured @ 16xS DVD except that J. Kim is @ 8xS DVD.

C. Tsai, ISSCC 2004

SATA

No

Yes

No

Summary Summary

Performance Single Chip SoC with CD/DVD-dual/RAM Operation

Speed up to 56xS/18xS/16xS

Integration SATA, WSG, PRML, Analog Front-End Integration

0.18 m CMOS with 27.5 mm2 die size 772mW @ 16xS DVD playback

Architectural Optimization for Low Power Recursive Parity Encode Adaptive Clock Control