Proceedings of the Second APSIPA Annual Summit and Conference, pages 427–430,Biopolis, Singapore, 14-17 December 2010.

A CMOS Integrated Driver Amplifier with

Programmable Gain for UHF RFID Reader

Xuesong Chen, Pradeep B. Khannur and Wooi Gan Yeoh * * Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research)

11 Science Park Road, Singapore Science Park 2, Singapore - 117685

E-mail: chenxs@ime.a-star.edu.sg Tel: +65-67705475

Abstract— This paper describes a CMOS integrated driver

amplifier (DA) design for a UHF RFID reader which meets EPC

Gen 2 standards and regulation requirement for most countries.

It is a highly linear class-A power amplifier delivering +10dBm

output power, with 16dB power control in 1dB step. All the

passive components including the matching network are

integrated on-chip in 0.18-µm CMOS technology. The DA covers

the full UHF band from 840MHz to 960MHz. The circuit

operates with a single 1.8V±10% supply and consumes total

drain current of 33mA. The operating temperature requirement

is from -25°C to +75°C.

I. INTRODUCTION

With the advantage of long read range and smaller tag size,

UHF RFID has wide applications in item tracking and tracing,

inventory monitoring and management, anti-theft, electronic

payment, access control, anti-tampering, etc. [1]. EPC Global

protocol is becoming more popular and most countries have

specified frequency band and power regulations for UHF

RFID applications. Currently, the corresponding tags are quite

cheap with big volume, but the readers in the market are

mainly built with discrete components which are costly and

big in size. The demand of integrated reader chips is high. In

addition, a reader chip makes it possible to integrate RFID

feature in various mobile devices like cellular phones, which

is a big potential for RFID applications.

Power amplifier plays a key role in a RFID reader as it

provides RF energy to passive tags wirelessly. There are two

challenges to design a power amplifier for a reader chip: one

is the linearity to meet spectrum mask specified by RFID

standards, the other one is the output power required for RFID

applications. The stringent spectrum mask requirements come

from Europe ETSI RFID standard [2] and EPC standard [3]

for dense reader mode. The output power is from 0.25W to

1W for long range readers, 1mW to 100mW for short range

handheld readers. From the system point of view, the reader

IC is mainly targeted for short range handheld readers, and

external high power amplifier is used for fixed long-range

readers. Taking these considerations into account, the

proposed driver amplifier is targeted to deliver 10mW power

and operate in class-A mode. As part of the system, other

requirements to the driver amplifier include 16dB

programmable power control in 1dB step, power down

control and operating environment from -25°C to 75°C. Table

1 gives the design specifications.

II. CIRCUIT IMPLEMENTATION

Fig. 1 is the block diagram of the proposed driver amplifier.

It is designed using a 0.18-µm CMOS process with a substrate

resistivity of 10 Ω-cm. The process has 6 metal layers with

thick top metal layer of 2-μm and MIM capacitors. All the

inductors used are on-chip and designed on the thick top

metal layer. The input matching circuit and output matching

circuit are on chip without any external components.

Fig. 1. Block diagram of the driver amplifier.

The programmable attenuator is designed using passive

resistor networks which consist of attenuation from 0dB to

15dB selected by 4 bits digital control signals [4]. One

advantage of using the passive resistor networks is that it is a

wide band matching circuits. Another advantage is that the

linearity and impedance do not change with input power.

Figure 2 shows the block diagram of the programmable

attenuator. One disadvantage is the power consumption is

same even at lower output power with attenuation control.

The passive resistor networks are designed with 100Ohm

Programmable

Attenuator Power

FETs

RF IN

Digital control bits

OM IM

Power down control

Bias supply

Table 1 Design specifications

Frequency range 840~960 MHz

Input impedance 100 Ohm

output impedance 50 Ohm

Gain 15 dB

IMD(Po=7dBm) 25 dBc

Output P1dB 10 dBm

Gain Control 16dB @1dB step

RF OUT

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10-0104270430©2010 APSIPA. All rights reserved.

input and output impedance for larger resistance which suffer

less from process variance.

Fig. 2. Block diagram of the programmable attenuator.

Only one of the 4-to-16 demultiplexer’s outputs is high and

selects the corresponding attenuator network with the

switches “on”. The other attenuator networks are isolated with

the switches “off”. A “Π” resistor network is chosen for the

passive attenuator. Figure 3 below shows the circuit diagram

of the attenuator core.

Fig. 3. Schematic of Attenuator Core.

Layout of the resistors used for the attenuators need to be

done carefully to improve the accuracy. The size of M1 and

M2 is chosen in the consideration of the switch’s loss and

isolation between input and output. The bigger size of the

switch gives lower loss, but the isolation is poorer.

Following the programmable attenuator is the driver

amplifier core. A cascode structure has been chosen for the

driver amplifier for better isolation between the input and the

output nodes. It improves the stability factor which is very

critical in power amplifier design. Figure 4 shows the

schematic diagram of the driver amplifier core.

Fig. 4. Schematic of the driver amplifier core.

M1 and M2 are the transistors for cascode structure which

use RF models. M1 is biased at class-A mode, the bias

voltage comes from PTAT connected through R2. M2 is self

biased from the output through R1 and C3, which is able to

improve the linearity [5]. M3 and M4 are used to power down

transistor M2. M3 is a PMOS transistor which is used to

switch on and off the gate voltage of M2. When the control

voltage is low, the gate voltage of M2 is supplied from its

drain. When it is high, the gate voltage is cut off from its

drain. M4 is a NMOS transistor which is part of the power off

control circuit. The function of M4 is to connect the gate of

M2 to ground to avoid floating in power down condition. L1,

C4 and C5 are the output matching circuits which match 50

Ohm to the optimum load impedance for maximum power.

The optimum load impedance is found with load-pull

simulation. L1 also functions as DC feeding. C6 is a big

decoupling capacitor for DC supply. C1, L2 and C2 are the

input matching circuit. All of the passive components are

integrated on chip.

The circuit is expected to operate in the temperature range

from -25°C to 75°C. To maintain the same performance over

the wide temperature range is quite difficult for CMOS

technology. Usually over design or complicated temperature

compensation circuit are used to overcome the problem. In

this work, the bias voltage is generated from a PTAT circuit

which has the reverse characteristic over temperature to the

driver amplifier. The performance over temperature is

compensated a lot with this kind of bias circuit. Some

simulation results are shown in next section.

III. LAYOUT AND SIMULATION

Layout is very important for a power amplifier design to

with impacts of parasitic and substrate coupling. More

attention has been paid to the layout design in the aspects of:

1) isolation between the output trace and the input trace; 2)

Good ground connection for current flowing out; 3) short RF

traces to reduce loss. Fig. 5 is the fabricated chip

microphotograph. The inductors are very sensitive to coupling

M1 M2

RB RB

RA

R1 R2

SW1 SW2 Attenuator

RF In RF Out

Control

SW1 SW2 0dB

ATTR.

4-to-16

Demulti

-plexer.

SW1 SW2 1dB

ATTR.

SW1 SW2 2dB

ATTR.

SW1 SW2 15dB

ATTR.

SW1 SW2 3dB

ATTR.

RF IN RF OUT

…

…

…

RF In

RF Out

VDD

Control

C1 C

2

C3

C6 C4

R1

L2 R2

C

5

L1

M1

M

2

M3

M4

Bias

428

hence they are separated as far as possible. The power

transistor’s source is connected to ground with a big area

which has a large parasitic capacitance functioning as a

ground to RF signals.

Fig. 5. Microphotograph of the chip.

The layout parasitic and package/bond-wire models were

included in the simulation. The simulated stability factor is

show in Fig. 6.

Fig. 6. Simulated stability factor.

Fig. 7 shows the simulated bias voltage from the PTAT

versus temperature. The corresponding output power changes

over temperature at -5dBm input is shown in Fig. 8.

Fig. 7. Simulated bias voltage over temperature.

Fig. 8. Simulated output power over temperature.

IV. MEASUREMENT RESULTS

The chip was fabricated in 0.18-µm standard CMOS

process and packaged in a 24-pin QFP package. The die area

including IO pads is 1.8mm2. The device was evaluated using

low cost 0.8-mm thick dielectric FR4 PCB with 1.8V DC

supply. The measured results are very close to simulation for

most parameters.

Fig. 9 shows the frequency response from 300MHz to

1.5GHz over the band. Fig. 10 shows the two tone inter-

modulation test results at +7dBm output power.

Fig. 9. Frequency response over the bandwidth.

Fig. 10. Two tone inter-modulation test at +7dBm output power.

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Fig. 11. Digitally programmable power gain control in 1dB step.

The 1dB power gain control was tested at 910MHz and the

result is shown in Fig. 11. It has a good accuracy in the lower

range control but not able to reach higher attenuation.

Investigation has been done and the reason is probably due to

the layout was not optimized for process variance.

The device has also gone through temperature testing from

-25°C to 75°C. The gain varied by 3.6 dB. Table 2 is a

summary of the measurement results.

V. CONCLUSION

In this paper, we have presented a high linearity driver

amplifier designed for UHF RFID reader IC with CMOS

process technology. The linearity is very good and meets the

system’s requirement. The power gain is digitally

programmable in 1 dB step using resistor attenuator networks.

The gain variance over temperature is minimized by the

compensation of the bias voltage from PTAT. Effects of

parasitic and substrate coupling from layout have been

addressed.

ACKNOWLEDGMENT

The authors wish to thank the colleagues from Institute of

Microelectronics for their help of device packaging and CAD

support.

REFERENCES

[1] S Lahiri, RFID Sourcebook. Prentice Hall PTR, August 2005,

ch. 4.

[2] ETSI EN 302 208-1 V1.1.2, European Standard, 2006-03.

[3] EPCTM Radio Frequency Identification Protocols Class-1

Generation-2 UHF RFID, Version 1.0.9, January, 2005.

[4] P. B. Khannur, “A CMOS power amplifier with power control

and T/R switch for 2.45-GHz Bluetooth/ISM band

applications,” IEEE RFIC Symp. Dig., pp. 145-148, June 2003.

[5] T. Sowlati,and D. M. W. Leenaerts, “A 2.4-GHz 0.18-µm

CMOS self-biased cascade power amplifier,” IEEE J. Solid-

State Circuits, vol. 38, no. 8, pp. 1318-1324, August 2003.

Programmable Attenuator

0

2

4

6

8

10

12

14

16

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Digital Control

Att

en

uati

on

Table 2 Performance Summary.

Parameters Measured Results

Frequency 840~960 MHz

Operating voltage 1.8±10% V

Output P1dB 10 dBm

Gain 13 dB

IMD(Po=7dBm) 28 dBc

DC Current 33 mA

PAE 16 %

Power Control 12dB @1dB step

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