A Calibrated Phase and Amplitude Control System

for Phased-Array Transmitters

Cameron T. Charles

A dissertation submitted in partial fulfillmentof the requirements for the degree of

Doctor of Philosophy

University of Washington

2006

Program Authorized to Offer Degree: Electrical Engineering

University of WashingtonGraduate School

This is to certify that I have examined this copy of a doctoral dissertation by

Cameron T. Charles

and have found that it is complete and satisfactory in all respects,and that any and all revisions required by the final

examining committee have been made.

Chair of the Supervisory Committee:

David J. Allstot

Reading Committee:

Hui Liu

Brian P. Otis

Jay Rajagopalan

Brian N. Bershad

Date:

In presenting this dissertation in partial fulfillment of the requirements for the doctoraldegree at the University of Washington, I agree that the Library shall make itscopies freely available for inspection. I further agree that extensive copying of thisdissertation is allowable only for scholarly purposes, consistent with “fair use” asprescribed in the U.S. Copyright Law. Requests for copying or reproduction of thisdissertation may be referred to Proquest Information and Learning, 300 North ZeebRoad, Ann Arbor, MI 48106-1346, 1-800-521-0600, to whom the author has granted“the right to reproduce and sell (a) copies of the manuscript in microform and/or (b)printed copies of the manuscript made from microform.”

Signature

Date

University of Washington

Abstract

A Calibrated Phase and Amplitude Control Systemfor Phased-Array Transmitters

Cameron T. Charles

Chair of the Supervisory Committee:Professor David J. Allstot

Electrical Engineering

A system is proposed that allows the phase and amplitude of a signal to be accu-

rately set and regulated over process and power supply variations. The intended

application is in a phased array transmitter, where the phase and amplitudes of the

array elements are electronically adjusted to shape and steer the beam of radiation

in the chosen direction. Phase and amplitude errors introduced in the array elements

lead to degradation of the array pattern through effects such as sidelobe growth and

reductions in directivity.

The conventional means of setting the phase in a branch of a phased array is

through look-up tables storing the control voltage - phase relationships for the phase

shifter. This method does not compensate for changes in these relationships intro-

duced by processing variations between fabricated devices or changes in operating

conditions such as power supply voltage and temperature. Additionally, if the phase

shifter has variable gain over the phase control range then the amplitude will vary

depending on the phase setting. The proposed system uses a variable gain amplifier

(VGA) in conjunction with the phase shifter to compensate for the variable losses of

the phase shifter and simultaneously provide a means of adjusting the amplitude of

the signal. Dual feedback loops are employed to set the control voltages for the phase

shifter and VGA, allowing the phase and amplitude to be closely regulated across

process variations and adjusted to compensate for changes in operating conditions.

The phase shifter is implemented as a reflective-type phase shifter which provides

up to 310 of phase shift, and the VGA is a narrowband implementation with a

resonant load that provides about 20 dB of gain and is intended to be used as a power

amplifier driver. The phase feedback loop includes buffers to remove the amplitude

dependancy of the signal, high-speed dividers, a charge pump, and an active loop

filter. The phase of the system is specified by digitally setting the charge pump

currents. The amplitude loop consists of an RF peak detector used in conjunction

with an active loop filter, and the amplitude is specified by setting an analog input

voltage to the loop filter.

The complete system has been fabricated in a 0.18 µm CMOS process, and assem-

bled on a custom printed circuit board using chip-on-board bonding to allow testing

and characterization. The system operates at 1.9 GHz, and the phase can be set with

5 bits of control over a 240 range, and the amplitude can be varied over a 20 dB

range. The amplitude feedback loop reduces the variation in |S21| across the phase

control range from 12.1 dB for the open loop case to 0.4 dB. The phase feedback

loop reduces the variation in 6 S21 across the amplitude control range from 32.1 to

7.4. The standard deviation of the phase across the phase control range is reduced

from 9.4 to 1.8 for changing power supply voltages, and from 5.0 to 1.2 between

different test chips.

TABLE OF CONTENTS

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Chapter 1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Dissertation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Chapter 2: Phased Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Types of Multiple Antenna Systems . . . . . . . . . . . . . . . . . . . 7

2.2 Phased Array Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4 Phased Array Architectures . . . . . . . . . . . . . . . . . . . . . . . 24

2.5 Phased Array Applications . . . . . . . . . . . . . . . . . . . . . . . . 27

Chapter 3: Previously Published Work . . . . . . . . . . . . . . . . . . . . 29

3.1 Phased Array Calibration . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2 Phase and Amplitude Control Techniques . . . . . . . . . . . . . . . . 31

3.3 Proposed Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Chapter 4: Proposed System . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.1 Qualitative Explanation . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.2 Quantitative Explanation . . . . . . . . . . . . . . . . . . . . . . . . 43

4.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Chapter 5: Phase Loop Design . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.1 Phase Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.2 Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.3 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.4 Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.5 Charge-Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5.6 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

i

Chapter 6: Amplitude Loop Design . . . . . . . . . . . . . . . . . . . . . . 100

6.1 Variable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.2 Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

6.3 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Chapter 7: Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 121

7.1 Test and Measurement Circuits . . . . . . . . . . . . . . . . . . . . . 121

7.2 Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Chapter 8: Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

8.1 Future Research . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

ii

LIST OF FIGURES

Figure Number Page

2.1 Worldwide smart antenna deployments (source: Visant Strategies) . . 6

2.2 Categories of multiple antenna techniques. . . . . . . . . . . . . . . . 7

2.3 A phased array transmitter. . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 A phased array receiver, showing the relationship between the angle ofthe incident wave and the time delays at the antenna elements. . . . . 11

2.5 A cell that has been partitioned into three sectors, each using a direc-tional antenna, to allow frequency reuse within the cell through spacedivision multiple access. . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.6 A switched beam phased array. Users are transferred from one beamto another as they move through the cell. . . . . . . . . . . . . . . . . 14

2.7 An adaptive array differs from a switched beam array in that the mainlobe is continuosly variable, and the nulls can be placed to reject in-terferers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.8 A plane wave of electromagnetic radiation impinging on a linear an-tenna array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.9 Radiation pattern for a 4-element broadside antenna array. . . . . . . 17

2.10 Radiation patterns for a 4-element antenna array at 0, 30, 60, and90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.11 Radiation patterns for antenna arrays with M = 4 and M = 8 elements. 19

2.12 Radiation patterns for 8 element antenna arrays with d = λ/2 andd = λ elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.13 Radiation patterns for 8 element antenna arrays with equal amplitudeweighting, triangular amplitude taper, and binomial amplitude taper. 21

2.14 The effect of phase and amplitude errors on sidelobe amplitude. (After:[1].) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.15 The effect of phase quantization on the radiation pattern for an 8 ele-ment array steered to 21 from broadside. . . . . . . . . . . . . . . . 24

iii

2.16 Architecture choices for implementing a phase shift in a multiple an-tenna receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1 Points where phase and amplitude errors can be introduced in eachbranch of a phased array transmitter. . . . . . . . . . . . . . . . . . . 30

3.2 Comparison of the control voltage to phase relationships of three dif-ferent instances of the same phase shifter. . . . . . . . . . . . . . . . 33

3.3 Variation of the phase shifters from Fig. 3.2. . . . . . . . . . . . . . . 34

4.1 High level system diagram for phase/amplitude feedback system. . . . 37

4.2 System level block diagram. . . . . . . . . . . . . . . . . . . . . . . . 38

4.3 Transient behaviour of pulse generator block. . . . . . . . . . . . . . . 41

4.4 Transient signals for Iup = 3 · Idn . . . . . . . . . . . . . . . . . . . . 42

4.5 System diagram for quantitative analysis of phase loop . . . . . . . . 44

4.6 Transfer function for phase shifter model . . . . . . . . . . . . . . . . 45

4.7 Charge-pump output current for varying output phases . . . . . . . . 46

4.8 System diagram for quantitative analysis of the amplitude loop . . . . 47

4.9 Transfer function model for the VGA . . . . . . . . . . . . . . . . . . 48

4.10 Schematic for phase loop simulation. . . . . . . . . . . . . . . . . . . 49

4.11 Transient waveform for the control voltage, with a step in the charge-pump current applied at t = 1 µs. . . . . . . . . . . . . . . . . . . . . 50

4.12 Schematic for amplitude loop simulation. . . . . . . . . . . . . . . . . 51

4.13 Transient waveform for the amplitude loop control voltage, with a stepin the amplitude control voltage applied at t = 1 µs. . . . . . . . . . 52

4.14 Schematic for complete system simulation. . . . . . . . . . . . . . . . 53

4.15 Transient waveforms of the control voltages for the complete systemsimulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.16 Transient plot of control voltages for phase and amplitude controlschanging simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.1 Illustration of the vector addition performed by a vector modulatorphase shifter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.2 Phase variation of all-pass phase shifter with frequency. . . . . . . . . 59

5.3 Distributed phase shifter implementations: (a) varactor loaded trans-mission line, (b) lumped element implementation. . . . . . . . . . . . 60

5.4 Operation of a reflective-type phase-shifter. . . . . . . . . . . . . . . . 62

iv

5.5 Lumped element hybrid 90o coupler. . . . . . . . . . . . . . . . . . . 64

5.6 Simulated S31 and S41 of the lumped element coupler (including par-asitics). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.7 Reflective loads: (a) Varactor, (b) Single resonated load (SRL), (c)Transformed single resonated load (TSRL), (d) Dual resonated load(DRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.8 RTPS phase shift superimposed on TSRL impedance over the varactorrange. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.9 Effect of zero location (value of CN) on phase shift characteristics. . . 68

5.10 Phase shift range vs. zero location (value of CN). . . . . . . . . . . . 69

5.11 TSRL with inclusion of parasitics: (a) Series resistance, (b) Parallelcapacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.12 The effect of parasitic series resistance on phase shift characteristics. . 71

5.13 The effect of parasitic parallel capacitance on the phase shift charac-teristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.14 Schematic of the TSRL of the implemented RTPS. . . . . . . . . . . 74

5.15 Die photo of the implemented RTPS. . . . . . . . . . . . . . . . . . . 76

5.16 Measured phase shift range of the implemented RTPS. . . . . . . . . 76

5.17 Measured loss of the implemented RTPS. . . . . . . . . . . . . . . . . 77

5.18 Measured noise figure of the implemented RTPS. . . . . . . . . . . . 77

5.19 Schematic of the buffer block. . . . . . . . . . . . . . . . . . . . . . . 79

5.20 Delay introduced by the buffer across the input amplitude range. . . . 81

5.21 Conventional frequency divider block diagram. . . . . . . . . . . . . . 82

5.22 Divider core schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.23 Divider multiplexer schematic . . . . . . . . . . . . . . . . . . . . . . 84

5.24 Timing diagram for pulse generator. . . . . . . . . . . . . . . . . . . . 84

5.25 State diagram for pulse generator. . . . . . . . . . . . . . . . . . . . . 85

5.26 System diagram for pulse generator. . . . . . . . . . . . . . . . . . . . 85

5.27 Schematic for pulse generator. . . . . . . . . . . . . . . . . . . . . . . 86

5.28 Schematic for a standard charge-pump. . . . . . . . . . . . . . . . . . 87

5.29 Schematic for a charge-pump with current steering to reduce chargeinjection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

5.30 Schematic for the new charge-pump with buffers and no switching. . . 89

v

5.31 Simulated transient current waveforms for the three charge-pump topolo-gies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

5.32 Toplogy of the phase loop filter. . . . . . . . . . . . . . . . . . . . . . 92

5.33 Schematic for the operational amplifier used in the phase loopfilter. . 93

5.34 Schematic of the reflective load as it appears to the loopfilter. . . . . 94

5.35 Approximate gain and phase relationships for the phase shifter and VGA. 97

6.1 Four VGA topologies: (a) variable feedback, (b) variable bias, (c) cur-rent steering, and (d) simple cascode. . . . . . . . . . . . . . . . . . . 101

6.2 Transistor model used for noise figure analysis. . . . . . . . . . . . . . 103

6.3 Schematic of variable gain amplifier. . . . . . . . . . . . . . . . . . . 106

6.4 Layout of the variable gain amplifier. . . . . . . . . . . . . . . . . . . 108

6.5 Simulated S21 for the variable gain amplifier. . . . . . . . . . . . . . 109

6.6 Simulated noise figure for the variable gain amplifier. . . . . . . . . . 109

6.7 Schematic for peak detector design and analysis. . . . . . . . . . . . . 111

6.8 Transient behavior of peak detector output voltage from Matlab sim-ulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.9 Transient behavior of peak detector output voltage from Cadence sim-ulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

6.10 Schematic for the amplitude loop filter. . . . . . . . . . . . . . . . . . 117

7.1 Schematic for the configuration register, showing 3 of the 20 bits. . . 122

7.2 Schematic of the Observe/Drive module used for the control voltages. 123

7.3 Photograph of the assembled printed circuit board. . . . . . . . . . . 125

7.4 Die photograph of the complete system. . . . . . . . . . . . . . . . . 127

7.5 Measured phase of S21 plotted against steps in the digital control bits. 129

7.6 Layout of the charge pump unit current elements, with the Up and Dnarrays denoted. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

7.7 Measured phase steps of S21 for each increment in the digital controlbits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

7.8 Measured phase of S21 for individual control bits (0 corresponds to onlythe fixed current elements being active). . . . . . . . . . . . . . . . . 132

7.9 Measured magnitude of S21 over the phase control range. . . . . . . . 134

7.10 Time domain waveforms of VGA and phase shifter control voltages fora step in the digital phase control bits. . . . . . . . . . . . . . . . . . 135

vi

7.11 Phase of S21 across the amplitude control range. . . . . . . . . . . . . 136

7.12 Time domain waveforms of VGA and phase shifter control voltages fora step in the desired amplitude input. . . . . . . . . . . . . . . . . . . 137

7.13 Phase characteristics for changing supply voltage with open loop oper-ation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

7.14 Phase characteristics for changing supply voltage with closed loop op-eration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7.15 Maximum deviation in phase characteristics across the control rangefor changing power supply voltage. . . . . . . . . . . . . . . . . . . . 140

7.16 Phase characteristics for three different test chips with open loop op-eration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

7.17 Phase characteristics for three different test chips with closed loop op-eration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

7.18 Maximum deviation in phase characteristics across the control rangefor three different test chips. . . . . . . . . . . . . . . . . . . . . . . . 144

vii

ACKNOWLEDGMENTS

viii

1

Chapter 1

INTRODUCTION

The era of wireless communications began in the 1860s when James Clerk Maxwell,

a Scottish Physicist, predicted the existence of radio waves. In 1886, a German

physicist names Heinrich Hertz was the first to verify that electromagnetic waves exist,

and propagate with a finite velocity. An Italian inventor named Gugliemlo Marconi

sent and received the first radio signals in 1895 using a spark gap transmitter, and

made headlines in 1899 by using his radio to provide up-to-the-minute coverage of the

America’s Cup yacht race. The vacuum tube was invented in 1907, and subsequently

the state of the art in radio advanced rapidly, with much of the early pioneering

work being done by Edwin Howard Armstrong, including the superheterodyne receiver

which he patented in 1917.

In recent years there has been tremendous growth in research into radio frequency

(RF) circuit design, driven largely by the advent of the cellular telephone and other

forms of wireless communications. The first cell phone call was made in 1973 by Dr.

Martin Cooper, a former general manager for the systems division at Motorola. Nine

years later the first American cellular service, AMPS (Advanced Mobile Phone Ser-

vice) was deployed in Chicago. This generation of cellular phone service was based on

analog modulation, and is known as 1G (for first generation). The next generation of

cellular phone service (2G) was based on digital transmission, and included the stan-

dards D-AMPS (Digital AMPS), CDMA (Code Division Multiple Access), and GSM

(Global System for Mobile Communications) in Europe. The third generation (3G)

of cell phone service added data transmission capabilities, allowing users to transmit

2

e-mail, send text messages, and access the internet. Work is presently underway on

standards for the fourth generation (4G) of cell phone systems, and while the scope of

this generation has not been fully specified, it is clear that it will require increased data

rates as compared to 3G systems. Also driving the need for increased data rates in

wireless communications systems are wireless local area network (WLAN) standards.

The most prominent WLAN standards are IEEE 802.11a, b, and g (also known as

Wi-Fi). These standards accommodate data rates up to 54 Mbps, and many new

home and office network installations use these for their benefits of easy installation

and user portability. An emerging WLAN standard, IEEE 802.11n, will triple the

data rates of the existing standards. Personal wireless connectivity standards such as

Bluetooth which allow users to achieve high data rates over short distances have also

grown in popularity.

Bandwidth is a scarce commodity in modern communications systems, with the

Federal Communications Commission (FCC) deciding which parts of the spectrum can

be used for emerging communications standards. The easiest way to accommodate

the rising data rates required by new communications standards is to increase the

bandwidth. This is often not possible, so engineers are forced to make the most of

the limited bandwidth that is available.

In the past this has involved improving spectral efficiency using time and fre-

quency domain methods, such as moving to more complex modulation schemes like

M-ary PSK, QAM, etc. [2]. These modulation schemes allow each transmitted sym-

bol to represent multiple bits, thus increasing data rates without affecting the the

bandwidth. The limiting factor with these methods is the requirement for higher

signal-to-noise (SNR) ratios. One way of improving the SNR ratio is to simply use

more power to transmit the signal, but this causes problems with battery life and

IIP3 limits of power amplifiers, and is not effective in most modern wireless networks

(which are interference limited).

As it becomes increasingly difficult to attain further improvements in data rates

3

through time and frequency domain methods, communications engineers are turning

to spatial methods. The use of cells allowing frequency reuse in a modern cellular

phone system is one example of a spatial method. Currently the most active spatial

research area is multiple antenna systems [3]. While there are several ways in which

multiple antennas can be exploited in a wireless system (as will be discussed in the

next chapter), the focus of this work is on beamforming applications. The most basic

requirement for a beamforming (or phased array) system is the ability to accurately

set the phase and amplitude of the signal being transmitted (or received) on each an-

tenna. This work investigates a system which compensates for the variable amplitude

response of an RF phase shifter over its phase range while simultaneously allowing

both the phase and amplitude in each branch of a phased array transmitter to be

accurately set.

1.1 Dissertation Overview

This dissertation is organized in the following manner. Chapter 2 provides an intro-

duction to the different types of multiple antenna systems, with a focus on phased

arrays which are the target application of this work. Basic concepts pertaining to

phased arrays are reviewed, and discussion on the importance of calibrating the phase

and amplitude of each path in a phased array is provided. Chapter 3 reviews the state

of the art in phased array calibration methods, and presents details on recent pub-

lications addressing this topic. Chapter 4 describes the system being proposed in

this work. The system is initially presented from a qualitative standpoint to give an

overview of the operation of the system as a whole, and then a quantitative system-

level analysis is provided accompanied by simulation results. Chapter 5 describes the

circuit-level implementations of each of the components in the phase loop, starting

with the phase shifter. A more rigorous analysis of the phase loop dynamics is also

provided in this chapter to arrive at the design of the loop filter. Chapter 6 describes

the circuit-level implementations of the components in the amplitude loop, starting

4

with the variable gain amplifier. Similar to the previous chapter, a more rigorous

examination of the amplitude loop dynamics is also presented. Chapter 7 describes

additional circuitry that was designed for test and measurement purposes, and then

presents the measurement results from the fabricated system. Finally, conclusions are

drawn in Chapter 8.

5

Chapter 2

PHASED ARRAYS

As mentioned in the previous chapter, recent years have seen growing interest in

the use of multiple antennas in communications systems as a means of increasing

data rates without requiring additional bandwidth. The basic definition of a multiple

antenna system is any configuration of several antenna elements at the transmitting

and/or receiving side of a communications link whose signals are processed adaptively

in order to exploit the spatial dimension of the wireless channel [4].

The logarithmic relationship between the capacity of a wireless link and the signal-

to-interference-and-noise ratio (SINR) has been recognized for many years [5], and

one obvious way to improve data rates over a wireless channel is simply to increase

transmit power levels. However, in the case of a mobile user this is extremely costly in

terms of battery life. In the context of interference-limited multi-user cellular systems,

increasing the transmit power provides no net gain as the interference received from

other users increases along with the signal received from the desired user. Most

mature cellular systems are interference limited [6], so this is not a viable option. As

mentioned previously, increasing the bandwidth is also an undesirable solution (and

may not even be possible), as bandwidth is an expensive and limited resource.

Multiple antenna systems achieve increases in channel capacity by exploiting the

spatial dimension of a wireless link. The type and degree of channel capacity im-

provement depends on the multiple-antenna technique being used. The concept of

exploiting the spatial dimension is not new, as cell sectorization allowing frequency

reuse (the fundamental concept upon which cellular communications networks are

built) can be regarded as a form of spatial processing [5]. Multiple antennas used

6

Figure 2.1: Worldwide smart antenna deployments (source: Visant Strategies)

for antenna diversity have been employed in cellular telephone base stations for a

number of years, where they mitigate the three major impairments caused by the

wireless channel: fading, delay spread, and co-channel interference. Recent studies

have reported that multiple antenna technology is now deployed in one of every 10

base stations worldwide, and deployment is expected to grow by 60 percent in the

next four years [4], as shown in Fig. 2.1. The same study showed that multiple an-

tenna systems have been implemented in base stations for as little as 30 percent more

cost than traditional base station antenna systems. As the push for higher data rates

intensifies, moves are now being made to incorporate multiple antenna technology in

mobile elements of wireless communications systems.

Multiple-antenna techniques can be grouped into three main categories, as illus-

trated in Fig. 2.2. The following section will briefly describe each of these techniques,

and the remainder of the chapter will be devoted to phased-array multiple antenna

systems, which are the target application for the work presented in this dissertation.

7

Figure 2.2: Categories of multiple antenna techniques.

2.1 Types of Multiple Antenna Systems

2.1.1 Diversity

Antenna diversity has been known for several decades [7], and has been employed in

cellular base stations for a number of years. The primary goal of diversity techniques

is to combat fading in the wireless channel. Fading results from the multiple paths

between the transmitter and the receiver over a wireless channel (caused by scatter-

ing). When the signals arriving from different paths cancel destructively, the received

signal undergoes what is known as a ”fade”, where the received signal power is greatly

reduced.

Diversity systems employ multiple antennas that are uncorrelated, and rely on

the the fact that they will undergo fading independantly from one another. When

one antenna is experiencing a fade, it is likely that some of the other antennas are

not, and a strong signal can still be received. There are several means of ensuring

8

that the different antennas in the system will be uncorrelated. The simplest is space

diversity, where the antennas are placed far enough apart to have uncorrelated signals.

The required distance will depend on the degree of scattering in the wireless channel,

but a distance of about 10 wavelengths is usually sufficient. Other approaches are

polarization diversity, where antennas with orthogonal polarizations are employed,

and angle diversity, where directional antennas are used. The benefit of the latter

two approaches is that the antennas can be housed in the same location.

Diversity techniques can be employed at either the receiver or the transmitter.

When employed at the receiver, there are three main techniques: switch diversity,

equal gain combining, and maximal ratio combining [8]. Switch diversity is the sim-

plest of the three techniques, where the antenna with the highest signal to noise ratio

(SNR) is determined, and this antenna alone is used with the receive chain. For equal

gain combining, the signals are co-phased and added together, similar to what is done

in a RAKE receiver. The drawback of equal gain combining is that if one antenna

has a low SNR, it will degrade the SNR of the entire system. To address this prob-

lem, maximal ratio combining can be used. In this scheme, the signals are weighted

according to their SNRs before co-phasing and combining them. In the presence of

noise, this leads to the best SNR for the overall system, but also has the highest

degree of complexity.

The diversity methods employed at the transmitter depend on how much channel

state information (CSI) is available. If perfect channel state information is available,

then any of the techniques described above for the receiver can also be employed

at the transmitter. This is often not the case, and there are a group of techniques

known as space-time coding techniques that can be used at the transmitter without

any knowledge of the channel characteristics. The most well known was proposed by

Siavash Alamouti [9], and involves transmitting a different signal on each antenna,

with delayed and redundant versions of each symbol being transmitted. By employing

some signal processing at the receiver, the same diversity benefits can be realized at

9

the transmitter as if the diversity were being implemented at the receiver.

2.1.2 Spatial Multiplexing

Spatial multiplexing evolved from seminal work done by Foschini and Gans [10] and

independantly by Telatar [11] in the late 1990s. Their work shed light on the pos-

sibility of using multiple transmit and receive antennas to achieve higher data rates

without any requiring extra bandwidth or transmission power. Telatar showed that

a wireless system using NT transmit antennas and NR receive antennas can theoret-

ically acheive data rates which are linearly proportional to the minimum of NT and

NR [11]. This result depends on the channel parameters being known at the receiver,

and on the path gains between the different antennas behaving independantly. In

practice these conditions will not be perfectly met and the theoretical linear increase

in data rates will not be realized, but significant increases in channel capacity are still

possible. This is an impressive result, in light of the fact that increasing the power

(and thus the SNR) in a single user system only leads to logarithmic improvements

in channel capacity.

Spatial multiplexing multiple antenna techniques require multiple antennas at

both the transmitter and the receiver, and send independant data streams over the

different transmit antennas. In these schemes, multipath interference is exploited to

establish multiple parallel channels operating simultaneously in the same frequency

band. The data streams are recovered and seperated at the receiver using interfer-

ence cancellation algorithms. The number of antennas at the receiver must be greater

than or equal to the number of antennas at the transmitter. As mentioned, spatial

multiplexing techniques can theoretically acheive a linear growth in channel capacity

with min(NT , NR). One of the most well known processing algorithms for this tech-

nique is the Vertical Bell Laboratories lAyered Space-Time (V-BLAST) algorithm

[12]. In this scheme, each receive antenna receives all of the signals radiated from

the NT transmit antennas, but the interence between the bit streams is removed by

10

Figure 2.3: A phased array transmitter.

using both optimum combining and interference cancellation. The emerging wireless

LAN standard, IEEE 802.11n is expected to mandate the use of spatial multiplexing

techniques to achieve its target data rates.

2.1.3 Phased Arrays

The third multiple antenna technique is the beamforming, or phased array technique.

Multiple antenna systems using this technique are sometimes also referred to as smart

antennas, or adaptive antennas. For beamforming, the same signal is transmitted

or received on each of the antennas, but a time delay and amplitude adjustment

is introduced at each antenna to shape the overall radiation pattern and focus it

in a particular direction. An intuitive picture of a multiple antenna beamforming

transmitter is shown in Fig. 2.3. In the presence of interferers, nulls can be introduced

in the pattern to limit the interferer’s effect on the received signal. This process is

also referred to as spatial filtering. A beamforming receiver is illustrated in Fig. 2.4

where the relationship between the angle of the incident wave and the time delays at

the antenna elements can be seen.

Phased array techniques work by improving the effective SNR at the output of

11

Figure 2.4: A phased array receiver, showing the relationship between the angle ofthe incident wave and the time delays at the antenna elements.

the receiver. If the antennas are spaced at a sufficient distance from one another, the

radiation noise of each antenna is uncorrelated, and the receiver noise sources in each

signal path are independant. As a result, the signals from the antennas add in ampli-

tude (coherently), while the noise adds in power (incoherently), creating a 10log(N)

dB improvement in the SNR for an N element phased array receiver. Intuitively,

the phased array can be thought of as focusing the transmitted (or received) energy

into a directional beam, so that more signal power arrives at the target than would

be the case for the same power being transmitted by a single isotropic antenna. To

express the advantage in terms of channel capacity, the single-user data rate bound

for a single transmit antenna and single receiver antenna system can be expressed

using Shannon’s equation as

C = B log2

(1 +

PT |h|2

σ2

)(2.1)

where B is the bandwidth, h is the channel gain, PT is the transmitted signal power,

and σ2 is the noise power. For N transmit or recieve antennas using beamforming

(assuming that the beam is steered in the proper direction), the channel capacity can

12

be expressed as

C = B log2

(1 +

NPT |h|2

σ2

)(2.2)

As N increases, the beam becomes more focused, with a corresponding increase in

channel capacity. In principle, all of the phased array techniques used for receivers

can be used at the transmitter.

Beamforming techniques can be implemented at either the receiver or the trans-

mitter, although to date most research efforts implementing beamforming systems for

communications have focused on the receiver, since the limited channel state informa-

tion (CSI) available at the transmitter can hamper the effectiveness of beamforming

techniques. However, in the case of a base station, the directional location of the

mobile user can be derived from the uplink [5], and CSI at the transmitter can also

be obtained through the use of feedback control sequences. Modern 3G wireless stan-

dards already employ feedback sequences for power control, adaptive modulation, and

closed loop diversity modes. Recent research has shown that even a few bits of feed-

back can provide performance close to that of having complete CSI at the transmitter

[13].

An elementary implementation of the space division multiple access (SDMA) prin-

ciples used in beamforming is the sectorization of cells in a modern cellular phone

network [14]. Sectorization (see Fig. 2.5) involves subdividing the cell into three or

six sectors with dedicated directional antennas and radio frequency (RF) paths. This

allows frequency channels to be reused within the same cell, increasing the capacity

of the cellular system. One limitation of the sectorization approach is that traffic

can be distributed unevenly throughout the geographical regions of a cell, leading to

unbalanced distributions of users between the sectors, saturating the network while

some sectors have unused capacity. Eliminating this imbalance would require sectors

with flexible orientations and beamwidths, but this is not possible with the directional

antennas used for conventional sectorization.

This leads to the use of antenna arrays which can be electrically configured through

13

Figure 2.5: A cell that has been partitioned into three sectors, each using a directionalantenna, to allow frequency reuse within the cell through space division multipleaccess.

phased array techniques. Phased arrays are typically used in one of two configura-

tions: switched beam and adaptive array. A switched beam system is considered an

extension of the current sectorization scheme, and employs an antenna array where

the phases of the signals on each antenna are adjusted to create a number of fixed

narrow beams (Fig. 2.6. As an individual user moves through the cell, the signal

strength is detected, and the user is passed from one beam to another.

Taking another step up in complexity and performance leads to adaptive array

systems. In these systems the beams are continuously steerable, and are adjusted to

track the user as they move through the cell. A primary advantage of these systems is

that in addition to adjusting the main beam to track the user, the nulls in the radiation

pattern can be placed to block interfering signals to yield the highest possible SNIR.

Another advantage of the adaptive array is that there is no need to hand off the user

between different beams, which leads to a degradation in throughput. The difference

14

Figure 2.6: A switched beam phased array. Users are transferred from one beam toanother as they move through the cell.

15

Figure 2.7: An adaptive array differs from a switched beam array in that the mainlobe is continuosly variable, and the nulls can be placed to reject interferers.

between a switched beam system and an adaptive array is illustrated in Fig. 2.7.

All phased array systems shape the radiation pattern of the array by adjusting the

complex weights of the different antenna branches, which will be discussed in the next

section.

2.2 Phased Array Theory

Antenna arrays can be laid out in a number of different configurations, including

linear, planar, and circular. For the purposes of this discussion, we will assume a

linear array of M antennas. We will assume a plane wave of electromagnetic radiation

is impinging on the array at an angle of φ relative to the axis of the antenna array, as

depicted in Fig. 2.8. The complex signal received by the antenna can be expressed as

S(φ) = Se(φ)Sa(φ) (2.3)

where Se(φ) is the element factor and Sa(φ) is the array factor. The element factor is

determined by the characteristics of the individual antennas in the array. In this dis-

cussion we will only be considering the effects of the array, and as such we will assume

16

Figure 2.8: A plane wave of electromagnetic radiation impinging on a linear antennaarray.

that Se(φ) = 1. The array factor accounts for the effects of the array configuration,

and can be expanded as [15]

Sa(φ) =M∑i=1

aiej(k0(i−1)d sin(φ)+ψi) (2.4)

where ai and ψi are the amplitude and phase adjustments performed at the ith antenna

element, d is the element spacing, and

k0 =2π

λ0

(2.5)

where λ0 is the wavelength of the radiation. Note that the angular frequency has been

omitted from (2.4), and it is assumed that the incoming radiation has a frequency

ω0. Also note that for this analysis the array is assumed to be operating in only two

dimensions.

17

Figure 2.9: Radiation pattern for a 4-element broadside antenna array.

Initially we will assume that the amplitude weights are all equal, and consider only

the effects of adjusting the phases of the different elements by changing ψi. If ψi = 0

for all of the elements in the array, it is said to be operating in broadside mode, and

the maximum array factor will occur at an angle of incidence φ = 0. A normalized

plot of the radiation pattern of an array with 4 elements operating in broadside mode

is shown in Fig. 2.9. The main lobe of radiation at 0 can be seen, with nulls and

sidelobes for angles of incidence moving towards 90. The sidelobes are undesirable,

as they result in interference and wasted power.

If we set a linear phase taper for all of the elements, so that

ψi = −k0(i− 1)d sin(φ0) (2.6)

where −90 ≤ φ0 ≤ 90, the array factor can be expressed as

Sa(φ) =M∑i=1

aiejk0(i−1)d(sin(φ)−sin(φ0)) (2.7)

Now by choosing a beam-pointing direction φ0 and by phasing the elements according

18

Figure 2.10: Radiation patterns for a 4-element antenna array at 0, 30, 60, and90.

to (2.6) we can steer the beam in the desired direction. Fig. 2.10 demonstrates an

array with 4 elements being scanned from φ0 = 0 to φ0 = 90. When φ0 = 90, the

array is said to be operating in endfire mode. From Fig. 2.10 it can be seen that the

width of the main lobe increases for larger scanning angles, more detail on this can

be found in [15].

The two variables that can be chosen in configuring the array are the number

of elements, M , and the spacing between the elements, d. The effect of increasing

the number of elements in the array is shown in Fig. 2.11. It can be seen that by

increasing the number of elements, the width of the main lobe is decreased and the

number of sidelobes and nulls in the pattern increases, while the level of the sidelobes

relative to the main lobe increases.

Fig. 2.11 shows that by increasing the size of the array through increasing the

number of elements, we can improve its performance. Another way to increase the

size of the array is to increase the element spacing, d. This is illustrated in Fig. 2.12

19

Figure 2.11: Radiation patterns for antenna arrays with M = 4 and M = 8 elements.

where the radiation pattern for an 8 element broadside array has been plotted for

d = λ/2 and d = λ. We can see that the width of the mainlobe has been reduced,

but there are now large sidelobes at the same level as the main lobe at −90 and 90.

These are referred to as grating lobes, and are undesirable as they result in wasted

power and interference. See [15] for a detailed discussion of grating lobes and the

conditions under which they appear.

Desirable characteristics for the radiation pattern of an antenna array are a narrow

main lobe and low sidelobe levels, which means that most of the energy is focused in

the main lobe. There are a number of metrics for quantifying these qualities, including

first null beamwidth and half-power beamwidth [14]. Another important metric is the

directivity of the array, which is given by

Do =4πUmaxPrad

(2.8)

where Umax is the power radiated per unit solid angle in the direction of maximum

radiation intensity (the main lobe) and Prad is the total power radiated by the array.

20

Figure 2.12: Radiation patterns for 8 element antenna arrays with d = λ/2 and d = λelements.

Until this point we have only considered the case where the amplitude weights

for all of the elements are equal. By choosing the amplitude weights differently, the

sidelobe levels and spacing can be altered. One approach is to taper the amplitude of

the elements moving out from the center of the array, which reduces the sidelobe levels.

Two variants of this approach are the triangular taper and the binomial taper [15],

illustrated in Fig. 2.13. It can be seen that in addition to reducing the sidelobe levels,

the width of the main lobe is also increased. There are numerous other methods for

setting the phase and amplitude weights to steer the main lobe and null out interferers,

more details on these can be found in [16].

2.3 Calibration

A phased-array transceiver can have errors present in the phase and amplitude settings

of the antenna elements. The errors can be introduced at any point from the RF chain

in the transceiver to the antenna, and can be caused by mismatches in the length of

21

Figure 2.13: Radiation patterns for 8 element antenna arrays with equal amplitudeweighting, triangular amplitude taper, and binomial amplitude taper.

the transmission lines feeding the different antennas, mismatches introduced by the

phase shifter, etc. These errors can be classified into two groups, static and dynamic

[17]. Static errors are caused by differences in component tolerances and physical

construction, and in larger arrays attempts are typically made to calibrate these errors

out. Dynamic errors result from the fact that the parameters of electronic components

vary with temperature and can drift over time [18], and can be eliminated through

periodic recalibration of the array. Changes in the absolute values of the phase and

amplitude do not affect the beam pattern, only changes in the relative phase and

amplitudes between elements [19], so if the phases and amplitudes drift in unison

then the array performance is not affected. In this work we will consider phase and

amplitude errors that are introduced in the phase and amplitude control modules of

each element, and assume that the rest of the antenna array operates in an ideal

manner.

22

Prior work has examined in detail the effect of phase and amplitude errors on the

array pattern [20], here we will summarize the key results that pertain to this work.

Random phase and amplitude errors lead to three nondesirable effects in a phased

array: increased sidelobe levels, reduction in directivity, and beam pointing error. For

this discussion the errors are defined as a phase error φn and an amplitude error δn

at array element n.

2.3.1 Sidelobes

As mentioned previously, the presence of sidelobes in the radiation pattern is un-

desirable, and a phased array is designed with the intent of minimizing them. The

most significant impact of phase and amplitude errors is to increase the size of these

undesirable sidelobes. The residual sidelobe level due to the phase and amplitude

errors (normalized to the isotropic level) can be expressed as [16]

σ2I = ge(φ2 + δ2) (2.9)

where ge is the element gain (directivity), φ2 is the variance of the phase error and δ2

is the variance of the amplitude error (both assumed to have a gaussian probability

distribution function with zero mean). From this it can be seen that as the variance

of the phase and amplitude errors increase, the sidelobe levels will also increase. A

plot of the residual sidelobe levels (relative to isotropic radiation) due to phase and

amplitude errors is shown in Fig. 2.14 [1].

From Fig. 2.14 it is evident that a phase (amplitude) error can be equated to an

equivalent amplitude (phase) error. It can be shown that [16] and amplitude error of

1 dB is equivalent to a phase error of 6.6.

2.3.2 Directivity

As defined previously, the directivity of a phased array is the ratio of the power density

in the direction of the main lobe to the power density from an isotropic source. In

23

Figure 2.14: The effect of phase and amplitude errors on sidelobe amplitude. (After:[1].)

the design of a phased-array system it is desirous to maximize the directivity. Phase

and amplitude errors cause a reduction in the directivity of the phased array, which

can be expressed as [20]

D

D0

=1

1 + δ2 + φ2(2.10)

Where D is the directivity of the array with errors and D0 is the directivity of the

error-free array. The reduction in directivity is usually insignificant compared to the

increase in sidelobes.

2.3.3 Beam Pointing Error

The third non-ideality introduced by phase errors is beam pointing error. For an array

of N elements with uniform amplitude, the variance of the beam pointing deviation

can be expressed as [16]

∆2 =12

N3φ2 (2.11)

24

Figure 2.15: The effect of phase quantization on the radiation pattern for an 8 elementarray steered to 21 from broadside.

2.3.4 Quantization Errors

Many phased-arrays make use of phase and amplitude control schemes with discrete

levels instead of a continuum of phases and amplitudes. This simplifies the control

circuitry, but also results in periodic phase and amplitude errors across the array.

The quantization errors are highly correlated, and they result in large, well-defined

sidelobe pattern errors called quantization lobes [16]. Fig. 2.15 compares the radiation

patterns resulting from 2 bits and 5 bits of phase quantization to the ideal case. It

can be seen that 5 bits of quantization provides a reasonable approximation to the

ideal case, with less than 2 dB of error in the radiation pattern.

2.4 Phased Array Architectures

There are a number of different phased-array architectures, differing in where to the

phase shift is inserted in the receive/transmit chain [21]. Four different options are

25

Figure 2.16: Architecture choices for implementing a phase shift in a multiple antennareceiver.

illustrated for the case of a receiver in Fig. 2.16, the same principles hold for the

transmitter.

The first option is to insert the phase shift in the radio frequency (RF) path (Fig.

2.16(a)), which has the advantage of minimal power consumption and area, since only

the antennas and phase shifters (and variable gain amplifiers if it is necessary to adjust

the amplitude of each path) must be duplicated, and the intermediate frequency (IF)

and baseband stages can be shared between all signal paths. Another advantage is

that since the interferers are nulled out at the RF stage, linearity requirements on the

IF/baseband stages can be relaxed.

The second option is to insert the phase shift at the IF stage (Fig. 2.16(b)),

which is desirable from the standpoint that it is easier to realize accurate phase

shifts at lower frequencies. Some disadvantages of this approach are that there will

be increased power and area consumption due to increased duplication (now each

26

antenna path requires a dedicated mixer for the downconversion to IF) and the phase

shifters themselves will be larger since the passive components required in a phase

shifter scale in inverse proportion to the frequency of operation, so inductors and

capacitors will be larger than they would be if the phase shifter was operating at RF.

The third option is to apply the phase shift to the local oscillator (LO) signal before

it is applied to the mixer (Fig. 2.16(c)). This scheme will have a power consumption

between that of the RF and IF phase shift architectures. It is attractive since it

relaxes the requirement for the phase shifter to have constant amplitude for varying

phase shifts. Since the mixers are typically hard driven, the LO stages are operated

in saturation, and variation in the phase shifter output will have a reduced impact. A

disadvantage of this scheme is that the time delay is not be applied to the modulated

signal, so for very wideband signals some distortion will be introduced. A detailed

derivation of this effect is given in [22]. However, for almost all communication systems

the bandwidths are such that the delay is negligible in the modulated signal.

The fourth option is to add an analog to digital (A/D) converter to each path

and perform the phase shift and any other required manipulation in the digital do-

main (Fig. 2.16(d)). This is an attractive option from a flexibility standpoint, as

the receiver/transmitter could be reconfigured for any of the MIMO techniques that

have been discussed. However, the additional A/D converters (one for each antenna)

greatly increase the power consumption, and it is difficult to design A/D converters

with adequate performance as the linearity, dynamic range, and speed requirements

are very stringent.

The four architectures shown in Fig. 2.16 can be grouped into two categories.

The first three architectures are analog implementations, and the fourth is a digital

implementation. The principle of analog beamforming has been known since the

1960s [23], while digital beamforming techniques have evolved more recently. The

advantage of the analog techniques is that they provide drastic reductions in power

dissipation and fabrication costs, since they eliminate the need to duplicate the entire

27

RF chains between the different branches [24]. Their limitation is that since the phase

shift is introduced after the baseband signals have been combined (for the case of a

transmitter), they are limited to single user or point to point communications. The

advantage of the digital approach lies in its flexibility, and its capacity for multi-user

beamforming [3]. It allows multiple beams to be formed and directed to an arbitrary

number of users.

This work will focus on analog beamforming, using the architecture presented

in Fig. 2.16(a). This architecture holds the possibility of minimizing the power

consumption and area, which are the motivating factors for considering the analog

architecture. The remainder of the discussion in this chapter will focus on analog

beamforming applications.

2.5 Phased Array Applications

Phased arrays have traditionally been used primarily for radar applications [25], [26].

Most of these applications are for military purposes, although there are emerging

applications in the civilian sector. One example is the development of short-range

vehicular radar systems for collision prevention and driver assistance [21]. Most mil-

itary applications are less concerned with cost, and are implemented using discrete

components or high performance semiconductors (such as GaAs). With the emer-

gence of automotive radar, more effort is being put into reducing the cost of phased

array systems [26], and one avenue for doing this is by exploring the possibilities of

integrated CMOS implementations.

The increasing prevalence of lower cost MMIC phased-array implementations cou-

pled with the growing demand for high data rate wireless communications has led to

an increased interest in phased-array systems for communications applications. Digi-

tal beam steering implementations are more suited for use in cellular base stations, but

analog implementations have also been reported in recent years [27]. Another possible

use of analog beamsteering in a base station would be to enable adaptive sectorization

28

which would allow network loading to be optimized as compared to the current fixed

sectorization schemes. There has also been interest in the use of phased arrays for

broadband wireless access (BWA) systems, which use wireless links to bridge the last

mile between the subscriber and the service provider [28]. This is attractive for the

speed of deployment and limited infrastructure requirements as compared with wired

solutions. Analog beamforming systems are also suitable for broadband terrestrial

LMCS/LMDS and satellite systems [3]. Another analog beamforming application is

wireless ad-hoc networks [29].

Other research has been done into combining beamforming with other MIMO tech-

niques to maximize spectral efficiency [30]. This idea is incorporated into the soon

to be released IEEE 802.11n standard for wireless LANs, which uses MIMO spatial

multiplexing techniques with optional beamforming. The move of phased arrays into

the consumer electronics domain necessitates low cost and compact systems, which

point to fully integrated CMOS implementations. The work presented in this disser-

ation will focus on a CMOS implementation of phase and amplitude control circuits

for a phased-array transmitter.

29

Chapter 3

PREVIOUSLY PUBLISHED WORK

As discussed in the previous chapter, phase and amplitude errors in the branches

of a phased array have a negative effect on the system’s performance. This chapter

will discuss how these errors are introduced, and different approaches for mitigating

them. The chapter will conclude with a brief introduction to the proposed technique,

which is expanded upon in the following chapter.

3.1 Phased Array Calibration

Phased-array calibration is widely recognized as an important topic, and numerous

papers have been published on research into methods and algorithms for phased array

calibration [17], [18], [19]. There are a number of points in a phased array transmitter

where phase and amplitude errors can be introduced, as pictured in Fig. 3.1. Errors

introduced in the RF phase and amplitude control sections are enumerated in numbers

1 to 3. These can result from improper control voltages being applied to the phase

shifter and VGA (1), as well as from unwanted amplitude variations across the control

range of the phase shifter (2) and unwanted phase variations across the amplitude

range of the VGA (3). Errors introduced in the physical antenna configuration are

enumerated in numbers 4 to 7. These include discontinuities at the interfaces between

lines and connectors (4), differences in the length of transmission lines (5), the air

interface discontinuity (6), and mutual coupling between antennas (7).

Different types of phased array systems use different methods for dealing with

these phase and amplitude errors, as will be discussed in the following sections.

30

Figure 3.1: Points where phase and amplitude errors can be introduced in each branchof a phased array transmitter.

3.1.1 High Precision Applications

In phased array applications that require high precision such as military radar, each

branch of each phased array system is calibrated. These systems are typically pro-

duced in low volumes, so the additional cost associated with the extra calibration is

not a significant drawback. Additionally, these systems often operate at very high

frequencies where small differences in feedline lengths introduce significant phase er-

rors, so individual branch calibration is important. Even after extensive calibration,

errors can still be introduced by changes in system behaviour over operating condi-

tions such as temperature and power supply voltages (for the active RF components).

These errors can be addressed by including the capacity for on-line self calibration to

periodically adjust the operation according to the changes in operating conditions.

3.1.2 Low Cost Applications

In lower cost, high volume applications precision is often not as critical and the

cost associated with calibrating each individual branch of each phased array system

31

is prohibitively high. These systems often operate at lower frequencies, where the

phase errors caused by small length mismatches in antenna feed lines are insignificant

enough that they can be neglected. For these applications calibration is performed

on one unit, and this information is used across a large number of devices, trading

accuracy for cost savings. This method is susceptible to changes in operating con-

ditions (temperature and power supply voltages) as mentioned above, and it is also

susceptible to manufacturing variations, as the system behavior will change across

different fabrication runs.

In this work, we will focus on the errors introduced by the RF phase and amplitude

control chain of the transmitter (sources 1 to 3 in Fig. 3.1). Errors introduced by

the physical antenna configuration are either calibrated out (as described for high

precision applications) or are small enough to be neglected (as described for low cost

applications) and are less susceptible to changes in temperature and power supplies

than the RF chain. The following sections describe different methods for setting the

phase and amplitude in the RF chain and discuss the phase and amplitude errors that

can be introduced in each case.

3.2 Phase and Amplitude Control Techniques

For the case of a phased array transmitter using analog beamforming under con-

sideration here, there are several approaches for setting the phase and amplitude.

These will be reviewed in the following sections, citing examples of previous work.

The techniques used for a receiver are typically interchangeable with those used for a

transmitter, so several of the examples of prior work cited will be for receivers. The

advantages and disadvantages of each approach will be reviewed, and finally a brief

introduction to the approach proposed in this dissertation will be given.

32

3.2.1 Look-up Tables

The most common approach for setting the phase of the signal is through control

voltage to phase shift relationships stored in look-up tables [31]. For this approach,

the control voltage to phase shift behavior of the RF phase shifter is characterized

and stored in a ROM. When the control unit determines the phase shift required,

it consults the look-up table to determine the proper control voltage, and then uses

a D/A converter to apply the analog control voltage to the phase shifter. Many of

the designs that use this approach employ vector modulator phase shifters (to be

described in more detail in Chapter 5) which require more than one control voltage,

increasing the complexity of the look-up tables required [32], [33].

One advantage of this approach is that it allows arbitrary phase resolution, limited

only by the number of entries in the look-up table and the number of bits in the D/A

converter used to set the control voltage. As described in Chapter 2, quantized phase

and amplitude in a phased array lead to degradation of the radiation pattern through

the introduction of quantization lobes (similar to grating lobes). Another advantage

of this approach is that it compensates for non-linearities in the control voltage to

phase relationships of the phase shifter.

The primary disadvantage of this approach is that the phase shifter characteri-

zation that is stored in the look-up tables is performed under one set of operating

conditions, and changes in operating conditions during system operation or variations

between phase shifter instances (due to manufacturing variations) will cause errors

to be introduced. An example of this is shown in Fig. 3.2 where the control voltage

to phase relationships of three different instances of the same phase shifter have been

characterized. It can be seen that there is some variation between the different phase

shifters, which would result in errors being introduced if one of the curves is used to

represent all of the phase shifters. This variation is made more clear in Fig. 3.3 where

it can be seen that the phase error introduced can approach 40. These errors can be

33

Figure 3.2: Comparison of the control voltage to phase relationships of three differentinstances of the same phase shifter.

minimized by including a calibration mode to allow the look-up tables to be updated

[34], but this approach is more suited to phased array receivers than to transmitters.

Another possible source of error is the amplitude control mechanism. The look-

up tables typically only store the control voltage to phase relationships, and changes

in the amplitude (to shape the sidelobes of the radiation pattern) will alter these

relationships, as described in [34]. If a VGA is used to set the amplitude of the signal,

it will introduce some additional phase shift that will vary with the gain. Additionally,

phase shifters often have a varying gain across their phase shift range. These phase

shifter/VGA interactions (2 and 3 in Fig. 3.1) are not accounted for in the look-up

tables, and are additional sources of error.

34

Figure 3.3: Variation of the phase shifters from Fig. 3.2.

3.2.2 Direct Digital Setting

Another approach for setting the phase is to set it directly using digital control. This

approach is most often used with the local oscillator (LO) phase shifting architecture

(2.16(c)). In these designs, the phase shift is achieved by multiplexing between differ-

ent fixed phase shifted versions of the LO signal. These can either be generated from

a higher frequency LO signal which is divided down to yield the different phases [35],

or by standard phase shifting techniques [22].

The primary advantage of this approach is its simplicity, since it eliminates the

need for ROM-based look-up tables and D/A converters to set analog control voltages.

In the case of [35] where there are no explicit phase shifters, the system can also be

more compact since the dividers can be implemented using only transistors, unlike RF

phase shifters which typically require large passive components. Another advantage

is that the variable losses of the phase shifter have less of an impact since the LO

signal can be hard-limited in driving the mixer.

35

The primary disadvantage of the direct digital approach is that the inherent quan-

tization places limits on the phase resolution that can be achieved, leading to unde-

sirable quantization lobes in the radiation pattern. The resolution can be increased

by using more bits, but this leads to very high LO frequencies in the divider scheme

[35] and to large numbers of fixed phase shifters in the other case [22], and in both

cases the distribution of the different LO phases becomes increasing difficult as the

number of bits increases. Another disadvantage is that this method typically pro-

vides no control over the amplitude of the signals, or if it does then the varying

phase shift introduced by the VGA as its gain changes introduces errors in the phase

characteristics.

3.3 Proposed Technique

The approach for setting the phase and amplitude proposed in this dissertation seeks

to combine the strengths of the two approaches described above. It provides the

capability for continuous variation of both phase and amplitude, automatically com-

pensates for interactions between the phase shifter and VGA at different phase/gain

settings and varying operating conditions, and obviates the need for look up tables.

It achieves these goals by using feedback loops to generate on the fly control voltages

(can be thought of as a dynamic single entry look-up table) whenever the phase or

amplitude needs to be adjusted. The proposed approach requires additional complex-

ity to implement the feedback loops, but the power and area requirements are small

in comparison to the phase shifter and VGA system components. Further discussion

of the proposed system is provided in the following chapter.

36

Chapter 4

PROPOSED SYSTEM

As described previously, a phased array must have a means of accurately setting

the phase and amplitude of each path in order to predictably steer the beam of radi-

ated (or received) power in the desired direction. This work develops and implements

a feedback system for accurately setting the gain and phase for each antenna path in

a phased-array transmitter. The aim of this work is to provide a means of controlling

the phase and amplitude which can compensate for changes in operating conditions

and manufacturing variations, and compensate for non-idealities in the phase shifter

and VGA characteristics.

The proposed system couples the phase shifter and VGA and allows them to

compensate for phase/amplitude non-idealities in each other, using methods similar

to those used in polar feedback linearization techniques for power amplifiers (PAs)

[36]. A conceptual depiction of the phase/amplitude control system being proposed

is shown in Fig 4.1. The system is composed of two feedback loops, one for the

phase and one for the amplitude. The inputs to each feedback subsystem are the

phase/amplitude at the output, and the desired phase/amplitude. Since the output

is taken after both the phase shifter and the VGA, the phase feedback loop can

correct for phase errors introduced by the VGA and the amplitude feedback loop

can compensate for amplitude errors introduced by the phase shifter. Additionally,

with proper design of the phase and amplitude feedback loops, the proposed system

compensates for changes in operating conditions and provides an attractive alternative

to setting the phase and amplitude using look-up tables.

The first section of this chapter provides a qualitative description of how the pro-

37

Figure 4.1: High level system diagram for phase/amplitude feedback system.

posed system operates, and the reasoning and design considerations used in choosing

the architecture. The second section provides a quantitative analysis of the system

loop dynamics, and describes how they affect the system design. The final section

provides system simulation results that have been obtained from verilogA modeling.

4.1 Qualitative Explanation

A detailed block diagram of the proposed system is shown in Fig. 4.2. This diagram

shows the blocks that are present in each of the phase and amplitude feedback loops.

The system is designed to be used in two different modes of operation. In the transmit

mode, the single pole single throw (SPST) switches are in the off position, and the

feedback loops are disconnected. The single pole double throw (SPDT) switches

are in the right hand position, and the control voltages for the phase shifter and

VGA are supplied by the control logic Digital to Analog Converters (DACs). In this

configuration the feedback loops are not operating, and thus do not consume any

extra power. The upconverted, modulated signal is applied to the input, and the

38

Figure 4.2: System level block diagram.

phase shifter applies the desired phase shift to the RF signal. The VGA applies the

desired gain to the signal, allowing both the phase and amplitude to be controlled.

Since this structure is intended for transmit applications, the VGA in Fig. 4.2

could have been implemented as a power amplifier (PA), and directly controlled the

power of the transmitted signal. However, several recent PA designs intended for

wireless standards requiring large dynamic ranges of transmission have implemented

the PA in two blocks to make it easier to provide the required dynamic range [37],

[38]. The first block is a variable gain power amplifier driver, and the second block

is a power amplifier. We have chosen to design the system in this manner, and in

Fig. 4.2 the VGA is intended to be used as a power amplifier driver. The inputs to

the phase and amplitude feedback loops in the final system should still be taken after

the PA, since it will also introduce non-idealities to the phase and amplitude of the

output signal. The PA in Fig. 4.2 is shown in dotted lines because it will not be

implemented in this work.

The phase shift was implemented at RF (as compared with the other choices shown

39

in Fig. 2.16) for two reasons. First, as mentioned previously, this choice minimizes

duplication in the transmit path since none of the IF circuitry needs to be duplicated

for each antenna path, and thus can lead to area and power consumption improve-

ments. Secondly, it was desired to use the phase shifter and the VGA to compensate

for non-idealities in each other, this is most easily done if they are operating at the

same point in the signal chain.

The concepts being applied in this work are similar to those used in polar feedback

correction for power amplifier linearization [36]. These systems make use of phase and

amplitude feedback loops to improve the linearity of a PA. If the proposed system

was used with a PA that employed polar feedback linearization, much of the phase

and amplitude detection circuitry for the feedback loops could be shared between the

proposed system and the linearization circuitry for the PA.

An ideal phase shifter would have a constant gain (or loss) over it’s entire phase

shift range, and an ideal VGA would have a constant phase shift over its entire

amplitude range. For real components this is not the case, the losses in the phase

shifter vary with the phase shift, and the phase shift introduced by the VGA varies

with the gain. Measurement results from a representative stand-alone phase shifter

indicate that the output amplitude will vary by ∼12 dB over the phase control range,

and simulations for the VGA indicate that the output phase will vary by ∼20 over

the amplitude control range. If a look-up table approach is used to independantly

set the control voltages for the phase shifter and VGA, the errors introduced to the

radiation pattern (in the form of directivity error, beam pointing error, and sidelobe

distortion as described in Chapter 2) will be significant. In this work, the feedback

loops determine the required control voltages for the phase shifter and VGA, to allow

them to compensate for non-idealities in each other. The phase shifter adjusts its

phase shift to compensate for the undesired phase shift introduced by the VGA, and

the VGA adjusts its gain to compensate for undesired losses introduced by the phase

shifter.

40

When it is necessary to adjust the phase and amplitude of the antenna element

(to steer the main beam in another direction), the system is switched to the calibrate

mode. This is done by removing the modulation on the signal applied at the input

so that a single tone is being applied. The SPST switches in Fig. 4.2 are switched

to their on positions, and the SPDT switches are moved from the right to the left,

so that the control voltages for the phase shifter and VGA are being supplied by the

feedback loops.

The feedback for each of the phase and amplitude loops is taken from after both the

phase shifter and the VGA, allowing them to compensate for each other. Considering

first the phase loop, the input tone is compared to the amplified and phase shifted

signal at the output. Both signals are amplified by the buffer/limiters shown in the

diagram to remove any amplitude dependance, and are then applied to the divide by 2

circuits shown in the diagram. The purpose of the divide by 2 circuits is twofold. First,

they allow the pulse generator/charge-pump combination that is used as a variable

phase detector to operate at a lower frequency, relaxing the design constraints on

these blocks. Second, as will be explained subsequently, they allow the full 360 of

phase range to be specified at the phase control input without running into boundary

constraints. Next, the signals from the divide by 2 blocks are applied to the pulse

generator. The output of the pulse generator is shown in Fig. 4.3, it acts as a digital

circuit that sets its output high on the rising edge of one signal and resets its output

low on the rising edge of the second signal. The in1 and in2 signals in Fig. 4.3 are

shown as having a 25% duty cycle because of the preceding divider circuits which act

as pulse swallowers.

The output of the pulse generator is then applied to the charge-pump. For a high

input, the charge-pump block will source a current Iup into the filter block, and for

a low input the charge-pump will sink a current of Idn out of the filter block. The

charge pump currents Iup and Idn are set by the phase control input, and this is how

the desired phase shift is specified during the calibration mode.

41

Figure 4.3: Transient behaviour of pulse generator block.

The negative feedback action of the loop ensures that the control voltage at the

output of the filter block will settle to a steady state value, which means that in the

steady state condition, the charge being removed and added to the control node by the

charge-pump in each cycle must be equal. If Iup and Idn are set equal to each other, we

can see from Fig. 4.3 that the two inputs to the pulse generator must be offset from

each other by 180. Because of the divide by two circuits preceding the pulse generator

inputs, this means that the phase shifter/VGA combination will be applying 360 (or

equivalently, 0) of phase shift. If Iup is increased to 3 times the amplitude of Idn, we

can see from Fig. 4.4 that the inputs to the pulse generator will be at 90 offset from

each other, which means that the phase shifter/VGA combination will be applying

180 of phase shift. By symmetry it is clear that if we reverse the situation and set Idn

to be 3 times that of Iup, the phase shifter/VGA combination will be applying -180.

From this analysis we can see that the inclusion of the divide by two circuit allows us

to cover the entire 360 range of phase shifts with a reduced range of charge-pump

currents, while maintaining the duty cycle of the pulse generator between 25% and

75%.

The filter can be designed in a similar manner to filters used for charge-pump

42

Figure 4.4: Transient signals for Iup = 3 · Idn

phase-locked loops (PLLs), and its design will determine the loop dynamics and set-

tling time.

The amplitude loop operates in a similar manner to the phase loop in that it makes

use of negative feedback to set the VGA control voltage to the value that yields an

output with the desired amplitude. The first component in the amplitude feedback

loop is the peak detector, which determines the amplitude of the output and converts

it to a dc signal. The output of the peak detector and the amplitude control signal

are the inputs to the integrator block. The integrator block is a differential circuit

which integrates the difference between the peak detector output and control input

(which can be positive or negative), and increases or decreases its output accordingly.

This allows the VGA control voltage to settle to the value that will yield an output

with the desired amplitude.

To resume the description of the calibration sequence, after a time period long

enough to permit the phase shifter and VGA control voltages to settle to their steady

43

state values for the desired control inputs, the control circuitry detects the steady

state values of these nodes using the Sense lines in Fig. 4.2, stores the values, and

then outputs them on the Control lines. The SPST switches are then turned off to

disconnect the feedback loops, and the SPDT switches are moved to the right hand

positions to allow the phase shifter and VGA control voltages to be set by the control

circuitry. The feedback loops can then be powered off, the modulated signal can be

resumed at the input, and transmission can continue as normal with the phase and

amplitude that was set during the calibrate phase.

4.2 Quantitative Explanation

This section will provide a quantitative analysis of the proposed system. The analysis

will assume linearized, frequency domain models for each of the blocks shown in Fig.

4.2, and will proceed in a manner similar to that used for the analysis of charge-pump

PLLs [39]. In order to simplify the analysis, the phase and amplitude loops will be

analyzed seperately. In reality they will not operate independantly, as changes within

the amplitude loop as it is settling will affect the settling of the phase loop, and vice

versa. They can be made to operate independantly (to a reasonable approximation)

by designing the loops with significantly different time constants (so that one loop

changes by a negligible amount in the time it takes the other loop to settle). This

is not a desirable option as it increases the overall time for the calibration period,

which should be minimized. Interactions between the phase and amplitude loops will

be covered in more detail in Chapter 5 when the design of the phase loop filter is

discussed.

4.2.1 Phase Loop

The system diagram for the quantitative analysis of the phase loop is shown in Fig.

4.5. For analytical convenience, a fixed 180 phase shift has been inserted after the

divide by 2 circuit for the input signal. The analysis assumes that the system is in

44

Figure 4.5: System diagram for quantitative analysis of phase loop

the locked state.

We first make the assumption that the input phase is constant, and for convenience

we choose φin(t) = 0. We assume that the phase shifter transfer function is as shown

in Fig. 4.6. Since we have assumed that the input phase is zero, the output phase

can be expressed as

φout(t) = KPSVcont(t) (4.1)

where KPS is the phase shifter gain (the slope of the curve in Fig. 4.6) and Vcont(t)

is the control voltage.

Next considering the pulse generator/charge-pump combination, the transient out-

put current waveform for different values of φout is shown in Fig. 4.7. From this figure

we can see that the average current output over one cycle can be expressed as a sum

of the up and down pulses as

Iavg(t) =Iup(t)(π − 0.5φout(t))

2π− Idn(t)(π + 0.5φout(t))

2π(4.2)

where Iup(t) and Idn(t) are the magnitudes of the up and down current pulses, respec-

tively. They have been given time dependance because the output phase is adjusted

45

Figure 4.6: Transfer function for phase shifter model

by changing the amplitude of the current pulses with respect to each other. We can

factor this equation to express it as

Iavg(t) =1

2(Iup(t)− Idn(t))−

φout(t)

4π(Iup(t) + Idn(t)) (4.3)

If we then express the sum and difference of the up and down currents as Isum(t) =

Iup(t) + Idn(t) and Idiff = Iup(t)− Idn(t), we can express the average current as

Iavg(t) =Idiff (t)

2− φout(t)Isum(t)

4π(4.4)

Since we will we working in the frequency domain, to avoid the convolution op-

erator when taking the Laplace transform of (4.4), we will make the simplifying as-

sumption that the sum of the up and down currents is a constant. This means that

Isum(t) = Isum, and when the up and down currents are adjusted to change the phase,

they are adjusted so that they change relative to each other but their sum remains

a constant (if one is increased the other is decreased). We can express the control

voltage as

Vcont(t) = Iavg(t) ∗ h(t) (4.5)

where h(t) is the impulse response of the loop filter. If we then take the Laplace

transform of these equations and substitute (4.4) into (4.5) and the result into (4.1),

46

Figure 4.7: Charge-pump output current for varying output phases

we can express the closed loop transfer function as

φout(s)

Idiff (s)=

2πKPSH(s)

4π +KPSH(s)Isum(4.6)

To analyze the simplest case, we will assume that the filter in Fig. 4.5 is a simple

capacitor, so that H(s) = 1/sC and we can express the closed loop transfer function

as

φout(s)

Idiff (s)=

A

1 + s/p(4.7)

where A = 2π/Isum is the dc gain and p = KPSIsum/4πC is the single pole. We can

see that this is a simple low pass filter with a bandwidth determined by the sum of

the up and down currents, the phase shifter gain, and C, the capacitor in the loop

filter. For this simplified analysis the loop will be unconditionally stable, however, to

confirm the stability it would be necessary to carry out an analysis which takes into

account the continuous time approximation used for the charge pump (similar to that

done by Gardner for charge-pump PLLs [40]). The result of this would be some limit

on the loop bandwidth to guarantee stability. From the analysis for this simple loop

filter choice we can see which variables affect the bandwidth (and thus settling time)

of the loop.

47

Figure 4.8: System diagram for quantitative analysis of the amplitude loop

4.2.2 Amplitude Loop

This section will provide a quantitative analysis of the amplitude loop, assuming it

is operating independantly from the phase loop. The analysis will be carried out in

the frequency domain using Laplace transforms, similar to the phase loop analysis

performed in the previous section. A system diagram of the amplitude loop for the

analysis is shown in Fig. 4.8. The quantity being operated on is the amplitude of

the sinusoidal signal being applied to the VGA, and as such the peak detector is not

necessary (it is assumed to be ideal) and has been omitted from Fig. 4.8.

It is assumed that the input amplitude Ain is constant, and the output amplitude

is altered by adjusting Vamp(t), the amplitude control input to the integrator. The

amplitude at the output of the VGA can be expressed as

Aout(t) = AinKV GAVcont(t) (4.8)

where KV GA is the gain of the VGA. The VGA transfer function model is shown in

Fig. 4.9.

We can express the output of the integrator as

Vcont(t) =1

τ

∫ t

0−Vamp(t)− AinKV GAVcont(t)dt (4.9)

48

Figure 4.9: Transfer function model for the VGA

where τ is the time constant for the integrator. Here we have assumed that the

quantities being integrated are all zero at t = 0 to simplify the Laplace transforms.

Taking the Laplace transform of (4.9) yields

Vcont(s) =1

sτ(Vamp(s)− AinKV GAVcont(s)) (4.10)

We can now take the Laplace transform of (4.8), sub in (4.10), and rearrange to

find the closed loop transfer function as

Aout(s)

Vamp(s)=

1

1 + s/p(4.11)

where p is the single pole at p = KV GAAin/τ . We can see that the bandwidth of the

system depends on the VGA gain, the amplitude of the input signal, and the time

constant of the integrator. The dc gain of the closed loop system is unity, as we would

expect since the negative feedback and the integrator serve to drive the amplitude at

the output to match amplitude control input Vamp.

4.3 Simulation Results

This section provides sytem level simulation results from verilogA modeling in Ca-

dence. The first two subsections provide simulation results for the phase and ampli-

tude loops operating independantly to verify the analysis that has been carried out

49

Figure 4.10: Schematic for phase loop simulation.

in the preceding sections. The final subsection provides simulation results for the

complete system.

4.3.1 Phase Loop

The schematic for the phase loop containing all of the verilogA blocks is shown in

Fig. 4.10. The loop filter capacitor has a value of 10 pF, and the gain of the phase

shifter is set at KPD = 2.09 rad/V. The bias currents for the charge pump are intially

both set at 100 µA, and then at t = 1µs one is increased to 110 µA while the other

is decreased to 90 µA.

The transient response of the control voltage is shown in Fig. 4.11. It can be seen

that it follows the familiar exponential form characteristic of a one-pole system. To

verify that the analysis and the simulation match, we can calculate the time constant

50

Figure 4.11: Transient waveform for the control voltage, with a step in the charge-pump current applied at t = 1 µs.

for the pole as

τp =4πC

IsumKPS

= 300 nS (4.12)

After one time constant, the control voltage should have reached 63.2% of its final

value. The control voltage starts at 900 mV and moves to 600 mV, so after one time

constant it should be at 900 − (300 · 0.63) = 710 mV, and this is confirmed by the

markers in Fig. 4.11.

4.3.2 Amplitude Loop

The top level schematic for the amplitude loop containing the verilogA blocks is shown

in Fig. 4.12. The input is a sinusoidal source with Ain = 100 mV. A peak detector

has been included with an exponential decay. The time constant for the decay of the

peak detector was set small enough so that it did not influence the ideal peak detector

assumption in the analysis of the previous section. The gain of the VGA is set to

51

Figure 4.12: Schematic for amplitude loop simulation.

KV GA = 11.11, and the time constant of the integrator is set to τint = 400 ns.

The transient response of the control voltage is shown in Fig. 4.13. It can be seen

that it follows the familiar exponental form characteristic of a one-pole system. To

verify that the analysis and the simulation match, the time constant of the loop can

be calculated as

τp =τint

KV GAAin(4.13)

After one time constant, the control voltage should have reached 63.2 % of its final

value. The control voltage starts at 910 mV and moves to 610 mV, so after one time

constant it should be at 910 − 300 × 0.63 = 720 mV, and this is confirmed by the

markers in Fig. 4.13.

4.3.3 Complete System

This section provides simulation results for the complete system. The schematic for

the complete system is shown in Fig. 4.14. The verilogA components and loop param-

52

Figure 4.13: Transient waveform for the amplitude loop control voltage, with a stepin the amplitude control voltage applied at t = 1 µs.

eters are the same as from the seperate loop simulations described in the preceding

sections, with the exception of the phase shifter and VGA blocks. These blocks have

been modified to include the non-ideal amplitude changes introduced by the phase

shifter, and the non-ideal phase shifts introduced by the VGA. These values were

chosen to be representative of transistor level simulations of the phase shifter and

VGA. The phase shifter gain was modeled as changing from -10 dB to 4 dB over the

phase shift range, and the VGA phase shift was modelled as changing from 0 to 22

over the amplitude range. Each non-ideality was modelled as having a linear relation-

ship with the control voltage, but more accurate relationships could be introduced

for more accurate modelling (at the cost of longer simulation times).

The transient waveforms of the two control voltages are shown in Fig. 4.15 where

the phase shifter control voltage is the thick line. From the plot it can be seen the

control voltages initially stabilize to their steady state values. At t = 2 µs (marker A

on the plot) the amplitude control input is adjusted to change the amplitude of the

53

Figure 4.14: Schematic for complete system simulation.

54

Figure 4.15: Transient waveforms of the control voltages for the complete systemsimulation.

output signal, and the VGA control voltage changes sharply to adjust for the new

amplitude. As the VGA changes its gain, its non-ideal phase shift also changes, and

a small change in the phase shifter control voltage can be seen, which compensates

for the VGA phase shift. At t = 4 µs (marker B on the plot) the phase control input

is adjusted to change the phase of the output signal, and the phase shifter control

voltage changes sharply. As the phase shifter changes, the gain (or loss) of the phase

shifter changes, and the VGA control voltage changes to compensate for the change

in the phase shifter loss and maintain a constant amplitude at the output.

Simulations were also run with both the phase and amplitude control inputs chang-

ing at the same time. The transient waveforms of the control voltages for this case

are plotted in Fig. 4.16. Both control inputs were changed at t = 3 µs, and it can

be seen that both the phase and amplitude control voltages settle quickly without

adverse effects from the feedback loops interacting with each other. The following

two chapters will give detailed descriptions of the implementations of the components

55

Figure 4.16: Transient plot of control voltages for phase and amplitude controls chang-ing simultaneously

in the phase and amplitude loops.

56

Chapter 5

PHASE LOOP DESIGN

This chapter will cover the design of each of the components in the phase feedback

loop. The phase shifter is covered in the greatest detail, as its operation is most crucial

for the performance of the overall system. The general design strategy for each of

the blocks is to keep the topologies as simple as possible to minimize power and area

consumption of the system.

5.1 Phase Shifter

5.1.1 Requirements

There are a number of general requirements for a phase shifter to be used in a multiple

antenna beam steering system. The phase shifter should be compact and consume

minimal power (if an active topology is chosen), since the number of phase shifters

scales in proportion to the number of antennas in the system. Smaller phase shifters

allow more antennas to be incorporated into the system, and reduced power con-

sumption extends the battery life in portable applications. The phase shifter should

also have a low noise figure (NF) and minimal loss. In this work the phase shifter

will be used in conjunction with a VGA, so the gain of the VGA can compensate for

the loss of the phase shifter and this requirement is relaxed to some degree. Another

requirement is that the phase shift should be approximately constant over the signal

bandwidth, to minimize distortion effects which lead to increases in the bit error rate

(BER) in the case of communications applications. In most architectures it is impor-

tant for the phase shifter to have constant gain across the phase shift range, however

in this work the VGA will compensate for changes in the gain of the phase shifter.

57

Finally, the phase shifter must provide at least 180 of phase shift with high resolu-

tion. It would be preferable to have 360 of phase shift, but if only 180 is available

then the full range can still be covered through switching a fully differential signal.

The switches required in this situation will introduce additional losses to the signal,

so this is less desirable than having a full 360 of phase shift. Phase shift ranges of

less than 180 and limited phase resolution both limit the effectiveness of the beam

steering.

With these requirements in mind, we will discuss different phase shifter topolo-

gies and select the one that comes the closest to meeting the requirements for this

application. The most well known architectures are switched high-pass/low-pass

(HP/LP) filters [41],[42], reflective-type phase shifters [43],[44],[45],[46],[47], all-pass

filters [48],[49],[50], and vector modulators [51],[52]. For high phase resolution, switched

HP/LP phase shifters require large amounts of area, and are not suitable for low cost

designs [51]. For this reason, they will not be considered further here.

5.1.2 Vector Modulators

Vector modulator phase shifters work by weighting and combining several signal paths

with fixed phase shifts in order to get the desired phase shift at the output. The

incoming signal is split into three paths, each with a fixed 120o phase shift relative

to the next signal path. Weighting is performed by a variable gain amplifier for each

path, and weights are chosen to obtain the desired total phase shift at the output

when the signal paths are recombined. This operation can be thought of in terms

of a vector addition between the different signal paths, as shown in Fig. 5.1. The

fixed phase offsets are typically generated by high-pass and low-pass passive networks.

Vector modulators are capable of phase shift ranges of 360, can provide gain, and

are well suited for monolithic microwave integrated circuit (MMIC) integration [51].

The disadvantage of vector modulators is that they require multiple control voltages

to regulate the phase shift. Each control voltage requires a seperate digital to analog

58

Figure 5.1: Illustration of the vector addition performed by a vector modulator phaseshifter.

converter (DAC) to interface between the digital control circuitry and the vector

modulator, which adds to the complexity and power consumption of the design.

For the phase control architecture being proposed here, the phase shifter archi-

tecture is limited to one control voltage, since the control voltage is derived from a

feedback loop with only one output. A vector modulator architecture requiring only

one control voltage has been proposed [52], but this architecture is limited to 120o of

phase shift, which also excludes it from consideration for our purposes.

5.1.3 All-pass Phase Shifters

All-pass phase shifters are a class of active phase shifter which have the advantage of

requiring only one control voltage. An all-pass network has the characteristic of having

a constant amplitude response over frequency (the source of the all-pass designation),

and a phase response which varies with frequency. The transfer function of general

second-order all-pass network can be expressed as

H(s) =s2 − ω0

Qs+ ω2

0

s2 + ω0

Qs+ ω2

0

(5.1)

The phase characteristics of this network can be expressed as

φ(ω) = −2 · tan−1

(ω0ω

Q(ω20 − ω2)

)(5.2)

59

Figure 5.2: Phase variation of all-pass phase shifter with frequency.

The phase characteristics with changing frequency are plotted in Fig. 5.2. By

changing the value of ω0, the curve plotted in Fig. 5.2 is shifted to the right or

left, and the phase shift at the frequency of interest is altered. The value of ω0

is usually changed using a varactor or active inductor. All-pass phase shifters are

usually active, and can provide gain in the signal path. This advantage is offset to

some extent by their high power consumption, 93 mW and 60 mW for the designs

reported in [48] and [49], respectively. They are also usually implemented in expensive

III-V semiconductors, with exceptions such as the SiGe design reported in [50].

Another drawback of the all-pass phase shifter is the variation in phase shift with

frequency. The variation of phase shift (as seen in Fig. 5.2) is determined by the

variable Q in (5.1). For varactors with limited tuning range, higher values of Q are

necessary to achieve the required phase shift over the varactor tuning range. This

leads to a higher variation in phase shift over the bandwidth of the signal, which

in turn will lead to distortion and increased bit error rates (BER). An advantage of

the all-pass architecture is that it provides a constant amplitude response over the

phase shift range, however, for this work that is not a requirement since the VGA will

60

Figure 5.3: Distributed phase shifter implementations: (a) varactor loaded transmis-sion line, (b) lumped element implementation.

compensate for amplitude variations in the phase shifter output.

5.1.4 Distributed Phase Shifters

Another phase shifter architecture which requires only one control voltage is the

distributed phase shifter, which is typically implemented as a varactor loaded trans-

mission line. Two possible implementations are shown in Fig. 5.3. At higher frequen-

cies, coplanar waveguides (CPW) are periodically loaded with varactors (Fig. 5.3(a))

which allow the phase velocity of the line to be altered to achieve different phase shifts

[53]. This architecture has the advantage of a constant phase shift over a very wide

bandwidth. At lower frequencies, the transmission lines can be replaced with lumped

element equivalents [54], as shown in Fig. 5.3(b). This implementation has a reduced

bandwidth as compared with the previous case.

The disadvantage of these designs is that they typically require a large area, due

to the large number of sections required to achieve 360 of phase shift (16 sections in

[54]). The number of sections required can be reduced, but this increases the losses.

61

Distributed phase shifters are usually implemented as passive circuits, and for GaAs

implementations the losses can be as low as 4 dB. However, for a low cost CMOS

implementation the loss per section is much higher due to the conductive substrate

of CMOS technology. This has been addressed in [55] by adding active circuitry to

amplify the signal before and after the lumped element transmission line. This greatly

mitigates the loss, however, the drawback is a high power consumption of 170 mW.

5.1.5 Reflective-Type Phase Shifters

A fourth phase shifter architecture is the reflective-type phase shifter. A reflective-

type phase shifter (RTPS) consists of a hybrid 90 coupler combined with two reflec-

tive loads. The operation of an RTPS is illustrated in Fig. 5.4. The incoming signal

is split evenly into two parts, with one part of the signal experiencing a 90 phase

shift relative to the other. Each part of the signal is then reflected by a load with a

different input impedance than the coupler, introducing an additional phase shift (φ).

This phase shift is equal to the phase of the reflection coefficient, which is expressed

as

r =ZL − Z0

ZL + Z0

(5.3)

The reflected signals are then split and phase shifted again by the coupler, so

that the signal components emerging from the input are 180 out of phase and cancel

each other out. The signals emerging from the output port are in phase and combine

constructively, with a total phase shift of 90 + φ. The phase shift is varied by

incorporating a varactor into the reflective load, allowing the input impedance to be

changed, thereby changing the phase shift.

Many previously reported RTPS implemenations have shown favorable results,

with areas as small as 0.5 mm2, losses as low as 4.9 dB, and phase shift ranges of

over 360. While none of the designs achieved all of these performance measures

simultaneously, it indicates that the RTPS is a promising architecture, and through

62

Figure 5.4: Operation of a reflective-type phase-shifter.

appropriate tradeoffs it should be possible to realize an implementation which per-

forms adequately for the proposed work. Most of the previously reported work has

been implemented in GaAs [44],[46],[45],[43]. To minimize the cost of the phase shifter

it is desirable to implement it in a CMOS process. This presents a number of design

challenges, the foremost being the increased losses due to the conductive substrate

and the lower quality passives. In [47] a technique was presented for reducing the

losses in a CMOS RTPS by introducing active elements to compensate for losses in

the inductors. This design reported worst case losses of -11 dB, which is approaching

the losses of some of the GaAs designs. The total phase shift for this design was lim-

ited to 110, so more work is needed, but the architecture shows promise for CMOS

implementations.

5.1.6 Reflective-Type Phase Shifter Analysis

A reflective-type phase shifter (RTPS) consists of a hybrid 90 coupler combined with

two reflective loads. The operation of an RTPS was illustrated in Fig. 5.4.

63

Hybrid 90 Coupler

The hybrid 90 coupler is a microwave circuit that is typically implemented using

microstrip lines. It can also be implemented using lumped element equivalents, as

shown in Fig. 5.5. The component values are calculated as follows:

C1 =1

ω0Z0

(5.4)

L1 =Z0

ω0

√2

(5.5)

C2 =1

ω20L1

− C1 (5.6)

where Z0 is the input impedance and ω0 is the center frequency. Our design was

done for a center frequency of ω0 = 2.0 GHz, which yielded values of C1 = 1.77 pF,

C2 = 323 pF, and L1 = 2.25 nH (after adjustments to compensate for parasitics). The

simulated transmission magnitudes and phases for the coupler (including parasitics)

are shown in Fig. 5.6. Simulations were also run to determine the sensitivity of

the coupler performance to variations in component values. It was found that a

10% change in the value of C1 or L1 resulted in a difference of 1.5 dB between the

magnitudes of the two paths, with a negligible effect on the phase. Altering the value

of C2 by 10% had a negligible effect, and it was found that removing the four C2

completely only shifted the crossover frequency (the frequency where the incoming

signal is evenly split) by 2.5%. The crossover frequency could then be restored to

the desired value by reducing the size of the C1 capacitors, resulting in an increase in

loss of only 0.09 dB as compared to the coupler with the C2 capacitors present, and

the same relative phase shifts. This is likely because the calculated value for the C2

capacitor is small compared to C1, and the inductor has enough parasitic capacitance

to ground to adequately perform the function of this capacitor. In designs where the

omission of the C2 capacitors will significantly reduce layout and wiring overhead, it

may be a good choice to omit them, since the impact on perfomance is very small.

64

Figure 5.5: Lumped element hybrid 90o coupler.

Figure 5.6: Simulated S31 and S41 of the lumped element coupler (including para-sitics).

65

Figure 5.7: Reflective loads: (a) Varactor, (b) Single resonated load (SRL), (c) Trans-formed single resonated load (TSRL), (d) Dual resonated load (DRL)

Reflective Load

The amount of phase shift that can be obtained from an RTPS is determined by the

design of the reflective load. A number of common reflective loads are shown in Fig.

5.7. The simplest is a single varactor (Fig. 5.7(a)). The phase shift of the single

varactor load can be increased by adding a series inductor which resonates with the

varactor at the operating frequency, adding a zero to the impedance function (single

resonant load, Fig. 5.7(b)). The phase shift can be further increased by adding

a parallel capacitance, which adds a pole to the impedance function (transformed

single resonant load, Fig. 5.7(c)). Further increases in phase shift can be obtained by

using two parallel single resonant loads, each resonating and introducing a zero at a

different point in the varactor capacitance range (Fig. 5.7(d)).

The choice of reflective load depends on how much phase shift is required, the

tuning range of available varactors, and the allowable loss. As the complexity of the

reflective load increases, the total phase shift increases, as does the loss. For most

CMOS processes the passive components are relatively low quality, so it is best to

minimize the complexity of the load. For this work we have chosen the transformed

66

single resonated load (TSRL). The analysis presented here assumes that the varactor

has a tuning range of 2, which means that the maximum phase shift attainable with

the TSRL is 360, and practical implementations will have less than this theoretical

limit. As mentioned previously, phase shifts of ≥ 180 are adequate provided that

differential signaling is used, since 360 of phase shift can be obtained by switching

the polarity of the inputs to the phase shifter. The switching network necessary to

obtain a full 360 range will introduce loss, so in a complete implementation the loss

introduced by the switches would have to be compared with the loss introduced by

moving to a more complex reflective load structure.

Ideal Components

This section will analyze the TSRL assuming ideal components, to obtain strategies

for sizing the components. The impedance of the circuit shown in Fig. 5.7(c) can be

expressed as

ZL =1− ω2LCV

jω (CT + CV − ω2LCTCV )(5.7)

From this we can see that the TSRL impedance is purely imaginary (as expected),

and assuming that ω is constant, as CV changes, there are two singularities, one in the

numerator where the TSRL impedance will go to zero, and one in the denominator

where the TSRL impedance will go to infinity. We will designate the values of CV

where these singularities occur as CN and CD, respectively. If we then choose L =

1/ω2CN and CT = CDCN/(CD − CN), we can express (5.7) as

ZL =1− CV /CN

jωCT (1− CV /CD)(5.8)

Since the change in the phase shift is determined by the change in the impedance,

the greatest change in the phase shift will occur when CV is in the range of CD, since

the impedance will transition from a finite value to infinity to negative infinity and

back to a finite value. This is shown in Fig. 5.8 where the phase shift and impedance

are plotted against CV . In this and the following plots we have assumed an operating

67

Figure 5.8: RTPS phase shift superimposed on TSRL impedance over the varactorrange.

frequency of 2 GHz and a tuning range of 2, since this is a good approximation for

what would be available in a CMOS process with standard supply voltages. From

figure 5.8 it can be seen that the phase changes most rapidly around CD, which has

been set to the middle (arithmetic mean) of the tuning range. From this we can

conclude that a good choice for CD is in the middle of the tuning range.

The rate of change of the phase will be determined by the rate of change of the

impedance, and this is set by the proximity of CN to CD, as well as by the magnitude

of CV . We have assumed that CD is chosen at the middle of the tuning range, and CN

is chosen to be less than CD. As CN moves closer to CD, the impedance changes more

quickly in the neighborhood of CD, and thus the slope of the phase shift increases.

This is plotted in Fig. 5.9, where the phase shift is plotted for CN increasing from

CV,min to 1.5CV,min. As CN increases, the slope increases, as does the total phase

shift, approaching the limit of 360 (for a varactor tuning range of 2). The change in

the phase shift range for changing CN is plotted in Fig. 5.10. Increasing the nominal

68

Figure 5.9: Effect of zero location (value of CN) on phase shift characteristics.

value of CV has a similar effect to moving CN closer to CD. From these plots we can

see that the choice of CN is a compromise between the phase shift range and the slope

of the phase shift curve. For higher slopes the phase shift will be more sensitive to

noise on the control voltage of the varactor. In the presense of non-ideal components,

higher slope in the phase shift curve also leads to higher losses.

A previously reported design which implemented an RTPS in CMOS technology

[47] implemented the capacitor CT in Fig. 5.7(c) with a varactor of the same value as

CV . The result of this is that the slope of the phase shift in the neighborhood of CD

is determined solely by the size of the varactor, which means that for a desired slope

at a specified operating frequency, the CV and L values are fixed. By making CT a

fixed capacitor (as we have done in this work), the varactor (and inductor) values are

decoupled from the slope of the phase shift characteristics.

69

Figure 5.10: Phase shift range vs. zero location (value of CN).

Impact of Parasitics

This section will analyze the first-order effects of parasitics on the phase shift charac-

teristics. The two circuits which will be analyzed are shown in Fig. 5.11. The circuit

in (a) includes a series resistance that would result from parastic resistance in the

varactor or inductor, and the circuit in (b) includes a parasitic parallel capacitance

to ground that would be present between wiring/components and the substrate.

Series Resistance

The impedance of the circuit shown in Fig. 5.11(a) can be expressed as

ZL =(1− ω2LCV ) + jωRPCV

jω(CV + CT + ω2LCVCT )− ω2CVCTRP

(5.9)

Comparing (5.9) with (5.7), we can see that the parasitic resistor has created an

additional term in each of the numerator and denominator. As expected, as RP → 0,

the last terms in the numerator and denominator of (5.9) disappear, and it becomes

identical to (5.7). We can also observe that as CV and CT become smaller, the

70

Figure 5.11: TSRL with inclusion of parasitics: (a) Series resistance, (b) Parallelcapacitance

extra terms created by RP will be less significant, and the behavior will more closely

approximate the ideal case.

To see the effect of the parasitic resistance on the phase shift, we can plot the

phase shift for increasing values of RP . This is shown in Fig. 5.12 for CV,min of 1

pF and RP values from 0 to 10 Ω. It can be seen that as RP increases, the slope of

the phase shift in the vicinity of CV = CN increases. For RP > 4.5 Ω the phase shift

characteristics change completely; the phase shift is greatly reduced and is no longer

monotonic.

As expected from (5.9), larger values of CV greatly increase the sensitivity of

the phase shifter to parasitic series resistance. For CV,min = 1 pF the phase shifter

switches to non-monotonic behavior (as shown in Fig. 5.12) at RP = 4.73 Ω, while

for CV,min = 10 pF (and CN chosen to provide similar slope in the phase shift char-

acteristics) the phase shifter switches to non-monotonic behavior at RP = 0.41 Ω.

The additional term in the denominator is also proportional to CT , so we can observe

that the sensitivity to RP will increase as CN moves closer to CD (which increases

the phase shift by steepening the phase shift characteristics in the vicinity of CD).

71

Figure 5.12: The effect of parasitic series resistance on phase shift characteristics.

From this analysis, it is evident that the value of the varactor in the TSRL should be

chosen as small as is practical to minimize sensitivity to parastic resistance.

Parallel Capacitance

The impedance of the circuit shown in Fig. 5.11(b) can be expressed as

ZL =1− ω2L(CP + CV )

jω(CT + CV − ω2L(CTCP + CVCT + CVCP ))(5.10)

If we make the same substitutions that were made in moving from (5.7) to (5.8), we

can express this as

ZL =(

CNCN − CP

) 1− CP +CV

CN

1− CV

CD

(1+

CP CDCN (CN−CP )

1

) (5.11)

From comparing (5.8) to (5.11) we can see that the parastic capacitance has re-

duced the zero from CN to CN − CP , and the pole has been reduced from CD to

CD(

11+CPCD/CN (CN−CP )

). Shifting the zero will reduce the slope of the phase shift

characteristics, and shifting the pole will move the phase shift characteristics to the

72

Figure 5.13: The effect of parasitic parallel capacitance on the phase shift character-istics.

left. If we make the assumption that CP CD, CN , we can see that the zero will be

reduced by CP and the pole will be reduced by CP (CD/CN)2. Since CD > CN , the

pole will move more than the zero, and the phase shift characteristics will steepen in

addition to moving to the left. This can be seen in Fig. 5.13, where CV,min = 1 pF and

CP increases from 0 to 300 fF. As CP increases, the phase shift curve steepens and

shifts to the left. When the varactor is larger, the phase shift will be less susceptible

to the parasitic capactitance, but if an accurate estimate of CP is known, the values

of CN and CD can be adjusted to restore the pole and zero to their desired locations.

Design Strategy

This section will consolidate the findings of the previous sections into a general pro-

cedure which can be followed in the design of an RTPS with a TSRL. To simplify the

design, the initial design should be simulated using ideal components, then simulated

with models that include component parasitics, and finally simulated with extracted

models which include layout parasitics, with adjustments to component values being

73

made at each step as necessary.

1. Size the hybrid 90o coupler using the design equations provided.

2. Choose a value for L which will yield the highest quality factor at the frequency

of interest.

3. Calculate the value of CN to resonate with L at the frequency of interest using

CN = 1/Lω2.

4. As a starting point, choose the varactor size to satisfy CV,min = CN .

5. Choose CD to be in the middle of the varactor tuning range, using CD = CV,min+

0.5(CV,max − CV,min).

6. Calculate the value of CT using CT = CDCN/(CD − CN).

7. Simulate the phase shift characteristics and adjust the slope of the phase shift

curve by adjusting the value of CN and recalculating CT . Increasing CN (moving

it closer to CD) will increase the total phase shift at the expense of making the

phase shift curve steeper in the vicinity of CD.

At this point real component models should be introduced for the varactor, capac-

itor, and inductor. After doing this, the greatest effect on the phase shift characteris-

tics will be due to the parasitic resistances in the non-ideal components. Resimulate

the circuit, and if the phase shift is greatly reduced and non-monotonic it will be

necessary to return to the first step and redo the sizing procedure with a larger value

of L (and thus a smaller CV ) to reduce the sensitivity to the parasitic resistance. The

loss of the RTPS should also be simulated at this point, the loss will be greatest in

the vicinity of CD. If the loss is too large, it can be reduced by moving CN away from

CD and reducing the slope of the phase shift characteristics.

74

Figure 5.14: Schematic of the TSRL of the implemented RTPS.

Finally, extract and simulate the circuit from the layout. The largest effect on the

phase shift characteristics after this step will be due to the parasitic capacitance to

ground. This can be compensated for by adjusting CN and CD and recalculating CT

to restore the pole and zero to their desired locations, and by adjusting the varactor

range if necessary.

RTPS Design

In this section we will report the performance of the RTPS that was designed using

the methods and analysis outlined above. The hybrid 90 coupler is shown in Fig. 5.5

and was designed using (5.4) - (5.6) for ω0 = 2.0 GHz. The schematic of the TSRL

is shown in Fig. 5.14. Capacitors CB1 - CB3 are blocking capacitors to allow proper

biasing of the varactor and the cross-coupled pairs. The NMOS and PMOS cross-

coupled pairs are included to reduce the loss of the RTPS by introducing a negative

resistance that compensates for the losses of the inductor, as described in [47].

The sizing for the different components is given in Table 5.1. The component

sizes were chosen using the design procedure outlined in the previous section, and

then adjusted after simulations to minimize loss and maximize the phase shift range.

75

Component Size

CB1 43.8 pF

CB2 7.0 pF

CB3 42.9 pF

CT 3.08 pF

CV,min 0.73 pF

CV,max 1.62 pF

L 4.5 nH

M1 −M4 4 µm/180 nm

Table 5.1: Sizing of components in the implemented TSRL

Blocking capacitor CB3 was sized considerably smaller than the other blocking ca-

pacitors in order to minimize the parasitic capacitance to ground that is introduced

between the bottom plate and the substrate. The varactor was implemented with a

hyper-abrupt junction varactor (HAV), with a tuning range t = 2.23.

A die photo of the RTPS is shown in Fig. 5.15. The RTPS has been implemented

in a 0.18 µm CMOS process, and occupies an area of 0.75 mm2. The measured and

simulated phase shifts are compared in Fig. 5.16. It can be seen that the measured

phase shift range is 308 for a control voltage from 0 - 1.8 V (the standard power

supply range for this process. The measured results are very similar to the simulated

results, with the exception of a shift with control voltage which is likely due to a

mismodelling of parastic capacitances. The measured loss over the nominal phase

shift range is shown in Fig. 5.17, and it can be seen that the loss varies from -4 dB to

-16.5 dB. The measured noise figure is plotted in Fig. 5.18, and it can be seen that

the noise figure varies from 12 dB to 27 dB.

The performance of the implemented RTPS is summarized in table 5.2, where it

is compared to the performance of previously reported CMOS phase shifters. It can

76

Figure 5.15: Die photo of the implemented RTPS.

Figure 5.16: Measured phase shift range of the implemented RTPS.

77

Figure 5.17: Measured loss of the implemented RTPS.

Figure 5.18: Measured noise figure of the implemented RTPS.

78

Specification [55] [47] This work

Process 0.18 µm 0.18 µm 0.18 µm

Frequency 8 GHz 2.4 GHz 2 GHz

Control voltage -1 to 1 V 0 to 1.8 V 0 to 1.8 V

Phase shift 180o 105o 308o

Max. loss NA -11 dB -16 dB

Max. NF NA 17 dB 27 dB

Area 0.23 mm2 1.08 mm2 0.75 mm2

Power 170 mW 1.8 mW 5.4 mW

Table 5.2: Comparison of this work with previously reported CMOS phase shifters

be seen that the phase shift range is the greatest of reported phase shifters, and the

loss and noise figure are comparable to previously reported work.

5.2 Buffer

The next block to be discussed is the buffer, which appears in the phase feedback

loop before and after the phase shifter/VGA combination (shown in Fig. 4.2). The

purpose of the buffer stage is to remove the amplitude dependancy of the input and

output signals before they are fed into the phase feedback loop, by converting the

sine wave signals to full scale digital waveforms where the information is contained

in the edge crossing locations. The digital output of the buffers is then used to drive

the pulse generator.

The most important requirement for the buffer is that it be able to produce a

digital output signal for a range of sine wave amplitudes at its input. This is necessary

since the buffer at the output of the phase shifter/VGA chain will have a varying

input amplitude depending on what amplitude has been specified at the input to the

amplitude feedback loop. Additionally, the delay introduced by the buffer should

79

Figure 5.19: Schematic of the buffer block.

be minimized for stability considerations, and should not vary across different input

amplitudes, as this will introduce error in the phase of the output signal. The buffer

should also contribute minimal phase noise (jitter), and consume minimal power and

area.

The buffer has been implemented with three different cascaded gain stages, as

shown in Fig. 5.19. Several stages were necessary to provide sufficient gain. Stages

1 and 2 provide the gain, and stage 3 produces the digital output that drives the

divider.

The buffer was designed for operation with input amplitudes ranging from 10 mV

to 100 mV. This range was chosen to allow operation over a 20 dB range of output

amplitudes. The minimum input amplitude of 10 mV determined the number of gain

stages required in the buffer.

80

5.2.1 Stage 1

The common source amplifier of stage 1 was chosen as the first stage since it provides

the most gain, at the cost of higher power consumption and increased area (primarily

due to the blocking capacitors CB required for biasing). It was biased with 150 µA

of current, and with a load resistor R1 of 5 kΩ it provides about 12 dB of gain. The

blocking capacitors were sized at 1.3 pF, which was chosen as a tradeoff between

signal attenuation and area consumption.

5.2.2 Stage 2

The second stage was implemented as a resistor-biased inverter, to allow significant

gain with minimal power and area consumption. To provide sufficient gain for input

amplitudes down to 10 mV it was necessary to use three cascaded instances of stage

2 (not shown in Fig. 5.19). Each stage draws 50 µA of current and provides 8 dB

of gain. The biasing resistor R2 was sized at 28 kΩ. This choice was a tradeoff

between higher gain (for larger resistor values) and faster settling times to the correct

bias point for a change in input amplitude. This settling time is not relevant for the

phase loop design, but is important for the dynamics of the amplitude loop, as will

be discussed in the design of the peak detector in the following chapter.

5.2.3 Stage 3

The final stage is a standard inverter that is used to drive the divider stage. Differ-

ent combinations of stages were simulated (i.e., more instances of stage 1 and fewer

instances of stage 2) to try and minimize the number of stages required while mini-

mizing the variation in delay over the input amplitude range, and it was found that

one instance of stage 1 followed by three instances of stage 2 and one instance of stage

3 was optimal.

The change in the delay introduced by the buffer across the range of input am-

81

Figure 5.20: Delay introduced by the buffer across the input amplitude range.

plitudes is plotted in Fig. 5.20. The delay is plotted in units of degrees so that it

is clear how much phase error will be introduced. It can be seen that, while the

buffer operates properly (outputs a full scale digital signal to drive the divider) for

input amplitudes down to 10 mV, for inputs below 30 mV the change in the buffer

delay introduces significant phase error. Thus, the buffer input amplitude should be

maintained above this level to insure that the phase error introduced by the buffer

remains below a few degrees.

5.3 Divider

As mentioned in the previous chapter, the divider circuits are included to allow the

full 360 of phase to be specified for the duty cycle of the pulse generator output

ranging from 25% to 75%, with a nominal value of 50% (as shown in Fig. 4.3). This

exposes the primary requirement for the divider: since the phase shifter has a limited

phase shift range, the divider must start up in the correct state so that the pulse

82

Figure 5.21: Conventional frequency divider block diagram.

generator has a nominal duty cycle of 50% and can span the range from 25% to 75%.

As will be described, this requirement is met by using multiplexing circuitry to choose

the correct phase of the divider upon start up.

The other requirements for the divider are that it contribute minimal phase noise,

consume minimal power, and be able to operate at 2 GHz (which is not difficult in a

modern CMOS process). The divider block can be partitioned into the divider core

and multiplexing circuitry, each of which is described in the following sections.

5.3.1 Divider Core

Most high speed dividers are fully differential structures that make use of two D flip-

flops connected in a master/slave configuration, as shown in Fig. 5.21 [56]. The D

flip-flops are typically implemented using source-coupled logic (SCL). Since the flip-

flops will not be used in a general digital circuit, design techniques can be used to

optimize them for speed that would pose timing problems in some applications.

The topology chosen for the divider core is a well-known design that was reported

by Razavi in 1997 [57]. The schematic is shown in Fig. 5.22. The divider uses two

identical latches in a master-slave configuration, driven by complementary clocks.

Since the input to the divider in our application is single-ended, the complementary

clock inputs are generated using inverters and transmission gates to approximate an

inverter delay. The differential structure of the divider naturally generates 4 phases of

83

Figure 5.22: Divider core schematic

the output clock (Out0−Out270 in Fig. 5.22), which are the input to the multiplexer

(described in the following section) which selects the proper phase to yield a nominal

50% duty cycle for the pulse generator.

5.3.2 Multiplexer

The schematic for the multiplexer is shown in Fig. 5.23. It is a standard design

using transmission gates, and the transistors are minimum size to minimize RC time

constants and allow high speed operation. Since there are four clock phases to be

multiplexed, three of the 2 input blocks shown in Fig. 5.23 are used together to

realize a 4:1 multiplexer.

In this design the control of the multiplexer is done manually through off-chip

switches, but in a real implementation it would be straightforward to design a start-

84

Figure 5.23: Divider multiplexer schematic

Figure 5.24: Timing diagram for pulse generator.

up circuit which automatically configures the multiplexer into the proper state upon

circuit initialization.

5.4 Pulse Generator

The pulse generator generates pulses to drive the charge-pump, with a duty cycle that

varies according to the phases of the two input signals. The primary requirements for

the pulse generator are that it be insensitive to the duty cycle of the inputs, and have

symmetry for reliable operation at high frequencies. Fig. 5.24 shows the required

input/output waveforms and Fig. 5.25 shows the state diagram that is required for

the pulse generator.

85

Figure 5.25: State diagram for pulse generator.

Figure 5.26: System diagram for pulse generator.

The insensitivity to the duty cycle of the inputs is necessary because the pulse

swallowing divider outputs have a duty cycle of 25%. This requirement points to an

edge triggered implementation, and a simple circuit that meets the requirements of

the state diagram of Fig. 5.25 is shown in Fig. 5.26. For a typical D flip-flop imple-

mentation the clock and reset inputs are not symmetrical, which is a key requirement

for our design. With this in mind, a proposed D flip-flop implementation is shown

in Fig. 5.27. The cross coupled latches hold the internal state, and transistors M1

and M2 set and reset the output. The edge sensitivity is accomplished through the

delayed and inverted input signals arriving at transistors M3 and M4, which disable

the set/reset transistors M1 and M2.

Due to it’s inherently differential operation, this design has the additional advan-

tage of generating differential outputs for use by the charge-pump. Care was taken

in the design of the circuit to size the latch transistors to be small enough so that

the set/reset transistors (M1−M4) could change the state of the circuit without any

86

Figure 5.27: Schematic for pulse generator.

glitches.

5.5 Charge-Pump

The charge-pump is driven by the pulse generator, and is the key component for

setting the phase of the feedback loop. When the pulse generator output is high,

the charge-pump pushes the specified current onto the loop filter node (referred to as

the Up current), and when the pulse generator output is low, the charge-pump pulls

the specified current off of the loop filter node (referred to as the Down current). As

shown in Fig. 4.4, the phase is adjusted by changing the values of the Up and Down

currents relative to each other.

With this in mind, the most important requirement for the charge-pump is that it

be able to generate accurate, programmable, Up and Down currents. Inaccuracies in

the charge-pump current will result in phase errors between the intended and actual

phase, and the resolution with which the Up and Down currents can be specified will

determine the phase resolution of the phased-array element. Additional requirements

for the charge-pump are that it should consume minimal power and area.

A schematic for a standard charge-pump is shown in Fig. 5.28. The current in

the branches is set by the current source and the diode connected transistor MN0.

87

Figure 5.28: Schematic for a standard charge-pump.

It is assumed that the charge-pump is employed in conjunction with an active loop

filter which holds the output node Out at voltage V ref . Operational amplifier 1

incorporates feedback to insure that the Up and Down currents are equal. To illustrate

how this works, if the Up current is higher than the Down current, the voltage on

node A will increase, causing the opamp to increase the voltage on the gates of MP1

and MP3, reducing their gate to source voltages, and reducing the Up current.

The primary weakness of the charge-pump in Fig. 5.28 is the charge-injection from

transistors MP3 and MN3 during switching. When the switch transistor MP6 is in

the off state, current continues to flow through transistor MP3, charging the parastic

capacitances on node B. When MP6 is switched on, this excess charge flows onto

the output node. Since this charge is not related to the duration of time for which

the Up current is switched on, it adds a non-linear component to the charge-pump

output, which is highly undesirable. A parallel situation holds for the Down current

and node C.

The most common modification to ameliorate this problem is to add a second set

of switch transistors so that the current in transistors MP3 and MN3 is steered back

88

Figure 5.29: Schematic for a charge-pump with current steering to reduce chargeinjection.

and forth between two branches, instead of being switched on and off. This topology

is shown in Fig. 5.29, where transistors MP5 and MN5 have been added to form

the second branch. These transistors are driven with the inverse of the output switch

transistors, so that when MP6 is switched off, MP5 is switched on, and the current

from MP3 is steered to this branch instead of accumulating on node B. The voltage

on this dummy output node is set to the same voltage as the output node.

This modification provides a significant improvement over the initial design in Fig.

5.28, but there is still residual charge injection due to mismatches in the switching

times of transistors MP5, MN5 and transistors MP6, MN6. Since the accuracy of

the charge-pump currents translates into phase accuracy in our application, an alter-

native charge-pump topology has been developed which almost completely eliminates

charge injection. The new charge-pump architecure is shown in Fig. 5.30. The central

features are the addition of operational amplifiers 2 and 3, and transistors MP4 and

MN4.

The charge injection problem arises from switching the current from transistors

MP3 and MN3, so in this topology the current from these transistors flows perma-

89

Figure 5.30: Schematic for the new charge-pump with buffers and no switching.

nently through the dummy switches MP4 and MN4, which are always on. In the

previously described topologies, charge accumulation at nodes B and C resulted in a

change in the voltage at those nodes. In this topology, there is no switching taking

place so these nodes are held at steady state values. Operational amplfiers 2 and 3

serve as buffers, and hold nodes D and E at the required voltages. Since all of the

switch transistors have identical sizing, the currents in the output branch will match

those in the dummy branch of MP4 and MN4. Although the switching in the out-

put branch will provide small disturbances at the output node, as long as operational

amplifiers 2 and 3 have sufficient gain and bandwidth, the charge injection will be

negligible.

A comparison of the charge-injection performance of the three topologies is shown

in Fig. 5.31. It can be seen that the current steering topology provides significant

improvement over the standard topology, but the newly proposed topology goes a step

further and completely eliminates charge injection effects, resulting in highly linear

operation.

In designing the circuit shown in Fig. 5.30 there are several important issues to be

aware of. To maintain stable operation, extra care has to be taken in designing the

90

Figure 5.31: Simulated transient current waveforms for the three charge-pump topolo-gies.

feedback loop containing operational amplifier 1 which maintains equality between

the unit Up and Down currents. A standard operational amplifier is usually designed

to have about 60 dB of gain and about 75 of phase margin, but in this feedback loop,

transistors MP1 and MP2 act as an additional cascoded common source amplifier,

adding about 30 dB to the gain of the feedback loop, making it potentially unstable.

With this in mind, operational amplifier 1 should have much less gain than operational

amplifiers 2 and 3 (which can be designed as standard opamps) to maintain stability.

Another consideration is that the charge-pump must provide means of setting the

Up and Down currents. This was accomplished by implementing transistors MP3

and MN3 as switchable arrays of unit transistors. The unit transistors are switched

in and out to allow precise digital control over the Up and Dn currents, which will

be multiples of the unit current set by the current source driving transistor MN0.

In this implementation, 5 bits of digital control were used for each of the Up and

91

Dn currents. If more resolution is required it is straightforward to add more bits to

the charge-pump transistor arrays. Since these arrays are isolated from the switching

nodes by the operational amplifiers 2 and 3, the additional parasitic capacitance does

not cause any problems. In addition to the switchable unit currents, a fixed current

equal to the most significant control bit was added to each of the Up and Dn branches

to avoid boundary conditions with zero current.

One final consideration relates to charge injection onto the output node from the

switches MP6 and MN6. The preceding discussion on charge injection has focused

on charge buildup at nodes D and E which is the dominant source of charge injection,

but injection of the channel charge of the transistors MP6 and MN6 during switching

can also have an effect. To ameliorate this effect, half-sized dummy transistors driven

by the inverse of the input with their drain and sources connected were added to the

output node.

5.6 Loop Filter

A preliminary analysis of the loop dynamics of the phase feedback was given in the

previous chapter, this section will build upon that analysis to account for second

order effects and to enable the design of the loop filter. The primary requirement

for the loopfilter is that it combine with the other loop components to yield the

desired dynamics for the feedback loop. The two most important elements of the

loop dynamics are the stability and the loop bandwidth, which determines how fast

the control voltage will settle to its final value.

Since we are using a charge-pump in our feedback loop, it was mentioned in the

previous chapter that the simplest choice of loopfilter that would provide an integra-

tion is a capacitor. However, from the design of the charge-pump in the previous

section, it is clear that we need an active loop filter which holds the charge-pump

output at a stable voltage. The loopfilter topology is shown in Fig. 5.32. Here Iin is

the charge-pump output current, and Vref is a reference voltage. Assuming an ideal

92

Figure 5.32: Toplogy of the phase loop filter.

opamp, the transfer function can be shown to be

H(s) = − 1

sC(5.12)

where C is the capacitor value. This is the same as for the case of the passive capacitor

loopfilter, with the exception of the sign inversion.

5.6.1 Operational Amplifier

The most important requirement for the operational amplifier used in the loopfilter

is that it be able to drive the output from rail to rail, to allow the full control range

of the phase shifter to be used. It is not necessary to have a rail-to-rail input stage,

as the feedback within the loopfilter will hold both inputs at Vref .

Initial designs were done using a 1.8 V opamp with a class AB rail-to-rail output

stage. However, it was found that the performance of the opamp was not consistent

across the process corners, so a decision was made to use a standard opamp topology

with a higher power supply to allow a 0 − 1.8 V output range. The schematic for the

final opamp is shown in Fig. 5.33. It has a common source differential pair for the

first gain stage, a common source second gain stage, and a source follower buffer for

the third stage to provide a low output impedance. The opamp was designed using

93

Figure 5.33: Schematic for the operational amplifier used in the phase loopfilter.

thick oxide transistors to allow a 3.3 V power supply, and it provides 60 dB of gain.

A Miller compensation network (not shown in Fig. 5.33) is used to provide a phase

margin of 78.

5.6.2 Sizing

The most important decision in the loopfilter design is the sizing of the capacitor,

as this will determine the loop dynamics. This can be done by starting with Eq.

(4.6) from the previous chapter. Two non-idealities that were not taken into account

in this expression are the effect of the biasing network of the phase shifter, and the

effects of the delays introduced by the other components (buffers, dividers, etc.). The

reflective load of the phase shifter was shown in Fig. 5.14. There it was implied that

the control voltage directly sets the voltage at one terminal of the varactor, but in the

actual design it is necessary to include a large blocking resistor between the output

of the loop filter and the varactor terminal. This blocking resistor combined with the

capacitance of the reflective load has a significant impact on the loop dynamics and

must be included in the analysis.

A representation of the load that must be driven by the loopfilter is given in Fig.

94

Figure 5.34: Schematic of the reflective load as it appears to the loopfilter.

5.34. Here Vin is the output of the loopfilter opamp and Vout is the voltage that is

applied to the varactor. The resistors labeled RB are the large blocking resistors and

RC is the coupler input impedance. The capacitors labeled CB are the large blocking

capacitors, and the other components comprise the reflective load. After making a

number of approximations based on the operating frequency and component values, it

can be shown that the transfer function of the network in Fig. 5.34 can be expressed

as

Vout(s)

Vin(s)=

1

1 + sRBCeq(5.13)

where RB = 9 kΩ and Ceq = CB/2 + CV = 7.5 pF.

After incorporating (5.12) and (5.13) into (4.6), we arrive at a final expression for

the closed loop gain of the phase loop:

φout(s)

Idiff (s)=

KPS

CRBCeq

1

s2 + s 1RBCeq

+ KPSIsum

4πCRBCeq

(5.14)

where KPS is the phase shifter gain, C is the loopfilter capacitor, RB and Ceq result

from the phase shifter bias network (as described above), and Isum is the sum of the

Up and Down charge-pump currents.

The denominator is second order, and can be put in the form of the characteristic

equation for a second order system. After doing so, we can express the natural

95

frequency and damping factor as:

ωn =

√KPSIsum

4πCRBCeq(5.15)

ζ =

√πC

RBCeqKPSIsum(5.16)

Using these equations, the design procedure is to set the damping factor (ζ) to 0.707

(for critical damping), and solve for the relation between the configurable parameters,

which are the loop filter capacitor and the charge-pump currents. These can then be

chosen to yield a reasonably sized capacitor. Since we have only one parameter

to adjust in the loopfilter, we cannot specify both the damping factor and natural

frequency, so if it was necessary to set these quantities independantly we would be

forced to move to a higher order loop filter.

The phase shifter gain varies across its control range (as seen in Fig. 5.16), so

to ensure that the system remains stable across the entire operating range the worst

case (for stability) of the maximum phase shifter gain was used (KPS = 8.2 rad/V).

Using this procedure, we arrive at a loop filter capacitor value of 35 pF for nominal

Up and Down currents of 126 µA (Isum = 252 µA). This yields a critically damped

system with a natural frequency of 250 KHz, so the settling time will be on the order

of several µs which is acceptable for our purposes.

Since the absolute value of integrated components is not well controlled, the ca-

pacitor in the loopfilter was implemented as a switchable array, allowing 2 bits of

control over the capacitor value. Additional control over the loop dynamics can be

realized by adjusting the charge-pump unit current, but this method is limited by the

need to maintain stability in the replica bias feedback network of the charge-pump.

One other non-ideality that must be considered is the additional delay introduced

by the buffer, divider, pulse generator, and charge-pump blocks in the feedback loop.

Since added delay reduces the phase margin at the unity gain frequency, it is necessary

to verify that the system is stable in the presence of these additional delays which were

not accounted for in the analysis presented above. Simulations were run to determine

96

the magnitude of these delays, which were incorporated into a Matlab script which

verified that they have a negligible impact on the phase margin at the unity gain

frequency.

The final non-ideality to be considered is the effect of finite gain and output

resistance in the op-amp, since the analysis presented above assumes an ideal opamp.

These effects were incorporated into a Matlab script which confirmed that they have

a negligible effect at the frequencies of interest.

5.6.3 Phase/Amplitude Loop Interaction

The final effect to be considered is the interaction between the phase and amplitude

loops, as this has the potential to degrade the stability of the loops. If the phase

shifter had constant gain across its phase range or if the VGA had constant phase

across its gain range then this issue would not arise, as the loops would not interact

with each other. For a real phase shifter and VGA this condition does not hold, and

part of the motivation for this work was to correct for the errors introduced by this

non-ideal behavior in the phase shifter and VGA.

The effect of the variable gain in the phase shifter and the variable phase shift in

the VGA is to change the effective gains of each of the blocks. As we have seen in the

previous chapter, the phase shifter and VGA gains play a role in determining the loop

dynamics of the system, so changes in these quantities caused by loop interactions

can either make the system more or less stable, depending on the gain and phase

relationships. This section will determine the changes in the phase shifter and VGA

gains introduced by the loop interactions, and the effect on the stability.

The approximate gain and phase relationships versus control voltage for each of

the phase shifter and VGA are shown in Fig. 5.35. It can be seen that the gain

relationship for the phase shifter is non-monotonic. As we will see, the characteristic

on the left part of the curve actually increases the stability of the loop, so we will

only consider the right portion of the curve.

97

Figure 5.35: Approximate gain and phase relationships for the phase shifter and VGA.

98

To examine the effect of the amplitude loop on the stability of the phase loop,

first consider the solid arrow on the phase relation plot for the phase shifter (the top

plot in Fig. 5.35). For an increase in phase, as shown by the solid arrow, there is

an increase in the control voltage, and from the next plot down we can see that this

corresponds to an increase in the amplitude of the signal at the output (assuming

we are operating on the right part of the phase shifter gain curve). This increase in

amplitude will then be detected by the amplitude loop, which will then decrease its

control voltage to restore the amplitude to its original value (solid arrow in the third

plot). From the solid arrow in the fourth plot showing the VGA phase relation, we

can see that this decrease in control voltage will lead to an increase in the output

phase, in addition to the increase in phase brought about by the original change in

the phase loop. So, we can see that the effect of the amplitude loop is to increase the

effective gain of the phase shifter, which makes the system less stable. The increase

in effective phase shifter gain can be calculated as

∆KPS =KG,PS ·KP,V GA

KV GA

=1.7 · 0.9

7.3= 0.22 (5.17)

where KG,PS is the amplitude gain of the phase shifter and KP,V GA is the phase gain

of the VGA. By following this procedure while assuming operation on the left portion

of the phase shifter amplitude plot, we can see that the effect of the amplitude loop

is to reduce the effect phase shifter gain, making the phase loop more stable.

A similar procedure can be followed to determine the effect of the phase loop on

the amplitude loop stability, by examining the dashed arrows in the order denoted

by their accompanying numbers. From the VGA amplitude plot we can see that

an increase in amplitude corresponds to an increase in control voltage, which from

the VGA phase plot, results in a decrease in phase. From the phase shifter phase

relation, we can see that the phase shifter will increase it’s control voltage to increase

it’s phase to compensate for the decrease of the VGA, and from the phase shifter

amplitude plot it is seen that this corresponds to an increase in amplitude, which

99

adds to the original intended increase in amplitude of the VGA. In a similar manner

to above, this increases the effective VGA gain, making the amplitude loop less stable.

The increase in effective VGA gain can be calculated as

∆KV GA =KP,V GA ·KG,PS

KPS

=0.9 · 1.7

1= 1.6 (5.18)

It should be noted that in this expression the minimum phase shifter gain of 1 rad/s

was employed, as this represents the worst case for this situation.

The calculated increases in the phase shifter and VGA effective gains can now

be factored into the design equations to recalculate the loop filter component values.

Since the above analysis assumes that the phase shifter and VGA operate in a linear

manner, there may be further loop interactions resulting from the nonlinear nature of

the real components that have been ignored. With this in mind, some further margin

of error is designed into the gains for the loop filter calculations, in addition to the

flexibility provided by the programmable nature of the loop filter components.

100

Chapter 6

AMPLITUDE LOOP DESIGN

This chapter will cover the design of the components in the amplitude feedback

loop. The most detail is provided for the variable gain amplifier (VGA), as its oper-

ation is most crucial for the performance of the overall system. The general design

strategy for each of the blocks is to keep the designs as simple as possible to minimize

power and area consumption of the system.

6.1 Variable Gain Amplifier

As mentioned in Chapter 4, a decision was made to implement the variable gain

for the system in a variable gain amplifier (VGA) that will drive a power amplifier

(PA), rather than implementing the variable gain in the power amplifier itself. This

decision was made both to avoid the linearity problems that can be encountered when

adjusting the bias of the power amplifier, and to limit the scope of the project. The

approach of achieving variable gain by dividing the power amplifier into a VGA and a

PA has been used in several PA implementations that require a large dynamic range

[37], [38]. The complexity of the amplifier block was limited by using a narrowband

design, making the design of a VGA with sufficient gain an easier proposition.

6.1.1 Requirements

The main requirement for the VGA is imposed by the losses of the phase shifter

in conjunction with the necessary amplitude range for providing sufficient sidelobe

reduction [58]. The phase shifter measurements indicate that the loss varies over a

range of 12 dB. Since it is desirable to implement the VGA in a single stage, it has

101

Figure 6.1: Four VGA topologies: (a) variable feedback, (b) variable bias, (c) currentsteering, and (d) simple cascode.

been decided to aim for 20 dB of gain with a control range of over 30 dB. This will

allow the VGA to fully compensate for the loss variation of the phase shifter while

providing 20 dB of gain control for setting the gain of each branch to reduce the

sidelobes of the array pattern.

It is also desirable to minimize the power consumption and noise figure of the VGA

since it will be a part of the transmit path, along with the phase shifter. Another

requirement and motivation for limiting the VGA to a single stage design is the need

to have a single control voltage, since the feedback loop can only generate one control

voltage.

6.1.2 Topology

There are a number of different techniques for varying the gain of an amplifier, four

of which are shown in Fig. 6.1. The first is the variable feedback approach, where

the gain is varied by altering the feedback resistance. The variable resistor can be

implemented as an FET device. While this approach has the potential for a high IP3,

its disadvantages are possible stability problems and a limited gain control range [59].

102

The second approach, shown in Fig. 6.1(b), is to incorporate a variable bias

network to alter the gain by varying the bias current of the drive transistor (to change

its transconductance). This approach has the advantage of a low noise figure, but

the disadvantage that the linearity of the amplifier is strongly dependant on the bias

current.

The third approach is to use differential cascode transistors to steer current to

and from the load. This approach has been reported frequently in the literature, with

implementations in both Si-BJT and GaAs HBT [37], [38], [60]. The advantage of

this approach is that it provides a large gain control range, and the disadvantage is

that it tends to suffer more from noise than the other approaches [59].

The fourth approach can be thought of as a variant of the third, where the ad-

ditional transistor for steering current away from the load has been omitted and the

gain is controlled by reducing the current in both the cascode transistor M2 and the

main drive transistor M1. This method has also been reported in the literature, and

it is attractive for its simplicity [61].

The architecture employed in this work is a combination of the third and fourth

approaches. These topologies are attractive for their large gain control ranges, and

an optimization technique is used to minimize the noise figure, which is their primary

disadvantage. If we assume that the current steering transistors M2 and M3 in Fig.

6.1(c) are sized with equal W/L ratios and we consider the topology shown in Fig.

6.1(d) to be a variant of this where the current steering transistor has been sized with

W3/L3 = 0, we can see that it is possible to size the current steering transistorM3 with

a continuum of sizes between 0 and W2/L2. In the following Section we will analyze

the general case, and use a combination of simulations and analytical techniques to

show that optimal noise performance can be achieved by sizing 0 ≤ W3/L3 ≤ W2/L2.

It will be shown that this minimizes the combined noise contributions of all of the

transistors in the amplifier.

103

Figure 6.2: Transistor model used for noise figure analysis.

6.1.3 Noise Analysis

To obtain a sizing strategy for minimizing the noise figure of the topology shown in

Fig. 6.1(c) we will use combination of simulations and analytical techniques. First

we will derive an expression for the noise figure of the VGA. For conciseness, we will

only consider the noise contributions of the transistors (which are the dominant noise

sources in the circuit). The transistor model used is shown in Fig. 6.2. The drain

current noise is expressed as [36]

i2nd = 4kTγgd0∆f (6.1)

where γ is a constant that is approximately equal to 4/3 in short channel devices, and

gd0 is the drain source conductance at VDS = 0. In this analysis we will neglect gate

noise and 1/f noise, since simulations have shown that thermal noise in the channel

dominates at the 2 GHz operating frequency of interest.

Considering the transistor noise sources individually and then superimposing their

effect at the output, we can derive the noise figure for the VGA shown in Fig. 6.1(c)

as

NF = 1 +(i2nd,1 + i2nd,3)

i2ns

s2C2gs,1

g2m,1

+i2nd,2i2ns

s2C2gs,1[gds,1 + s(Cgs,2 + Cgs,3) + gm,3]

2

g2m,1g

2m,2

(6.2)

where i2ns is the noise contribution of the source and we have omitted terms that were

shown to be negligible by simulation results. It can be seen that the second term is

104

due to noise contributions from M1 and M3 and the third term is due to noise from

M2. We can obtain the noise figure for the VGA topology shown in Fig. 6.1(d) by

omitting all of the terms in (6.2) due to M3. We then obtain

NF = 1 +i2nd,1i2ns

s2C2gs,1

g2m,1

+i2nd,2i2ns

s2C2gs,1[gds,1 + sCgs,2]

2

g2m,1g

2m,2

(6.3)

First we will look at the noise performance of the simple cascode topology com-

pared with that of the current steering topology. We will focus on their noise per-

formance when the gain is reduced from its maxiumum value, as this is the region

where the VGA is most susceptible to noise. As the gain is reduced, the signal power

at the output is reduced while most of the noise sources remain constant, resulting

in a degraded signal to noise ratio (SNR). From (6.1), the drain noise contributions

depend on gd0, which in turn depends on the VGS bias condition. Simulations have

shown that VGS stays approximately constant for the topologies as the gain is varied,

so in this analysis we will focus on the coefficients of the drain noise contributions,

and assume that the i2nd terms remain relatively constant as the gain is varied.

Intuition might indicate that the simple cascode topology will have superior noise

performance since by adding M3 for the current steering topology we have added an

additional noise source, but to arrive at a final result we must examine the coefficients

of the noise contributions as the gain is varied. The two architectures operate in a

similar manner when the gain is high, since negligible current flows through M3 in

the current steering topology. As the gain is reduced, in the current mirror topology

the current through M1 stays approximately constant while in the simple cascode

topology the current in M1 is greatly reduced.

For the current steering topology, simulations reveal that the noise from M2 dom-

inates at low gain settings. In the simple cascode topology, as the current in M1 is

reduced to very low levels, gm,1 decreases significantly causing the the second term

in (6.3) to increase sharply so that the noise from M1 begins to dominate, increasing

the overall noise figure. The result of this is that as the gain decreases, the noise

105

figure of the simple cascode topology degrades considerably faster than that of the

current steering topology. As a quantitative example, in preliminary simulations it

was found that 20 dB down from the maximum gain the noise figure for the simple

cascode topology was 10.1 dB, while for an identically sized current steering VGA

with W3/L3 = W2/L2 it was 8.4 dB.

As mentioned previously, simulations have shown that at lower gain settings the

third term in (6.2) (the contribution from M2) dominates the noise figure of the

current steering topology. Since this term depends partially on the characteristics of

M3, we can infer that it is possible to reduce this term by changing the size of M3 so

that it is not necessarily equal in size to M2. By reducing the size of M3, both gm,3

and Cgs,3 are reduced. Since both of these quantities appear in the numerator of the

M2 drain noise coefficient, by scaling down M3 we can minimize the effect of the M2

drain noise. Since this is the dominant noise source at reduced gain settings for this

topology, this will reduce the overall noise figure.

As we scale downM3 we also reduce the current that it can carry, thus reducing the

current through M1 for low gain settings. If M3 is scaled down too much, the current

in M1 will be reduced enough so that it becomes the dominant noise source at low

gain settings, as in the cascode topology. From this discussion, it is evident that an

optimum size for M3 can be found to minimize the noise, with W3/L3 being between

W3/L3 = 0 (simple cascode topology) andW3/L3 = W2/L2 (standard current steering

topology). As a quantitative example, preliminary simulations showed that a VGA

with W3/L3 = 0.2W2/L2 had a noise figure of 8.0 dB, as compared with 8.4 dB for

the same VGA with W3/L3 = W2/L2.

While the analytical noise figure equations are useful for gaining intuition into

which parameters we should adjust to minimize the noise figure, they neglect higher

order effects that are important for accurately determining the overall noise figure.

For this reason, the final optimization must be carried out using simulations. In the

following section the VGA is designed making use of the principles discussed in this

106

Figure 6.3: Schematic of variable gain amplifier.

section.

6.1.4 Design and Sizing

The schematic of the implemented VGA is shown in Fig. 6.3. It has been designed to

operate at 2.0 GHz, and has been implemented in 0.18 µm CMOS technology. The

CB capacitors are large blocking capacitors to allow proper biasing, and RB is a large

resistor included to allow biasing of M1. Transistor M3 is sized to be 1/5 the size of

M2, a ratio that was arrived at through simulator optimization. LL and CL form a

resonant load, and transistors M4 and M5 act as a buffer to minimize loading effects

on the VGA output. Due to the gain of the first stage, the noise contribution of these

transistors is negligible.

Improvements in the gain could have been obtained by including matching net-

works at the input and output, however this would have required additional inductors.

One of the goals for this VGA was to create a compact implementation, so matching

networks were not included. A summary of the sizing for the VGA components is

107

Component Size

CB 10 pF

RB 12 KΩ

LL 3.2 nH

CL 1.5 pF

M1 250 µm

M2 100 µm

M3 20 µm

M4 100 µm

M5 60 µm

Table 6.1: Sizing of components in the implemented VGA

given in Table 6.1, where all transistors are sized with the minimum length of 180

nm. The layout for the standalone VGA is shown in Fig. 6.4. It can be seen that the

area of the VGA is dominated by the size of the inductor. The rectangles around the

perimeter are pads to allow wafer probing to measure the VGA in isolation.

6.1.5 Simulation Results

It had been planned to fabricate the VGA in a standalone configuration prior to its

inclusion in the final system (as was done for the phase shifter), but the targeted

fabrication run was cancelled so the post-layout extracted simulations are presented

here. These simulations include the effects of parastic resistances and capacitances,

and are expected to be close to the measured results. The power supply voltage

for this process is 1.8 V, and the bias currents were 2 mA and 3 mA for M1 and

M4 respectively, leading to a total power consumption of 8 mW (not including bias

circuitry). The simulated S21 characteristics over the control voltage range are shown

108

Figure 6.4: Layout of the variable gain amplifier.

in Fig. 6.5. It can be seen that the maximum gain is 20.6 dB. As noted above, this

could be improved by adding matching networks at the input and output of the VGA,

at the cost of increased area due to the additional inductors. The bandwidth of the

VGA is 340 MHz, centered around 2 GHz.

The simulated noise figure is plotted in Fig. 6.6. Both the actual noise figure

and the minimum achievable noise figure are plotted, and it is evident that further

improvements in the noise figure are possible with the addition of matching networks.

The sharp increase in the noise figure as the gain is reduced is evident in Fig. 6.6. At

maximum gain, the actual noise figure is 1.47 dB, and the minimum achievable noise

figure is 0.76 dB. When the gain is reduced to 20 dB below the maximum, the actual

noise figure is 8.8 dB, and the minimum achievable noise figure is 5.1 dB.

The simulated IP3 for the bias conditions cited above was -14 dBm. This is quite

low, and if necessary it could be improved by increasing the bias current levels.

109

Figure 6.5: Simulated S21 for the variable gain amplifier.

Figure 6.6: Simulated noise figure for the variable gain amplifier.

110

6.2 Peak Detector

The primary requirements for the peak detector are that it be capable of operating

at 2 GHz, and that it have sufficient dynamic range. The dynamic range must be at

least 10 dB, as that is the chosen amplitude range for the output to provide sufficient

sidelobe reduction. As with the other components, it is preferable that the peak

detector have low complexity and power consumption.

The simplest peak detector consists of a diode for rectification followed by a low-

pass RC filter for averaging. Monolithic peak detectors are typically implemented

using schottky diodes or bipolar transistors [62]. A number of low-power peak de-

tectors with large dynamic ranges have been reported, but they are limited to low

frequency operation [63]. Recently, several CMOS implementations of power detec-

tors have been reported [64], but many of them have high complexity and power

consumption, and are not appropriate for this work.

In this work we employ a CMOS implementation of the bipolar RF peak detector

introduced in [62], similar to one that was described in [65]. The peak detector in its

simplest form is shown in Fig. 6.7. The actual circuit employed has some additional

stages, but the core circuitry in Fig. 6.7 is sufficient for the analysis and design. The

following sections will present an analysis of the DC behavior of the peak detector

(using a similar approach as in [62]) as well as the transient behavior, which will be

used in the design of the system loop dynamics.

6.2.1 DC Analysis

In the circuit shown in Fig. 6.7, the transistor acts as a non-linear rectifying element.

The capacitor acts as a hold capacitor, and its value is determined (in conjunction

with the current source) by the allowable droop on the output voltage over a half

period of the input frequency. When the transistor is off, the current I1 comes from

111

Figure 6.7: Schematic for peak detector design and analysis.

the capacitor, and can be expressed as

I1 = C1dVoutdt

(6.4)

The output voltage droop can then be expressed as

∆Vout = ∆tI1C1

(6.5)

where ∆t is one half of the period of the input frequency. As will be shown in the

section on transient analysis, the choice of the capacitor also influences the settling

behavior of the peak detector.

To determine the relationship between the amplitude of the input signal and the

output voltage of the peak detector, we assume that the input voltage is a sinusoidal

signal specified as

Vin = VB + V1 sinωt (6.6)

where VB is the bias voltage, V1 is the amplitude of interest, and ω is the angular

frequency of the input signal. If we assume that the droop is small enough to be

neglected, then Vout can be assumed to be constant. The average current through

transistor M1 must be equal to the current through the current source, so if we

assume that the transistor is biased so that it remains in the saturation region for the

112

majority of the time, then we can write

I1 =µnCox

2

W

L(Vin − Vout − VT )2 (6.7)

Now if we represent the constant as β = µnCox

2WL

and sub in (6.6), we get

I1 = β (VB + V1 sinωt− Vout − VT )2 (6.8)

Combining the three constant voltages as VC = VB−Vout−VT , expanding the squared

quantity and using a trignometric identity yields

I1 = β

(V 2C + 2VCV1 sinωt+

V 21

2(1− cos 2ωt)

)(6.9)

Since we are interested in the average current, we can set the two sinusoidal terms

on the right hand side of (6.9) to zero, leaving

I1 = β

(V 2C +

V 21

2

)(6.10)

Rearranging to express in terms of VC yields

VC =

√√√√I1β− V 2

1

2(6.11)

We can now sub in the expression for VC to solve for the output voltage, giving

Vout = VB − VT −

√√√√I1β− V 2

1

2(6.12)

It can be seen that (6.12) only provides a valid result when

V 21

2<I1β

(6.13)

If the input amplitude increases beyond this threshold then on the positive swings

the current through M1 is so large that to maintain an average current of I1, on the

negative swings the transistor would have to pull current off of the capacitor. This

is clearly not possible, so the result would be that C1 would charge up so that M1 is

113

no longer in the saturation region, invalidating the assumptions used to derive (6.12).

This case could also be analyzed, but for predictable operation according to (6.12)

the range of input voltages should be determined and then the W/L ratio for M1 can

be adjusted so that (6.13) is always satisfied.

To more clearly observe the relation between Vin and Vout in (6.12), we can expand

the last term using its MacLaurin series. If we truncate the series after the first three

terms, we get

Vout = VB − VT +

√I1β

(V 2

1

β

4I1− 1

)(6.14)

From this we can see that Vout has a square law relationship with the input amplitude

V1.

6.2.2 Transient Analysis

The peak detector is a non-linear device, thus Laplace analysis does not strictly apply.

However, since we would like to include the effects of the peak detector in the Laplace

domain analysis of the overall amplitude loop behavior, it is desirable to develop a

linear approximation for the transient behavior of the peak detector.

To aid in the analysis of the peak detector, Matlab code has been written to plot

the output voltage for changes in the input amplitude. As in the previous section, it

is assumed that when the transistor is on, it is in the saturation region. A plot of the

output voltage (as produced by the Matlab code) for a positive and negative voltage

step is shown in Fig. 6.8. It can be seen that each of these transitions has settling

behavior which can be approximated by an exponential settling, so in this section we

will model the peak detector transient behavior as a one-pole system.

Step Up Behavior

The conceptual behavior of the peak detector is simplified if the input amplitude is

equated to an equivalent DC input voltage Veff . Then when the input amplitude

114

Figure 6.8: Transient behavior of peak detector output voltage from Matlab simula-tion.

increases, Veff increases so that the output voltage increases so that the VGS for the

transistor settles to the proper value (where IDS of the transistor is equal to I1, as

must be the case in the steady state). The relation between the input amplitude and

the newly defined Veff can be determined from the DC analysis performed in the

previous section.

With this representation, we can express the current flowing onto the hold capac-

itor C1 as the difference between the current of M1 and the current source I1:

IC = β(Veff − Vout)2 − I1 (6.15)

If we assume that the current source I1 is small relative to the current flowing through

the transistor, and use the relation for the current on a capacitor, we get

dVoutdt

=β

C1

(Veff − Vout)2 ∝ β

C1

(6.16)

From this we see that the slope is proportional to β/C1.

115

For an exponential settling characteristic with time constant τ , the slope is pro-

portional to 1/τ . From this, we can conclude that for the exponential approximation,

τ ∝ C1

β(6.17)

Thus, for the transient behavior for an positive step in the input amplitude, we can

use curve fitting to determine the time constant τ for the exponential approximation,

and model the peak detector using a one pole transfer function

Vout(s)

Vin(s)=

KPD

1 + sτ(6.18)

where the peak detector gainKPD incorporates the DC relationship between the input

and output voltages which was derived in the previous section. From the analysis

above, we can see that if it is necessary to adjust the time constant of the peak

detector, we can do so by changing the the W/L of M1 and/or the size of C1.

Step Down Behavior

From Fig. 6.8 it is evident that the peak detector behaves in a different manner for

a step down in the input amplitude than it does for a step up. For a step down,

the effective voltage Veff described in the previous section is reduced so that the

transistor M1 is initially turned off. During this period, Vout declines linearly, with a

slope of I1/C1. After Vout is reduced enough so that the transistor starts to turn on,

the behavior can then be approximated with an exponential.

The initial slope of the exponential is equal to the slope of the linear region, so

in a similar manner as for the step up behavior, we can relate the exponential time

constant as

τ ∝ C1

I1(6.19)

Again we see that the settling time can be reduced by reducing C1, and in this case

it can also be reduced by increasing I1. From this expression and (6.5) we can see

that achieving a faster settling time is in direct conflict with minimizing the droop

voltage, so these two factors must be traded off.

116

6.2.3 Design Procedure

The peak detector can now be designed with the following procedure. First, the

allowable droop is used to determine the relative values of C1 and I1 using (6.5). The

transistor W/L ratio is then chosen to ensure that (6.13) is satisfied. Next, the peak

detector is simulated for positive and negative voltage steps, curve fitting is performed

to determine the exponential time constants for each case, and the worst case (slowest)

time constant is assumed for the design of the loop dynamics. If necessary, the time

constants can be altered using the relations given in (6.17) and (6.19). Finally, using

the largest allowable step in the input amplitude, the maximum delay due to the

linear portion of the curve for a step down in input amplitude is determined. This

can then be inserted as a fixed delay in the loop dynamics to ensure that the system

remains stable in this situation.

The final peak detector design contains additional buffering, level-shifting, and

biasing circuitry not shown in Fig. 6.7. A transient simulation of the peak detector

output voltage for a changing input voltage is shown in Fig. 6.9, which confirms the

behavior shown in the Matlab simulations.

6.3 Loop Filter

As discussed in Chapter 4, the loop filter for the amplitude loop was chosen as an

integrator to force the difference between the desired output amplitude and the actual

output amplitude (as detected by the peak detector) to zero. There are a number

of different choices for implementing an integrator, including a simple operational

amplifier design making use of a resistor and a capacitor to set the time constant, and

the well-known gm−C integrator. A comprehensive summary of integrator structures

and their characteristics can be found in [66]. The main requirement for the integrator

is that the output voltage be able to cover the required range for the VGA control

voltage, which from Fig. 6.5 is from 0.8 V to 1.8 V.

117

Figure 6.9: Transient behavior of peak detector output voltage from Cadence simu-lation.

The topology selected for the loop filter is the RC opamp integrator, as shown in

Fig. 6.10, where Vdes is the desired output amplitude and Vpd is the output of the

peak detector. This topology was selected for its low complexity and ease of design.

Figure 6.10: Schematic for the amplitude loop filter.

118

6.3.1 Operational Amplifier

Unlike the operational amplifier for the phase loop filter, the operational amplifier for

the amplitude loop filter does not require a rail to rail output stage. This enabled the

use of a standard opamp topology as shown in Fig. 5.33, with the standard power

supply voltage of 1.8 V. In contrast to the opamp shown in Fig. 5.33, an NMOS

differential input stage was used, to permit the use of a PMOS source follower output

stage which can drive the output voltage to the positive power supply rail. The opamp

was designed for 60 dB of gain and a phase margin of 75.

6.3.2 Sizing

The most important decision in the loopfilter design is the sizing of the resistor-

capacitor combination, as this will determine the time constant of the integrator,

which will in turn determine the loop dynamics. This can be done by starting with

Eq. (4.11) from Chapter 4. In deriving this equation it was assumed that the peak

detector behaved in an ideal manner. As seen in the previous section, a real peak

detector introduces additional delay in the feedback loop, and the behavior can be

approximated with the one pole behavior.

After incorporating (6.18) into (4.6), we arrive at the final expression for the closed

loop gain of the amplitude loop:

Aout(s)

Vdes(s)=AinKV GA

RCτ

((1 + sRC)(1 + sτ)

s2 + s 1τ

+ AinKV GAKBUFKPD

τRC

)(6.20)

where Aout is the output amplitude, Vdes is the desired output amplitude, Ain is the

input amplitude, KV GA, KBUF , and KPD are the gains of the VGA, buffer, and peak

detector, τ is the time constant of the peak detector, and R and C are the loopfilter

components. The closed loop gain has been expressed with the assumption that the

desired voltage input to the feedback loop has been adjusted while the input amplitude

stays constant. It can also be expressed with the assumption that the desired voltage

input to the feedback loop stays constant and the input amplitude changes (as would

119

occur for a change in the phase shifter losses as the phase loop adjusts the phase

shifter control voltage), which yields the same expression multiplied by a different

constant.

The denominator is second order, and can be put in the form of the characteristic

equation for a second order system. After doing so, we can express the natural

frequency and damping factor as:

ωn =

√KV GAKBUFKPD

τRC(6.21)

ζ =1

2

√RC

KV GAKBUFKPDτ(6.22)

Using these equations, the design procedure is to set the damping factor (ζ) to 0.707

(for critical damping), and solve for the relation between the configurable parameters,

which are the loop filter components. These can then be chosen to yield a reasonably

sized capacitor. Since we have only one parameter to adjust in the loopfilter (the

resistor and capacitor are inversely proportional to one another), we cannot specify

both the damping factor and natural frequency, so if it was necessary to set these

quantities independantly we would be forced to move to a higher order loop filter. To

confirm the values obtained using this procedure, Matlab code was written to check

the phase margin and bandwidth of the complete loop including the two zeros in

(6.20).

As in the previous chapter, the adjusted VGA gain was employed in the design

equations to account for the interactions with the phase loop due to the variable losses

of the phase shifter. The other gain values were determined through simulation, and

after the design calculations, we arrive at a loop filter capacitor value of 5 pF for

a resistor value of 24 kΩ. This yields a critically damped system with a natural

frequency of 4.7 MHz, so the settling time will be on the order of several hundreds

of ns which is acceptable for our purposes. The natural frequency of the amplitude

loop is over an order of magnitude greater then that of the phase loop, which will

minimize interaction between the two loops.

120

Since the absolute value of integrated components is not well controlled, the ca-

pacitor in the loopfilter was implemented as a switchable array, allowing 2 bits of

control over the capacitor value. Additional control over the loop dynamics of the

final system can be realized by adjusting τ of the peak detector by changing the bias

current. The final non-ideality to be considered is the effect of finite gain and output

resistance in the opamp, since the analysis presented above assumes an ideal opamp.

These effects were incorporated into a Matlab script which confirmed that they have

a negligible effect at the frequencies of interest.

121

Chapter 7

EXPERIMENTAL RESULTS

This chapter presents the the measured results from the fabricated system. The

system was fabricated in the IBM 7RF process. This is a CMOS mixed-mode process,

with 6 metal layers and a minimum feature size of 0.18 µm. In addition to the standard

CMOS devices, the process also offers hyper-abrupt junction varactors (which were

used in the phase shifter), characterized inductor models, and high K metal-insulator-

metal capacitors. The power supply voltage is 1.8 V for the core, with thick oxide

devices available with a power supply voltage of 3.3 V.

The first section of this chapter describes the design of the additional circuitry

that was included on the die for test and measurement purposes, such as configuration

registers and buffers. The next section describes the test setup, including the printed

circuit board design and measurement equipment used. The final section presents

and discusses the measured results that were obtained for the complete system.

7.1 Test and Measurement Circuits

This section presents the additional circuitry that was included with the system to

allow its functionality to be fully verified.

7.1.1 Configuration Registers

There are a number of digital control signals needed to configure the system, such

as the digital control for the charge-pump currents and the configuration bits for the

loopfilter components. Using I/O pins for each of these bits would require too many

pins, so a configuration register was designed to allow these bits to be loaded onto

122

Figure 7.1: Schematic for the configuration register, showing 3 of the 20 bits.

the chip in a serial manner. The schematic for the configuration register is shown in

Fig. 7.1.

The register consists of two chains of D flip flops. The Data in and Clock inputs

are used to load the top chain of registers in a serial manner, with the data being

clocked in on the rising edge of the Clock signal. Once the top chain of registers has

been loaded, the Load signal is clocked to load the data into the bottom chain of

registers, where it is available on the Q outputs of the flip flops to drive the digital

control bits. The Reset signal is an active low signal which clears all of the registers.

To allow the system to start in a default state after a reset of the configuration register,

some of the outputs are taken from the Q outputs and the others are taken from the

Q outputs, depending on whether the bit should be 0 or 1 in the default setting.

7.1.2 Control Voltage Observe/Drive Modules

As described in Chapter 4, the phase shifter and VGA control voltages driven by

either the feedback loops or by an external source, depending on whether the system

is in the calibrate or transmit mode. In a final implementation this would all take

123

Figure 7.2: Schematic of the Observe/Drive module used for the control voltages.

place on the die with analog-to-digital and digital-to-analog converters, but in the

prototype implemented here it is necessary to have a means of observing the control

voltage and driving it from an external source.

To enable this, Observe/Drive modules were implemented for each of the two

control voltages. The schematic for the Observe/Drive module is shown in Figure

7.2. It has two modes of operation, determined by the observe and drive control

bits. When both control bits are low, the transmission gates are open and the control

voltages are disconnected from the external circuitry. When observe is driven high,

the voltage follower opamp buffers the control voltage so it can be observed through

off-chip measurement equipment. When drive is driven high, the upper transmission

gate allows the control voltage to be driven by an external source (as would be done

after the feedback loop has been shut off and the system is in the transmit mode).

The additionaly nMOS transistor is included to ensure that the input to the opamp

is not floating when the observe control bit is low.

124

7.2 Test Configuration

This section describes the printed circuit board that was used to test the system, as

well as the configurations of measurement equipment that were used in the different

test phases.

7.2.1 Printed Circuit Board Design

A four-layer printed circuit board (PCB) was designed to enable the testing of the

system. The final system has 44 I/O pins, which eliminated wafer probing as a

test option. The die was bonded directly to the PCB using Chip-On-Board (COB)

bonding to minimize parasitics due to longer than necessary bondwires (as would

have been the case if the die had been packaged). The AppCad software package was

used to design 50 Ω transmission lines for routing the RF input and output signals

on the PCB, and SMA connectors were used to interface between the PCB and the

measurement equipment.

A photograph of the final assembled PCB is shown in Figure 7.3. The main fea-

tures of the PCB are power connections with decoupling capacitors, potentiometers

for setting bias voltages and currents, buffering circuitry for interfacing the configu-

ration registers to the parallel port of a PC, and switches for configuring the divider

multiplexors in the phase feedback loop.

7.2.2 Measurement Equipment

The test board was powered using two HPXXXX adjustable power supplies, and bias

currents were supplied and adjusted using on board potentiometers. The configura-

tion registers were loaded using the parallel port on a laptop running custom C++

code, and control voltages were measured and recorded using an HPXXXX multime-

ter. Phase and gain measurements were made using an Agilent XXXX vector network

analyzer (VNA). For the open loop measurements the VNA was calibrated and op-

125

Figure 7.3: Photograph of the assembled printed circuit board.

126

erated in the frequency domain, and for the closed loop measurements the VNA was

operated in the time domain in Continuous Wave mode. The gain measurements were

also confirmed using an Agilent XXXX signal generator to drive the RF input and

an Agilent XXXX spectrum analyzer to observe the output power levels.

7.3 Measurement Results

A die photo of the fabricated chip is shown in Figure 7.4. In the meaurement results

to follow, the system was operated with a 1.9 GHz input signal at -8.0 dBm. Sim-

ulations were performed for a 2.0 GHz signal, however, the phase characteristics of

the fabricated phase shifter at this frequency were significantly steeper which reduced

the stability of the phase feedback loop. Reducing the operating frequency to 1.9

GHz reduced the total phase control range from 310 to 275, but also improved the

stability of the phase feedback loop and reduced the losses of the system.

7.3.1 Phase Characteristics

As mentioned in Chapter 5, the charge pump has been designed with the Up and

Dn branches each having a fixed current of 16 · ICP (where ICP is the unit current

set by the charge pump bias current) as well as a digitally switchable current which

varies from 0 to 31 · ICP . As described in Chapter 4, the phase loop dynamics remain

constant if the sum of the Up and Dn currents remains constant. This provides 5 bits

of control over the phase, by varying (Up, Dn) from (0, 31) · ICP to (31, 0) · ICP , with

a constant sum of Isum = 63 · ICP (taking into account the fixed components of the

charge pump currents in addition to the variable components). From (4.4), by setting

the average current over a cycle (Iavg) to zero the output phase can be expressed as

in radians as

φout =IdiffIsum

· 2π (7.1)

127

Figure 7.4: Die photograph of the complete system.

128

Since Idiff varies by 2 · ICP with each step, the theoretical phase change for each step

can be calculated as 11.4. This allows the entire 360 of phase to be covered with

the 5 control bits if an ideal phase shifter is available. With a real phase shifter, the

system control range may be limited by either the range of the phase shifter or by

the middle of the system control range (which corresponds to a phase shift of 180)

not coinciding with the middle of the phase shifter range.

The measured results for the phase characteristics of the system are shown in Fig.

7.5. Due to the limitations described above, only 240 of the range is accessible. Since

the middle of the phase shifter control range is not aligned with the 180 center of the

charge pump control range, the low end of the charge pump control range (Up, Dn)

= (31, 0) coincided with a control voltage of 0.12 V, meaning that the full range of

the phase shifter (275) could not be exploited. The 1.8 V limit on the phase shifter

control voltage was reached for (Up, Dn) = (8, 23), yielding 24 steps of phase control

over the 240 range.

The average phase step across the phase control range is 10.3, which is less than

the ideal value of 11.4 calculated above. From (7.1) it can be seen that this is due

to the fixed components of the charge pump currents (present in the denominator)

being too large relative to the variable components (present in the numerator and the

denominator). The layout of the charge pump current elements is shown in Fig. 7.6,

with the arrays of Up and Dn unit current elements denoted. The transistors were not

arranged in a completely symmetrical array, which has resulted in differences between

the unit currents in the fixed and variable current components. A revised version of

the charge pump should have the unit current elements arranged in a completely

regular array, with elements for the different control bits interdigitated with each

other and dummy devices surrounding the entire array.

A line with the same average slope as the measured data has been plotted alongside

the data points (labeled as Ideal), and it can be seen that the data points exhibit

some deviation from the constant phase step that is expected. This is more clearly

129

Figure 7.5: Measured phase of S21 plotted against steps in the digital control bits.

illustrated in Fig. 7.7 where the phase difference between successive settings of the

data points is plotted along with the average phase difference over all of the data

points. This deviation can also be attributed to the charge pump layout causing (or

rather, failing to prevent) differences between the unit currents among the different

control bits.

To confirm this, the system phase shift was measured with individual pairs of Up

and Dn control bits activated, i.e. (Up, Dn) = (0, 0), (1, 1), (2, 2), (4, 4), etc. Ideally,

the phase shift for each case should be 180 since the currents should be equal, or if

the Up and Dn currents are different but the unit currents for each are the same, then

all of the bits should display a phase offset from the ideal case of 180 proportional to

the bit value. As seen in Fig. 7.8 this is not the case, indicating that the unit currents

of the charge pump elements vary between the different control bits within the Up and

Dn currents. The supposition that this is due to the charge pump layout is confirmed

130

Figure 7.6: Layout of the charge pump unit current elements, with the Up and Dnarrays denoted.

131

Figure 7.7: Measured phase steps of S21 for each increment in the digital control bits.

by the fact that the pattern of deviations from the ideal step size was repeated for the

different chips that were tested (as will be seen in Section 7.3.5) rather than varying

randomly. This indicates that the linearity of the phase characteristics in Fig. 7.5

could be greatly improved through the use of more rigorous layout techniques for the

charge pump.

One other point worth mentioning is that while the system has only been demon-

strated with the equivalent of 5 bits of resolution over a control range of 360 (assum-

ing that a phase shifter with sufficient range were used), if the condition of having

constant loop dynamics across the phase control range were relaxed much greater

phase resolution could be achieved through using different combinations of Up and

Dn currents. For each of the 25 settings of the Up current, 25 unique settings for the

Dn current are possible, meaning that close to 210 unique phase settings can be real-

ized (the actual number is less than 210 since combinations such as (1,1) and (4,4) yield

132

Figure 7.8: Measured phase of S21 for individual control bits (0 corresponds to onlythe fixed current elements being active).

133

the same phase offset). These are not linearly distributed through the phase range

(they are concentrated around the nominal phase shift of 180), but it still opens the

door for increased phase resolution without any change in the circuitry (other than

insuring that the phase loop remains stable across the range of Isum values).

7.3.2 Amplitude Regulation for Changing Phase

As mentioned in Chapter 4, one of the advantages of the proposed system is that it

allows the VGA to compensate for the variable losses of the phase shifter across its

phase control range. The measured gain of the system is plotted in Fig. 7.9, where

the magnitude of S21 has been plotted for the open loop case (with the VGA control

voltage fixed at the maximum of 1.8 V) and the closed loop case (with the amplitude

feedback loop setting the VGA control voltage). For the closed loop case, the desired

amplitude input has been set lower than the minimum amplitude for the open loop

case to ensure that the amplitude requirement can be met across the entire phase

control range. If some variation in the magnitude of S21 can be tolerated, then the

desired amplitude input can be increased to provide a higher average gain over the

phase control range in exchange for some variation in output amplitude. From Fig.

7.9 it can be seen that the system gain for the open loop case varies by 12.1 dB (which

is what would be expected based on the measurement results for the standalone phase

shifter described in Chapter 5), while the feedback of the closed loop case reduces the

gain variation to just 0.4 dB.

The settling behavior of the phase shifter and VGA control voltages is shown in

Fig. 7.10 for a change in the phase control inputs from (Up, Dn) = (31, 0) to (12,

19), which corresponds to a phase step of 204. The third waveform in the plot is the

Load signal for the configuration register, which applies the new digital control values

to the charge pump. It can be seen that the phase shifter control voltage settles in

about 6 µs, whereas the amplitude control loop is faster with the VGA control voltage

settling in about 3 µs. The loop filters were designed to err on the conservative side

134

Figure 7.9: Measured magnitude of S21 over the phase control range.

of stability, so it is likely that the settling speed could be increased significantly from

the behavior shown here. This plot also confirms the supposition made in Chapter 5

that there will be limited interaction between the settling of the phase and amplitude

loops.

7.3.3 Phase Regulation for Changing Amplitude

Another benefit of the proposed system is that it provides the ability to vary the

amplitude of the output signal (which can be useful for reducing the sidelobes of the

array pattern, as described in Chapter 3) while maintaining a constant phase shift.

The measured phase shift of the system as the gain is varied is plotted in Fig. 7.11.

For the open loop case the phase shifter control voltage is held steady at 0.75 V (which

yields the same phase shift as the closed loop case at the maximum gain setting), and

for the closed loop case the phase feedback loop adjusts the phase shifter control

135

Figure 7.10: Time domain waveforms of VGA and phase shifter control voltages fora step in the digital phase control bits.

136

Figure 7.11: Phase of S21 across the amplitude control range.

voltage to compensate for the changing phase shift introduced by the VGA as its gain

is reduced. From the plot it can be seen that the feedback loop reduces the variation

in phase from 32.1 (for the open loop case) to 7.4. The phase regulation across

the amplitude range is not as effective as the amplitude regulation across the phase

range, and this is because of the buffer block used in the phase loop (and described

in Chapter 5). As the amplitude of the input signal to the buffer changes, the buffer

undergoes variation in the phase shift that it introduces, and this variation appears

as phase error at the output. However, the phase variation introduced by the buffer

is small enough that the phase loop still provides considerable improvement over the

open loop case.

The settling behavior of the phase shifter and VGA control voltages is shown in

Fig. 7.12 for a step change in the desired amplitude input to the amplitude feedback

loop. The step change was achieved by using an analog multiplexor to switch abruptly

137

Figure 7.12: Time domain waveforms of VGA and phase shifter control voltages fora step in the desired amplitude input.

between two input voltages, with the switching initiated by the changing of a bit in

the configuration register. The third waveform in the plot is the Load signal for the

configuration registers. It can be seen that the settling behavior is similar to that for

a phase step in Fig. 7.10, only now the changes in control voltages are being initiated

by a change in the VGA control voltage, with the phase loop altering the phase shifter

control voltage to compensate for the altered phase shift of the VGA at its new gain

setting.

7.3.4 Phase Regulation Across Power Supply Voltages

As mentioned in Chapter 4, one of the intentions in implementing the proposed system

was to provide stable operation across variations in process, voltage, and temperature.

The measured phase characteristics for changing power supply voltages are plotted in

138

Figure 7.13: Phase characteristics for changing supply voltage with open loop opera-tion.

Figs. 7.13 and 7.14. The power supply voltage was varied from 1.7 V to 1.9 V, and

Fig. 7.13 plots the system behavior for fixed phase shifter and VGA control voltages

while Fig. 7.14 plots the system behavior when the phase shifter and VGA control

voltages are set by the feedback loops. It can be seen that the closed loop case does

a better job of regulating the phase to a constant value.

To better illustrate this point, the maximum deviation between the three power

supply voltages at each phase control point is plotted in Fig. 7.15. The maximum

deviation for the open loop case is 28.1, which is reduced to 7.3 in the closed loop

case. The standard deviation in phase for the open loop case is 9.4, which is reduced

to just 1.8 when the feedback loops are active in the closed loop case.

The variation in phase with changing power supply voltage is primarily due to the

active loss reduction circuitry included in the phase shifter architecture (described

139

Figure 7.14: Phase characteristics for changing supply voltage with closed loop oper-ation.

140

Figure 7.15: Maximum deviation in phase characteristics across the control range forchanging power supply voltage.

141

in Chapter 5). A passive phase shifter implementation would have greatly reduced

phase variation for a changing power supply voltage, but completely active phase

shifter implementations (such as All-Pass phase shifters) would have greater phase

variation than shown here, and the use of the feedback loops in the system would

have an even greater benefit. The deviation in the phase for the closed loop case that

is shown in Fig. 7.15 is due to the changing power supply voltage altering the delays

in the feedback loop and introducing phase error at the output.

7.3.5 Phase Regulation Across Test Boards

The measured phase characteristics for three different test chips are plotted in Figs.

7.16 and 7.17. Fig. 7.13 plots the system behavior for fixed phase shifter and VGA

control voltages while Fig. 7.17 plots the system behavior when the phase shifter and

VGA control voltages are set by the feedback loops. It can be seen that the closed

loop case does a better job of regulating the phase to a constant value, and both cases

have less variation than what was seen in the previous section for a changing power

supply voltage.

To better illustrate this point, the maximum deviation between the three test

chips at each phase control point is plotted in Fig. 7.18. The maximum deviation for

the open loop case is 15.4, and this is reduced to 4.4 in the closed loop case. The

standard deviation in phase for the open loop case is 5.0, and this is reduced to just

1.2 when the feedback loops are active in the closed loop case.

The variation in phase characteristics between different test chips is due to process

variations across the wafer. Since all of the test chips were fabricated on the same

processing run, there is fairly minimal variation between the different test chips, as

shown in Fig. 7.16. For a system that was manufactured in higher volume across

different fabricaton runs there would be a more significant variation in the phase

characteristics between different chips, and the benefits of the feedback loops would

be more pronounced.

142

Figure 7.16: Phase characteristics for three different test chips with open loop oper-ation.

143

Figure 7.17: Phase characteristics for three different test chips with closed loop op-eration.

144

Figure 7.18: Maximum deviation in phase characteristics across the control range forthree different test chips.

145

7.3.6 Noise

Since this work is intended for use in a transmitter the noise performance is of less

significance than if it were to be used in a receiver. Due to the position of the

phase shifter (with its comparatively high losses) preceding the VGA, the noise figure

was relatively poor, varying from 25 dB at the low end of the phase control range

(where phase shifter losses are at a maximum) down to 11 dB at the high end of the

phase control range (where phase shifter losses are at a minimum). This variation

in noise figure is roughly the same as the variation in the losses of the phase shifter.

In a receiver implementation the positions of the phase shifter and VGA would be

reversed, putting the high gain, low noise VGA before the phase shifter so that the

noise and losses of the phase shifter would have a greatly reduced impact on the

overall noise figure.

7.3.7 Power Consumption

The power consumption for each of the various blocks in the system is shown in Table

7.1. The total current draw (excluding pads and test and observation circuitry) is

12.6 mA, and the total power consumption is 23.6 mW. Since the feedback circuitry

is only used during periods when the phase and amplitude are being calibrated or

adjusted, the power consumption during normal operation is just that of the phase

shifter and VGA, which is 13 mW.

146

Block Current (mA) Vdd (V) Power (mW)

Phase Shifter 4 1.8 7.2

VGA 3.2 1.8 5.76

Buffer 2×0.5 1.8 1.8

Divider 2×0.5 1.8 1.8

Pulse Generator 0.2 1.8 0.36

Charge Pump 1.7 1.8 3.06

Phase LPF 0.6 3.3 1.98

Peak Detector 0.3 1.8 0.54

Amplitude LPF 0.6 1.8 1.08

Table 7.1: Power consumption for each of the system blocks.

147

Chapter 8

CONCLUSIONS

A system was proposed that allows the phase and amplitude of a signal to be

accurately set and regulated over process and power supply variations. The intended

application is in a phased array transmitter, where the phase and amplitudes of the

array elements are electronically adjusted to shape and steer the beam of radiation

in the chosen direction. Phase and amplitude errors introduced in the array elements

lead to degradation of the array pattern through effects such as sidelobe growth and

reductions in directivity.

The conventional means of setting the phase in a branch of a phased array is

through look-up tables storing the control voltage - phase relationships for the phase

shifter. This method does not compensate for changes in these relationships intro-

duced by processing variations between fabricated devices or changes in operating

conditions such as power supply voltage and temperature. Additionally, if the phase

shifter has variable gain over the phase control range then the amplitude will vary

depending on the phase setting. The proposed system uses a variable gain amplifier

(VGA) in conjunction with the phase shifter to compensate for the variable losses of

the phase shifter and simultaneously provide a means of adjusting the amplitude of the

signal. Dual feedback loops were employed to set the control voltages for the phase

shifter and VGA, allowing the phase and amplitude to be closely regulated across

process variations and adjusted to compensate for changes in operating conditions.

The phase shifter was implemented as a reflective-type phase shifter which provides

up to 310 of phase shift, and the VGA is a narrowband implementation with a

resonant load that provides about 20 dB of gain and is intended to be used as a power

148

amplifier driver. The phase feedback loop includes buffers to remove the amplitude

dependancy of the signal, high-speed dividers, a charge pump, and an active loop

filter. The phase of the system is specified by digitally controlling the charge pump

currents. The amplitude loop consists of an RF peak detector used in conjunction

with an active loop filter, and the amplitude is specified by setting an analog input

voltage to the loop filter.

The complete system was fabricated in a 0.18 µm CMOS process, and assembled

on a custom printed circuit board using chip-on-board bonding to allow testing and

characterization. The system operates at 1.9 GHz, and the phase can be set with

5 bits of control over a 240 range, and the amplitude can be varied over a 20 dB

range. The amplitude feedback loop reduced the variation in |S21| across the phase

control range from 12.1 dB for the open loop case to 0.4 dB. The phase feedback

loop reduced the variation in 6 S21 across the amplitude control range from 32.1 to

7.4. The standard deviation of the phase across the phase control range was reduced

from 9.4 to 1.8 for changing power supply voltages, and from 5.0 to 1.2 between

different test chips.

8.1 Future Research

The implemented system performed well, and successfully demonstrated the benefits

of the proposed architecture. There were a few limitations that could be corrected in

a revised version of the implemented system, such as the phase control range being

limited to 240. A future revision could provide the full control range of 360 by

employing a phase shifter with over 360 of phase control range. Another limitation

was the nonlinearity in the phase characteristics introduced by variations between

different charge pump unit current elements. This could be improved through the use

of better layout techniques, such as laying out all of the current elements in a regular

array with interdigitated devices and dummy devices surrounding the array.

There are also a number of extensions that could be made to the work described in

149

this dissertation, such as employing a similar architecture for a phased array receiver.

The biggest change for this case would be to reverse the positions of the phase shifter

and VGA to achieve a better noise figure. A practical implementation of this system

in a phased array would have more than one branch integrated on the same die,

so another step towards a complete system would be to implement a number of

phase/amplitude control paths on the same die and investigate the impact of the

substrate noise and interactions on the accuracy of each branch.

150

BIBLIOGRAPHY

[1] J. Ruze, “Pattern degradation of space fed phased arrays,” MIT Lincoln Labo-ratory, Project Rept. SBR-1, Dec. 1979.

[2] S. Haykin, Digital Communications. New York: John Wiley & Sons, 1988.

[3] S. Blostein and H. Leib, “Multiple antenna systems: Their role and impact infuture wireless access,” IEEE Commun. Mag., vol. 41, no. 7, pp. 94–101, 2003.

[4] A. Alexiou and M. Haardt, “Smart antenna technologies for future wireless sys-tems: Trends and challenges,” IEEE Commun. Mag., vol. 42, no. 9, pp. 90–97,2004.

[5] A. Lozano, F. Farrokhi, and R. Valenzuela, “Lifting the limits on high-speedwireless data access using antenna arrays,” IEEE Commun. Mag., vol. 39, no. 9,pp. 156–162, 2001.

[6] D. Cox, “Universal digital portable radio communications,” Proc. of the IEEE,vol. 75, no. 4, pp. 436–477, 1987.

[7] D. Brennan, “Linear diversity combining,” Proc. IRE, vol. 47, pp. 1075–1102,June 1959.

[8] R. Murch and K. Letaief, “Antenna systems for broadband wireless access,”IEEE Commun. Mag., vol. 40, no. 4, pp. 76–83, 2002.

[9] S. Alamouti, “A simple transmit diversity technique for wireless communica-tions,” IEEE J. Select. Areas Commun., vol. 16, no. 8, pp. 1451–1458, 1998.

[10] G. Foschini and M. Gans, “On limits of wirelss communications in a fadingenvironment when using multiple antennas,” Wireless Pers. Commun., vol. 6,no. 3, pp. 311–335, 1998.

[11] E. Telatar, “Capacity of multi-antenna gaussian channels,” European Tran. onCommun., vol. 10, no. 6, pp. 585–595, 1999.

151

[12] G. Golden et al., “Detection algorithm and initial laboratory results usingV-BLAST space-time communication architecture,” IEE Electronics Letters,vol. 35, no. 1, pp. 14–16, 1999.

[13] D. Love, R. Heath, W. Santipach, and M. Honig, “What is the value of limitiedfeedback for mimo channels?” IEEE Commun. Mag., vol. 42, no. 10, pp. 54–59,2004.

[14] A. E. Zooghby, Smart Antenna Engineering. Boston: Artech House, 2005.

[15] H. J. Visser, Array and Phased Array Antenna Basics. West Sussex, England:John Wiley and Sons, 2005.

[16] R. J. Mailloux, Phased Array Antenna Handbook. Boston: Artech House, 2005.

[17] N. Tyler, B. Allen, and H. Aghvami, “Adaptive antennas: The calibration prob-lem,” IEEE Commun. Mag., vol. 42, no. 12, pp. 114–122, 2004.

[18] R. Sorace, “Phased array calibration,” IEEE Trans. Antennas Propagat., vol. 49,no. 4, pp. 517–525, 2001.

[19] G. Tsoulos and M. Beach, “Calibration and linearity issues for and adaptiveantenna system,” in IEEE Vehicular Tech. Conf., vol. 3, May 1997, pp. 1596–1600.

[20] M. Skolnik, Antenna Theory. New York: McGraw-Hill, 1969, pp. 227–234.

[21] A. Hajimiri et al., “Phased array systems in silicon,” IEEE Commun. Mag.,vol. 42, no. 8, pp. 122–130, 2004.

[22] T. Yamaji et al., “A four-input beam-forming downconverter for adaptive anten-nas,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1619–1625, 2003.

[23] J. Butler et al., “Beamforming matrix simplifies design of electronically scannedantennas,” Electronics Design, vol. 9, pp. 170–173, Apr. 1961.

[24] T. Ohira, “Adaptive array antenna beamforming architectures as viewed by amicrowave circuit designer,” in Asia-Pacific Microwave Conf., Sydney, Dec. 2000,pp. 828–833.

[25] D. Parker and D. Zimmermann, “Phased arrays-part ii: Implementations, ap-plications, and future trends,” IEEE Trans. Microwave Theory Tech., vol. 50,no. 3, pp. 688–698, 2002.

152

[26] E. Brookner, “Phased arrays around the world - progress and future trends,”in IEEE Int. Symp. on Phased Array Systems and Tech, vol. 3, May 1997, pp.1596–1600.

[27] C. du Toit et al., “Smart multibeam phased array antenna for GSM, GPRS andEDGE,” in IEEE Int. Symp. on Phased Array Systems and Tech., Oct. 2003, pp.146–151.

[28] K. Sheikh, D. Gesbert, D. Gore, and A. Paulraj, “Smart antennas for broadbandwireless access networks,” IEEE Commun. Mag., vol. 37, no. 11, pp. 100–105,1999.

[29] T. Ohira, “Analog smart antennas: an overview,” in IEEE Int. Symp. on Per-sonal, Indoor, and Mobile Radio Com., vol. 4, Sept. 2002, pp. 1502–1506.

[30] P. Sudarshan, N. Mehta, A. Molisch, and J. Zhang, “Antenna selection with RFpre-processing: robustness to RF and selection non-idealities,” in IEEE Radioand Wireless Conf., Sept. 2004, pp. 391–394.

[31] D. Banbury, N. Fayyaz, S. Safavi-Naeini, and S. Nikneshan, “A CMOS 5.5/2.4GHz dual-band smart-antenna transceiver with a novel RF dual-band phaseshifter for WLAN 802.11a/b/g,” in IEEE RFIC Symp., June 2004, pp. 157–160.

[32] T. Ohira et al., “Megalithic microwave signal processing for phased-aray beam-forming and steering,” IEEE Trans. Microwave Theory Tech., vol. 45, no. 12, pp.2324–2332, 1997.

[33] P. Wu et al., “New miniature 15-20-GHz continuous-phase/amplitude controlMMICs using 0.18-/mum CMOS technology,” IEEE Trans. Microwave TheoryTech., vol. 54, no. 1, pp. 10–19, 2006.

[34] F. Ellinger, R. Vogt, and W. Bachtold, “Calibratable adaptive antenna combinerat 5.2 ghz with high yield for laptop interface card,” IEEE Trans. MicrowaveTheory Tech., vol. 48, no. 12, pp. 2714–2720, 2000.

[35] A. Natarajan, A. Komijani, and A. Hajimiri, “A 24ghz phased-array transmitterin 0.18 µm cmos,” in Proc. Int. Solid-State Circuits Conf., San Francisco, USA,Feb. 2005.

[36] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. NewYork: Cambridge University Press, 2004.

153

[37] V. Vintola et al., “Variable-gain power amplifier for mobile wcdma applications,”IEEE Trans. Microwave Theory Tech., vol. 49, no. 12, pp. 2464–2471, 2001.

[38] D. Coffing et al., “A variable gain amplifier with 50-db control range for 900-mhzapplications,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2324–2332, 1997.

[39] B. Razavi, RF Microelectronics. New Jersey: Prentice Hall, 1998.

[40] F. Gardner, “Charge-pump phase-locked loops,” IEEE Trans. Commun., vol. 28,no. 11, pp. 1849–1858, 1980.

[41] J. Wallace, H. Redd, and R. Furlow, “Low cost MMIC DBS chip sets for phasedarray applications,” in IEEE MTT-S Int. Microwave Symp. Dig., June 1999, pp.677–680.

[42] K. Fujii, “A sophisticated analysis procedure for an MMIC phase shifter,” IEEEJ. Solid-State Circuits, vol. 33, no. 4, pp. 666–668, 1998.

[43] H. Hayashi et al., “A high-Q broad-band active inductor and its application toa low-loss analog phase shifter,” IEEE Trans. Microwave Theory Tech., vol. 44,no. 12, pp. 2369–2374, 1996.

[44] F. Ellinger, R. Vogt, and W. Bachtold, “Compact reflective-type phase-shifterMMIC for C-band using a lumped-element coupler,” IEEE Trans. MicrowaveTheory Tech., vol. 49, no. 5, pp. 913–917, 2001.

[45] K. Miyaguchi et al., “An ultra-broad-band reflection-type phase-shifter MMICwith series and parallel LC circuits,” IEEE Trans. Microwave Theory Tech.,vol. 49, no. 12, pp. 2446–2452, 2001.

[46] F. Ellinger, R. Vogt, and W. Bachtold, “Ultracompact reflective-type phaseshifter MMIC at C-band with 360o phase-control range for smart antenna com-bining,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 481–486, 2002.

[47] H. Zarei and D. Allstot, “A low-loss phase shifter in 180 nm cmos for multiple-antenna receivers,” in Proc. Int. Solid-State Circuits Conf., Feb. 2004, pp. 392–393.

[48] D. Viveiros, D. Consonni, and A. Jastrzebski, “A tunable all-pass MMIC activephase shifter,” IEEE Trans. Microwave Theory Tech., vol. 50, no. 8, pp. 1885–1889, 2002.

154

[49] H. Hayashi and M. Muraguchi, “An MMIC active phase shifter using a variableresonant circuit,” IEEE Trans. Microwave Theory Tech., vol. 47, no. 10, pp.2021–2026, 1999.

[50] H. Zarei et al., “A full-range all-pass variable phase shifter for multiple antennareceivers,” in Proc. Int. Symp. on Circuits and Systems, Kobe, Japan, May 2005.

[51] F. Ellinger, U. Lott, and W. Bachtold, “An antenna diversity MMIC vector mod-ulator for HIPERLAN with low power consumption and calibration capability,”IEEE Trans. Microwave Theory Tech., vol. 49, no. 5, pp. 964–969, 2001.

[52] F. Ellinger and W. Bachtold, “Novel principle for vector modulator-based phaseshifters operating with only one control voltage,” IEEE J. Solid-State Circuits,vol. 37, no. 10, pp. 1256–1259, 2002.

[53] A. Nagra and R. York, “Distributed analog phase shifters with low insertionloss,” IEEE Trans. Microwave Theory Tech., vol. 47, no. 9, pp. 1705–1711, 1999.

[54] F. Ellinger, H. Jackel, and W. Bachtold, “Varactor-loaded transmission-linephase shifter at C-band using lumped elements,” IEEE Trans. Microwave TheoryTech., vol. 51, no. 4, pp. 1135–1140, 2003.

[55] S. Hamedi-Hagh and C. Salama, “A novel C-band CMOS phase shifter for com-munication systems,” in Proc. Int. Symp. on Circuits and Systems, vol. 2, May2003, pp. 316–319.

[56] J. Wong, V. Cheung, and H. Luoung, “A 1-v 2.5-mw 5.2-ghz frequency dividerin a 0.35-µm CMOS process,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp.1643–1648, 2003.

[57] B. Razavi, K. Lee, and R. Yan, “Design of high-speed, low-power frequencydividers and phase-locked loops in deep submicron CMOS,” IEEE J. Solid-StateCircuits, vol. 30, no. 2, pp. 101–109, 1995.

[58] D. Parker and D. Zimmermann, “Phased arrays-part i: Theory and architec-tures,” IEEE Trans. Microwave Theory Tech., vol. 50, no. 3, pp. 678–687, 2002.

[59] K. Kobayashi et al., “Gaas HBT 0.75-5 ghz multifunctional microwave-analogvariable gain amplifier,” IEEE J. Solid-State Circuits, vol. 29, no. 10, pp. 1257–1261, 1994.

155

[60] R. Meyer and W. Mack, “A DC to 1-ghz differential monolithic variable-gainamplifier,” IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1673–1680, 1991.

[61] K. Koh, Y. Youn, and H. Yu, “A gain boosting method at RF frequency usingactive feedback and its application to RF variable gain amplifier (VGA),” inProc. Int. Symp. on Circuits and Systems, Arizona, USA, May 2002.

[62] R. Meyer, “Low-power monolithic rf peak detector analysis,” IEEE J. Solid-StateCircuits, vol. 30, no. 1, pp. 65–67, 1995.

[63] S. Zhak, M. Baker, and R. Sarpeshkar, “A low-power wide dynamic range en-velope detector,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1750–1753,2003.

[64] Y. Zhou and M. Wah, “A wide band CMOS RF power detector,” in Proc. Int.Symp. on Circuits and Systems, Kos, Greece, May 2006.

[65] D. Su and W. McFarland, “An IC for linearizing RF power amplifiers using enve-lope elimination and restoration,” IEEE J. Solid-State Circuits, vol. 33, no. 12,pp. 2252–2258, 1998.

[66] T. Georgantas, Y. Papananos, and Y. Tsividis, “A comparative study of fiveintegrator structures of monolithic continuous-time filters,” in Proc. Int. Symp.on Circuits and Systems, Chicago, USA, May 1993.