YSI IQ SensorNet Wastewater Process Monitoring and Control Instrumentation
A Building Block Approach to Sensornet Systems
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Transcript of A Building Block Approach to Sensornet Systems
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A Building Block Approach to Sensornet Systems
Prabal Dutta, Jay Taneja, Jaein Jeong, Xiaofan Jiang, and David Culler
Computer Science DivisionUniversity of California, Berkeley
Sensys’08 – Raleigh, NC – Nov. 5-7, 2008
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(Wireless) embedded systems are tightly coupled to the application
• Common– Computation– Communication– Storage
• Application-specific– Power– Sensing– Mechanical
PicoCube [Chee08]
Shimmer [Intel06]
Radar [Dutta06]
PEG [Sharp05] HydroWatch [Taneja07]
Redwoods [Tolle05]
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Serious applications go through three stages
PrototypeGoal: “Try it and see”“Rapid prototyping”
PilotGoal: “Unprecedented data”
“Realistic study”“Modest scale”
“Modest investment”“Well-enough executed”
Production“Reducing cost”
“Optimizing performance”“Improving manufacturability”
“Obtaining high reliability”“Finalizing mechanicals”
+
= AccrueLearningsArtifacts
Investments
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Epic design philosophy
• Consolidate deep expertise into reusable modules
• Integrate modules with simple glue
• 3 P’s : Prototype, Pilot, Production
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Outline
• Introduction• Related Work: Building the design rules• Design Rules• Building Blocks and Development Stages• Results• Revisiting the Design Rules• Conclusion
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Modular platforms and plug-and-play development
WINSng [Pottie00]
Mica [Hill01]Rene [Hill99] Mica2 [Xbow03]MicaZ [Xbow05]
PC/104 [Cerpa01] PASTA [Bajura05]
mPlatform[Lymberopoulos07]
WeC [Hill98]
WINS [Rockwell]
Stargate [Intel]
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Some (inconvenient) truths about these modular approaches
• Prototyping is simple…plug-and-play– Unspecified “faux busses” can result in signal conflicts
• Multiplexed busses can avoid conflicts– They present barriers to simple interfacing
• Lego-like snap together modularity is great– Backplanes and board stacks
• Too Bulky• Waste space• Expensive relative to other components• Too fragile for experimentation and pilots (max insertions)• Force 3D board packaging geometry
• 51-pin connector is ubiquitous!– It fails the “Goldilocks test”– Instead of being “just right”
• Often too general for simple applications• And too limited for demanding ones
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Building the design rules
1. Modularity…– Really hard stuff must be reused unchanged
2. Snap/plug together– Good for prototyping…bad for production
3. Generic bus/backplane– Expensive, fragile, and often gets in the way
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Opposite view: the highly-integrated approach
WINSng [Pottie00]
Mica [Hill01]Rene [Hill99] Mica2 [Xbow03]MicaZ [Xbow05]
PC/104 [Cerpa01] PASTA [Bajura05]
mPlatform[Lymberopoulos07]
WeC [Hill98]
WINS [Rockwell]
Telos/Tmote[Polastre05]
Stargate [Intel]
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Some (inconvenient) truths about thehighly-integrated approach
• Bundles core, sensors, antenna, power, host interface, and expansion port
• Onboard sensors make great demos– Onboard sensors complicate the mechanicals– Some sensors don’t make sense: TSR/PAR next to Temp/Hum
• Integrated USB host interface makes software development easy– Integrated USB host interface adds cost and goes unused in
production
• IDC expansion slot– Forces 3D board stacking or cabling– Realistic pilots strained because too few I/O are exposed
• Integrated power with battery/host cutover– Hard to intercept power lines for measurement or debugging
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Building the design rules
1. Modularity is good2. Snap/plug together3. Eliminate bus/backplane4. Export everything
– Don’t limit generality
5. Partition functionality– Eliminate waste
6. Remove the sensors– They’re application-specific
7. Separate the power supply– It’s application-specific– Make current measurements easy
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Emerging commercial platforms are designed for manufacturability
WINSng [Pottie00]
Mica [Hill01]Rene [Hill99] Mica2 [Xbow03]MicaZ [Xbow05]Iris [Xbow07]
PC/104 [Cerpa01] PASTA [Bajura05]
mPlatform[Lymberopoulos07]
WeC [Hill98]
WINS [Rockwell]
Telos/Tmote[Polastre05]
Tmote Mini[Sentilla07]
MicaZ Stamp[Xbow06]
Iris OEM[Xbow07]
Stargate [Intel]
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Some (inconvenient) truths about theproduction-quality, assembly-optimized modules• Excellent radio performance
– Might still require RF engineering
• Ideal for high-volume, pick-and-place assembly– Hard to socket or hand-solder for prototype and pilot
studies– Hard to probe I/O lines for debugging
• Narrow interface makes integration easy– Hides many internal signals useful for research
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Design rules for application-specific platform development
1. Modularity is good2. Snap/plug together3. Eliminate bus/backplane4. Export everything5. Partition functionality6. Remove the sensors7. Separate the power supply8. Performance at worst -suboptimal9. RF out-of-the box10.Socketable11.Hand-solderable
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Design Rules redux
1. Modularity is good2. Snap/plug together3. Eliminate bus4. Export everything5. Partition functionality6. Remove the sensors7. Split power supply8. Only -suboptimal9. RF out-of-the box10.Socketable11.Hand-solderable
• Partition functionality
• Export wide electrical interface
• Eliminate the system bus
• Modules at worst -suboptimal
• Support many physical interconnects
Epic Building Block design rules
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Epic building block approach to supportprototype, pilot, and production• Two architectural elements
– Module– Carrier
• Module– General-purpose subsystem– Reusable, self-contained– Multi-chip module package– Composed of one or more
ICs and discrete components
• Carrier– Application-specific glue– Glues together
• General-purpose modules• Application-specific sensors,
power supplies, mechanicals
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Epic building block approach: a concrete example
Teaching/Experimentation-Sensors: via connectors-Power: USB, Li+, Alkaline-Mechanical: All I/O exposed
Research/Measurement-Sensors: temp/hum/light-Power: USB, Alkaline-Mechanical: Telos-like
Scientific/Application -Sensors: V/I/temp-Power: AC, USB-Mechanical: Wall plug
Core
Prototype
StorageUSB
Pilot Production
Start with modules
Incorporate with carriers
Create platforms
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Outline
• Introduction• Related Work: Building the design rules• Design Rules• Building Blocks and Development Stages• Results
– Prototype– From Pilot to Production– Organic Reuse
• Revisiting the Design Rules• Conclusion
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Prototyping: experimentation and debugging
Breakout Board Development Board Interface Board
PhidgetsInterface Board
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Result: Five application-specific platforms in six months with five grad students
HydroWatch Benchmark ACme
PowerNet(Stanford)
Gal, Heller, Kazandjieva
Quanto Testbed
Dutta
Dutta
Jiang
Meraki Daughterboard
Dutta, Goto
Jeong, Taneja
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Carriers: gluing together module with app-specific sensors, power supplies, and mechanicals ACme
AC Meter & CtrlBenchmark
Testbed measurementMeraki Daughterboardb6lowpan border router
1. Modules: Core2. Sensors: T/H/L3. Power: Solar, NiMH 4. Mech: NEMA 4 encl5. PCB: 2-layer6. Design: 2 days7. $10.83 ea @ 60 pcs8. Fab Leadtime: 5-day
1. Modules: Core2. Sensors: V, I3. Power: AC4. Mech: enclosure5. PCB: 2-layer6. Design: 1 week7. $26.40 ea @ 5 pcs8. Fab leadtime: 5-day
1. Modules: Core, USB2. Sensors: E/T/H/L3. Power: USB4. Mech: Telos-like5. PCB: 4-layer6. Design: 3 days7. $141.30 ea @ 10 pcs8. Fab leadtime: 5-day
1. Modules: Core2. Sensors: T/H3. Power: Meraki4. Mech: Meraki5. PCB: 2-layer6. Design: 5 hours7. $33 ea @ 6 pcs8. Fab leadtime 5-day
HydroWatchEnvironmental Mon.
All first articles were hand-assembled in hours.Shortens platform development time-to-result.Makes custom platforms broadly accessible.
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A New Testbed Node: Epic + iCount + Quanto
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Approach promotes reuse in modules, CAD parts, inventory, subsystems
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Outline
• Introduction• Related Work• Design Rules• Building Blocks and Development Stages• Results• Revisiting the Design Rules• Conclusion
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The design rules
• Partition functionality
• Export wide electrical interface
• Eliminate the system bus/backplane
• Modules at worst -suboptimal
• Support many physical interconnects
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Where do modules come from?Heuristics for partitioning functionality
If the answer to any of these questions is yes, then make it a module.Otherwise, it’s a carrier board.
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Export a wide electrical interface…actually, just export everything (almost)
4SPI
SPI
SFDCCAFIFOFIFOP
2ENA/RST
ATEST1ATEST2
RFOUTRFGND(2)
4
WPRST
RVDD
FVDD
VREF+VeREF+VeREF-
P4 / GPIO [LED(3)]3
P5 / GPIO
JTAG OSC
P6 / ADC / DAC / GPIO
P1 / GPIO
P2 / GPIO
8
8
5
4
P3 / USART / GPIO4
DVDD AVDD P4.1P1.4P1.3P1.0
P4.5/P4.6
P3/SPI0
P5/SPI1
P1.7
OSC
RST
U.FL
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LCC-68 PAD FRAME
P2.4 ONEWIRE
MSP430F1611 CC2420
AT45DB161D
DS2411
AGND
2
RFRXTX
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Modules can be only –suboptimalif they are to be enthusiastically adopted
Node Sleep Current
Wakeup Time
Epic 7 µA 629 ± 3 µs
Telos/Tmote 6 µA 619 ± 3 µs
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Support many physical interconnect options
Socketing
Hardware Inlining
“Routed Vias”1. Free connector2. Easy to solder3. Easy to probe4. Connect all layers
LCC-68footprint
Prototype
Pilot
Production
Hand
Sold
erin
g
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Conclusion
• Near-optimal platform decomposition– From “try it and see” to high-volume
production– Enables rapid platform development through
reusable carriers, modules, and CAD parts
• Epic is Open Source Hardware– CAD source, gerbers, BOM available online– Share you CAD parts and board designs!
http://www.cs.berkeley.edu/~prabal/projects/epic
Jan’08Oct’08
PowerNet (Stanford)
TinyOS 2.1 support:Make epic install [miniprog]
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Questions?
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Backup Slides
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A cautionary tale:achieving only –suboptimality takes a lot of work
4 mil
20 mil