A Basic Introduction to the gm/ID-Based DesignMethodology

0.1 Abstract

This article introduces the reader to the gm/ID-baseddesign methodology, which is a way to help CMOSanalog circuit designers link physical transistor pa-rameters to small signal models. It is written at thelevel of university students who are taking a firstcourse on analog integrated circuits. It is also rel-evant to experienced engineers interested in a designflow that incorporates technology details early in thedesign cycle and yields excellent agreement betweenhand-calculations and circuit simulations.

0.2 Introduction

Following perhaps a long road to maturity, CMOShas become an excellent platform for analog circuitdesign. Not only is it unrivaled in switching andcharge-mode processing, but it benefits from persis-tent process improvements fueled by the digital con-sumer market. Unfortunately, designers may find itvery difficult to take advantage of these strengths. Aprimary reason for this is that CMOS behavior is hardto predict without using very complex models, andthis complexity only worsens with technology scal-ing. Designers, incidentally under pressure to meetdeadlines, are forced to either incorporate complexmodels into their hand calculations or spiral into aSpice-intensive design loop. Neither of these strate-gies are as effective or pleasant as we would like.

My goal in this article is to introduce you to thegm/ID-based design methodology, which greatly im-proves the predictability of CMOS small-signal be-havior without requiring complex equations. We willdefine the ratio gm/ID in more detail later, but fornow, just think of it as a design variable that encap-sulates the biasing conditions of a MOS transistor.Or, even more concisely:

gm/ID bias point small-signal model

Development of the methodology will involve severalsteps. We will start with a very broad overview ofanalog circuit design to see what problem it is thatwe are attemping to solve, and how it has been solvedin the past. I will then explain, at a qualitative level,

Figure 1: Low-level circuit implementation is oftenmore difficult than higher-level design.

why the gm/ID-based approach is the best tool forsolving this problem. Next, we will rehash the en-tire discussion at a quantitave level. This will entaila review of transistor operation and a chronologicaldevelopment of the tools we have available. Finally,we will close with a thorough design example.

0.3 The Big Picture

0.3.1 Analog Design Relies on Ab-straction

Fig. 1 shows several levels of abstraction in which wecan view an analog design. Thanks to abstractions,engineers working at the higher levels can performanalysis using linear Signals-and-Sytems theory. Thisis the domain of filters, gain blocks, OpAmp circuits,etc. The mathematics that govern this realm are el-egant, often with centuries-old roots. Consequently,we have gotten very good at understanding how towork with these blocks. Most engineering schoolssend students through an entire battery of coursesthat satisfactorily cover this area.

Descending to the lower levels, there is a differentstory. While we find it straightforward to build again-of-two stage using an OpAmp, we find it verydifficult to build the OpAmp itself. How big shouldeach transistor be? How much bias current is needed?These low-level decisions can be unclear, and thereare two big reasons why. First, transistor behavior

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Figure 2: Small-signal model of a transistor.

is nonlinear, and classical Signals-and-Systems anal-yses fall apart when applied to nonlinear systems.Second, technology advancements change the rules ofthe game faster than we can make them. There areno centuries-old roots here! As a result, we simply donot have a nice set of transistor equations that is bothcompact enough for hand calculations and accurateenough to match Spice simulations.

0.3.2 Making Low-Level Design Man-ageable

We can make low-level design easier if we transformtransistors into Signals-and-Systems-friendly devices.As you know, we do this by approximating each tran-sistor with a few ideal elements, collectively referredto as a small-signal model. Fig. 2 shows a basic andfamiliar small signal model of a MOSFET. It alsohighlights the translational role that gm/ID (or itspredecessor, Vov, another biasing variable) plays inthe design process. Of course, the drawback of usingsmall-signal models is that they introduce errors, asall approximations must. But that is far outweighedby the benefits of using Signals-and-Systems tech-niques, without which we would not have conceptslike gain, bandwidth, frequency response, poles, andzeros!

Fig. 3, then, is a good illustration of how the gm/ID-based design methodology fits into the big picture.At the top is the abstract Signals-and-Systems world,where we are very comfortable. At the bottom arephysical transistors, which, in the end, must behavethe way we want them to. Sitting in the middle of allthis is gm/ID, an intermediate biasing variable thatbridges the abstract-to-physical gap very well. Keepthis picture in mind as we continue our discussion.

Figure 3: Small signal models allow us to use tran-sistors in a Signals-and-Systems context.

0.3.3 Why gm/ID is Better than Vov

Vov-based design, which we will shortly cover in moredetail, long predates gm/ID-based design. As we havealready hinted, both Vov and gm/ID are quantitiesthat tell you something about the bias point of a tran-sistor. So, how are these approaches different?

When CMOS designers choose to follow a Vov-baseddesign strategy, they implicitely accept the validityof the long-channel model. I am certain that you arefamiliar with the long-channel model (we will alsoreview it in a later section). When we were firsttaught how to analyze a MOSFET, we were showna derivation of it using basic calculus. Unfortunately,most of the assumptions that make the derivation soclean are untrue for todays small geometries. Conse-quently, the Vov-based methodology no longer yieldscircuits that behave as intended. In order to salvagethe model, designers have tried to patch it with short-channel effects and a variety of curve-fitting termsthat are (sometimes only wishfully) based on differ-ent physical arguments. But in the end, Vov-baseddesign only gets harder and less accurate.

Our new strategy, gm/ID-based design, does not relyon the validity of the long-channel model. In fact,it does not rely on the validity of anything exceptsimulation. This methodoloy is lookup-table-based.The underlying philosophy is that the equations gov-erning MOSFETs are so complex that we must get

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Figure 4: High-level comparison of two popular de-sign methodologies.

rid of them in favor of a few tables or graphs. Andbecause these graphs are generated using device sim-ulations in Spice, they are much more accurate thanthe long-channel model could ever hope to be.

It is no stretch to say that most of us cringe a little atthe thought of using a lookup table. With the adventof cheap and powerful computing, we electrical en-gineers have lost touch with filter tables, log tables,trigonometric tables, and the like. But our currentequational exclusivity has been only a brief fad inour industry. Just as vacuum tube circuit designersonce used (and still use!) tube curves, so we are redis-covering the value of table-based design for situationswhere it is the most efficient means of computation.

Fig. 4 compares Vov-based design and gm/ID-baseddesign in a side-by-side summary. In both cases, weneed physical information about the technology tar-get. After all, the capabilities of the target will ob-viously affect transistor performance greatly. In thecase of the long-channel model, the technology datamust be limited to only the barest of essentials, suchas and Cox, otherwise hand calculations become in-tractible. Consequently, initial designs may only getwithin an order of magnitude until the designer gets afeel for that process. Meanwhile, the gm/ID-basedmethod utilizes complete Spice models from the tech-nology target and yields initial results that only re-quire minor tweaking.

0.4 The More-Detailed Picture

Now I want us to start over trying to solve the designproblem, but at a more quantitative level. We willreach the same conclusion, of course, even though weare taking a very different approach.

A First Attempt at Transistor-Level Design

How might an intelligent-but-inexperienced engineergo about designing a circuit? Of course, I have apreferred method towards which I am working, butit is certainly worthwhile to see if we can solve thedesign problem without knowing the answer ahead oftime.

To begin, let us step back and ask, what will ourfinished design look like? Or, what is a finished de-sign? In the context of this article, it is a netlist.Ultimately we just want a file that contains specifica-tions for all the transistors, resistors, capacitors, etc.,and explains how they are all connected together. Ofcourse, in the real world, circuits must be fabricated,and designers must be wary of the limitations of simu-lation itself, and how well it agrees with actual mea-sured performance, but those concerns are beyondour scope here.

If our end goal is a netlist, why not start with thenetlist and work backwards? What kinds of informa-tion do we need in order to fill in the blanks? Forreference, here is a line that instantiates a transistorin Hspice:

M1 drn gat src blk nchmodel L=0.18u W=10u

Well, which blanks can we fill in? Put another way,how do we design a transistor? Obviously, VT , , Cox,and other familiar transistor quantities are not amongthe parameters we get to specify. In fact, apart fromthe terminal connections, it looks like we only get tochoose W and L.

Is that all there is to it? Is circuit design just a matterof deciding how big each transistor is? Well, yes andno. With the exception of some advanced options(such as source or drain sharing, or multi-fingeredgates),W and L really are the only transistor charac-teristics that you get to explicitely specify. You hookthem together, size them correctly, and you almosthave the whole thing. Really!

One possible design method, then, might be to justuse W and L directly as design variables. This pro-cess would be something like the following:

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1. Assume you have a usable topology.

2. Guess a bunch of values for W s and Ls (andpossibly Rs and Cs).

3. Simulate in Spice.

4. See if the design meets all the specifications

5. If not, modifyW s and Ls (and possibly Rs andCs) and go back to Step 3.

Note: This kind of iterative process is some-times called Spice Monkeying, and its useis strongly discouraged. It is very commonfor designers of all experience levels to lapseinto Spice Monkeying in the face of loomingdeadlines!

This strategy, however tempting, does not work wellin practice. First, the sheer length of time requiredfor simulation makes it impractical to run too manyof them (and this is true even if you automate theprocess). More importantly a Spice-intensive designmethod is a blind trek, completely devoid of intuition.Spice is good for analyzing a design and making finaltweaks, but it is not very good at helping you decideamong the infinitude of topologies, sizings, and biaspoints available in an open-ended task.

All this is summarized in the simplified design flowshown in Fig. 5. The inner-most loop, loosely calledthe hand calculations phase, is where we have thebest opportunities to make big-impact decisions. Ifwe have meaningful and accurate small-signal models,we can make informed and confident decisions in thisinner loop without resorting to frequent simulation.Let us see if we can develop a reliable link betweensmall-signal models and actual transistor behavior.

0.4.1 Long-Channel Model Review

The best vehicle to carry us further on our quanti-tative discussion of MOSFET behavior is the long-channel model. Of course, I just told you that thismodel was inadequate, but, just to be clear, I am notadvocating its complete abandonment. The deriva-tion may be over-simplified, but it still usually givesthe right kind of intuition; and we do not want to berobbed of that. In addition, it is simply a good placeto start when discussing transistor modelling.

The long-channel model attempts to describe the re-lationships between drain-current, ID, and the termi-nal voltages, Vds and Vgs. The plot in Fig. 6 is one

Figure 5: We can do more effective optimization inthe hand-calculations phase than in the simulationsphase of the design process.

of the most commonly used to display these relation-ships. One thing that is a little different about thisplot, compared to others you may have seen, is theuse of Vov instead of Vgs. Vov is called the overdrivevoltage, and it is defined as follows:

Vov = Vgs VT

Vov tells you how inverted the channel is, and is alittle easier to work with than Vgs, in part becauseit hides any dependence on VT . Inversion, so-calledbecause the material in the channel (e.g. p-type),starts to behave like the inverse type of material (e.g.n-type), can be roughly interpreted as ON-ness. Itis because it controls the level of inversion that wecan consider Vov to be a biasing variable. Sometimesthe condition of having a very small Vov is referred toas weak inversion while a large Vov may cause stronginversion.

Also denoted in Fig. 6 are the three operating regions:cutoff, linear and saturation. We will quickly go overeach one.

Note: This is an N-Channel-centric review. You willhave to apply the usual flips to get the P-Channelrelationships.

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Figure 6: In the saturation region, ID is primarily afunction of Vgs.

Cutoff Region

Condition Vov < 0, (or, equivalently, Vgs < VT )There is no channel inversion, so no current flows

ID = 0

Linear Region

Condition Vov 0 and Vds < VdsatThere is channel inversion, but ID is heavily affectedby Vds

ID =12Cox

W

L

[2VovVDS V 2DS

]The linear region is always of concern when the tran-sistor is being used as a switch. In that case, you canalso define its ON-resistance.

Ron VdsID

Saturation Region

Condition Vov 0 and Vds VdsatID becomes purely a function of the gate voltage, Vov(not of Vds)

ID =12Cox

W

LV 2ov

Figure 7: A saturation-centric view of transistor bi-asing.

Saturation is the desired operating region for most ofthe transistors in the signal path, other than switches.In fact, for the rest of this article, we will oper-ate almost exclusively in the saturation region. Aslong as each transistor has enough headroom, mean-ing that we maintain Vds Vdsat, then we can adopta saturation-centric point of view, which is shown inFig. 7. Note that, as Vov increases, not only does IDincrease, but gm grows as well due to the quadraticequation. In other words, gm is a function of Vov.Keep this picture in the back of your mind.

0.4.2 Introduction to the Vov-BasedDesign Methodology

gm, fT and Making Sense of Transistor-LevelDesign

Now that we have been introduced to Vov, we can de-velop it into a design variable. Remember, we even-tually need it to tie into the small signal model shownin Fig. 2. The first element in the model we will workon is gm, which is just the slope of the ID vs. Vovcurve.

gm =IDVov

= CoxW

LVov

With a little algebraic manipulation, we can derivean interesting equation, which, as you may recognize,contains both of the biasing variables that we areinvestigating.

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gmID

=2Vov

I bring this up now for two reasons. First, it gives youan idea of the relationship between gm/ID and Vov.We will see later that this equation is inadequate,because the actual relationship between these termsis much more complex. But for now, just keep inmind that these two quantities are somewhat similar.

A second reason for bringing up this equation is todefine tranconductor efficiency, which is just anotherword for gm/ID. This title is appropriate if you un-derstand its meaning. I like to give it the intuitiveunits ofmS/mA (rather than simplifying to 1/V ) be-cause it captures the spirit of the term. It tells youhow much gm (in mS) you get when you invest agiven ID (in mA).

Going back to gm itself, let us look at some expres-sions we can derive for it and see if we can make anysense out of them. Here is what we know so far:

gm = CoxW

LVov =

2IDVov

What does this mean? Is gm is proportional to ID?If you want more transconductance, do you have toinvest more current? That seems reasonable. Buthow about Vov? Well now I know we are in troublebecause it is in the numerator in one case and in thedenominator in the other!

In order to move forward, let us assume that we canprogram Vov to any constant we want. Furthermore,we are going to think of Vov as a knob that we canuse to determine transistor behavior. We could havechosen a different knob, like ID or W/L, but Vov willturn out to be a better knob than these.

Let us do an example to show why a constant Vov isa nice thing. In Fig. 8, we will operate M1 with a Vovof 300mV. This is a reasonable value, and it is alsoan arbitrary choice. Also, arbitrarily, suppose thatID = 1mA. How can we analyze this circuit?

M1 has 1mA of drain current, and superimposed onthis is some signal current, is, which is a functionof vin. What kind of function? We are assuming alinear one based on gm. In fact, we expect somethinglike this:

vout = is R = vin gm 1k

And because we know Vov and ID, we know gm

Figure 8: Example circuit.

gm = 2ID/Vov =2 1mA300mV

= 6.7mA

V

voutvin

= 6.7mAV

1k = 6.7VV

In fact, we can use ID to make the gain whatever wewant. Suppose we double it.

gm = 2ID/Vov =2 2mA300mV

= 13.4mA

V

voutvin

= 13.4mAV

1k = 13.4VV

What a breeze! Once we make Vov a constant, we canprogram the gain by adjusting ID. Analog design inCMOS is so easy.

Well, not quite. Though later when we get finishedwith gm/ID-based design, you might actually feel thisway a little bit! But we are not there yet. There issomething very obviously wrong with what we havedone. You may have caught if you are paying atten-tion. If we can make Vov whatever we want, thenwhy not make it zero? Is that not the ideal value? Imean, if the following relationship is true,

gm =2IdVov

then zero Vov would make the circuit infinitely effi-cient! Certainly your suspicions are aroused, as theyshould be any time you manage to make a circuit in-finitely efficient. We must be doing something wrong,but what?

It is actually something very basic. We have beenignoring speed. How fast is our transistor? Can we

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Figure 9: Vov controls the tradeoff between transcon-ductor efficiency and fT .

put speed in terms of Vov? The answer, of course, isyes, and the derivation is painless. First, we define

fT =(

12pi

)gmCgs

This is often called the transit frequency, and it is theanswer to the question How fast is this transistor?In saturation, Cgs = 23CoxWL. If we plug that backinto the long-channel model, we get

fT =12pi

gmCgs

=12pi

2Vov3L2

Well, guess what. Now we know why we cannot makeVov arbitrarily small because it limits speed. Wehave found a gm vs. fT tradeoff, which is illustratedin Fig. 9.

Let us examing Fig. 9 more closely. Earlier, we de-cided that Vov was a knob that we could use to adjusttransistors. At the time, I told you it was an arbi-trary decision, but now perhaps it is starting to looklike it was also a good one. Two things that we careabout, gm and fT (which could roughly translate asgain and bandwidth), are both dependent on Vov invery simple ways. Even better, these two things haveconflicting interests regarding Vov, which means wecan find an optimum and make design choices. Forexample, if we can live with a slow design, then wecan use a low Vov, which will yield a high transcon-ductor efficiency (i.e. low power). On the other hand,if the circuit needs to be fast, we must operate with a

Figure 10: Vov is like a gm vs. fT knob.

Figure 11: Design example showing how to use Vov.

high Vov and live with lower transconductor efficiency(i.e. high power).

This really is the heart of the matter. Vov is use-ful precisely because it lets you manage the tradeoffbetween two of the things you need most in analogdesign. Think of it like the screwdriver in Fig. 10. Fora fixed current, ID, we can use Vov to decide whetherwe want to spend that current investment on gm (toget more gain) or on fT (to get more bandwidth).

Now we want to plug all this back into the designflow. Remember Fig. 2. We want to be able toapproximate a transistor, which is nonlinear, with asmall signal model, which we can use in Signals-and-Systems analysis. We can illustrate how to do thiswith an example.

Using the circuit in Fig. 8, suppose we want 500MHzbandwidth and we want a gain of 10. One possible de-sign flow, listed here, can be followed along in Fig. 11.

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1. To achieve the required gain, we must have

gm = 10V

V/1k = 10mA/V

2. And for an input pole at 500 MHz, we need

Cgs =1

2pi 300 500MHz = 1.1pF

3. We can then easily calculate the required transitfrequency

fT =gmCgs

=10mS1.1pF

= 9.4GHz

4. Which means (see Fig. 9, Note 4)

Vov 75mV

5. Which means (see Fig. 9, Note 5)

gm/ID 26mS/mA

6. And finally

ID =gm

gm/ID=

10mS26mS/mA

= 385A

Pretty easy, really. Not only that, but we know thatour design is efficient. A larger Vov would deliver afaster-than-necessary transistor, and we would wastepower. A smaller Vov would deliver a slower-than-required transistor, and we would not achieve the de-sign goals.

Note that ro has not been determined, so technicallythe small signal model from Fig. 2 is a little lacking.In this article, will not deal with ro in a Vov context.Later, once we have introduced gm/ID-based design,we will investigate the limitations due to ro.

In summary, finding an optimum operating point us-ing the Vov-based design methodology is much morestraightforward than working brute force with W orL. And thinking in terms of Vov makes it easy todeal with the interdependencies of gm, Cgs and bi-asing than by trying to manage these independently.The only real problem, as we pointed out earlier, isthat the long-channel model is not accurate.

0.4.3 The Limitations of Vov-BasedDesign

We have been hinting all along that the long-channelmodel is just way too simple to make Vov-based design

reliable - even if we patch the model with extra Greekletters. Now it is time to present some hard evidence.

The first bit of evidence is simple common sense:Why do you think Spice uses dozens of transistorparameters during simulation? Do you think thatit ignores all but 2 or 3 of them? Of course not!Consequently, we should be shocked (and modellingengineers should be embarrassed) if and Cox provedto be as complete as the entire Spice model.

Figs. 12 and 13 illustrate this graphically. In Fig. 12,we compare actual transconductor efficiency simu-lated in Spice to the long-channel prediction. Forlarge values of Vov, the long-channel model is only offby 25% - not too bad. But for small Vov, the valuesare nonsense - most notably at Vov = 0, where it stillinsists on infinite transconductor efficiency. Fig. 13shows that the long-channel model does no betterin predicting fT . And the intersection where bothgraphs are on target is hardly existent at all.

You may also have noticed that Figs. 12 and 13 con-tain a region of negative values for Vov, which is alsocalled the subthreshold region. The long channelmodel predicts that for Vov 0, ID = 0, implyingwe should never bias a MOSFET near VT because itmight turn off. But the simulation data in Fig. 12shows that gm/ID actually continues to climb as wehead into the subthreshold region, which means thatthis may really be a useful biasing point. Is it?

In fact, the subthreshold and weak inversion regionsare very important in low-power designs. Fig. 13 ex-plains the tradeoff, which is that subthreshold tran-sistors are slow. But keep in mind that they are notthat slow in newer technologies. In fact they can oftenbe much faster than we need them to be, which allowsdesigners to trade some of that speed for low power.For many of todays power-constrained designs, sub-threshold operation is imperative, and a model thatdoes not accomodate this region is useless.

What does all this mean? It means that, although Vovis a very good design variable in theory, it does notwork in practice. If the long channel model were ac-curate, then Vov-based design would work brilliantlyand there would be no reason to look elsewhere. Butthe long-channel model does not work and so we needa new design varible: something in the spirit of Vov,but that yields better agreement between hand cal-culations simulation.

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Figure 12: Vov does not predict transconductor effi-ciency very well.

0.4.4 Introduction to the gm/ID-BasedDesign Methodology

gm/ID as a Design Variable

For starters, suppose we tried to keep Vov as a designvariable. We could use simulations to see how Vovaffects both transconductor efficiency and fT , similarto what was done in Figs. 12 and 13. Using those twocharts, we can certainly find the best value for Vov tosuit our needs.

Fortunately, someone has already come up with amuch better idea that encapsulates all this informa-tion compactly. Recall that Vov and gm/ID are simi-lar, biasing-related quantities. If they are so similar,maybe we can get rid of one of them. The clevertrick is to plot fT vs. gm/ID directly, as shown inFig. 14. This plot lets you see exactly how increas-ing transconductor efficiency comes at the cost of fT .We are cutting out the Vov middle-man, so to speak.From here on, gm/ID is the only biasing variable wewill need.

By the way, where is the subthreshold region inFig. 14? You can get a hint by looking at Fig. 12.The subthreshold region is where we expect to findthe highest values for transconductor efficiency. Inother words, it lies somewhere on the far right side ofFig. 14. Does it matter exactly where it begins? Ofcourse not! We know gm/ID. We know fT . The re-gion we are in is irrelevant. In fact, with the exceptionof the linear region, of which we must always be care-

Figure 13: Vov does not predict fT very well.

Figure 14: A more direct depiction of the gm/ID vs.fT tradeoff.

ful, all the regions of operation become transparentwhen we use the gm/ID-based design methodology.

Again, let us do an example based on the circuit inFig. 8. And, again, assume that we want a signalbandwidth of 600MHz, a gain of 10, and that wewant to use as little power as possible. We can followalong in Fig. 15 to do the design.

1. To achieve the required gain, we again must have

gm = 10V

V/1k = 10mA/V

2. And for an input pole at 500 MHz, we still need

Cgs =1

2pi 300 500MHz = 1.1pF

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Figure 15: Using gm/ID in a simple design.

3. So the transit frequency must be

fT =gmCgs

=10mS1.1pF

= 9.4GHz

4. Which means (see Fig. 15, Note 4)

gm/ID 17.5mS/mA

5. And finally

ID =gm

gm/ID=

10mS17.5mS/mA

= 570A

Easy. Of course, so was the Vov-based method welooked at earlier. The important difference is thatthese new relationships are accurate.

Fig. 16 is a more complete (and actually our final)version of the fT vs. gm/ID design chart. It incor-porates the effect of channel length, L, on transistorspeed. Several lengths are included, ranging from theprocess minimum up to a reasonably large value. Wewill explain how to create this chart in a later section.

Let us look closely at Fig. 16. For any given value ofgm/ID, a larger L always means a slower transistor.This means that, if we have no other constraints, weshould always choose the shortest-length transistoravailable (i.e. the process minimum). It also meansthat there must be some other constraint we mightneed to consider. That constraint is ro, and we willcover it now.

Figure 16: An fT design chart for a 0.18m process.

Figure 17: ro of a common-source amplifier appearsas an additional load.

What about ro?

Fig. 17 explicitely highlights ros place in a transistorcircuit. As you know, ro is simply another load inparallel with RL. In practice, we usually either wantro RL so that ro can be ignored, or we will makeRL very large (perhaps using a current source insteadof an actual resistor) in order to get as much gain aswe can. I want to examine the second case. Let ussee what happens as RL .Fig. 18 illustrates this case effectively. When ro be-comes the dominant resistive load, the overall gainis limited by what we refer to as the intrinsic gainof the transistor. Intrinsic gain is the product of gmand ro and tells us the highest (Voltage) gain we canpossibly get.

Intrinsic Gain = gmro(VV

)10

Figure 18: What is the maximum gain we can getfrom a transistor?

Figure 19: An intrinsic gain chart for a 0.18m pro-cess.

In practice, intrinsic gain is a more convenient num-ber to know than ro itself (we will see why shortly).Mathematically they are quasi-equivalent. That is,you can put gains in parallel just like you can putRs in parallel. For example, if a circuit has an idealgain of 10, and you use a transistor with an intrinsicgain of 100, then the net gain degrades by about 10%.

We can use the concept of intrinsic gain to createanother design chart. Fig. 19 is similar to Fig. 16,except that intrinsic gain is the dependent variable.Like Fig. 16, it is plotted vs. gm/ID, and that is donefor several different channel lengths.

Figs. 16 and 19, taken together, comprise a very pow-erful design tool. Not only are they extremely helpfulin transistor implementation, but they also allow adesigner to understand the capabilities of the tran-sistors available in the technology target.

Figure 20: A biasing chart for a 0.18m process.

As an example, suppose you would like a circuit witha gain of at least 50. A quick glance at the intrin-sic gain chart tells you that this is certainly feasible.Choosing the minimum channel length, L = 0.18m,is probably too risky since it leaves no margin, butperhaps L = 0.28m would be conservative enough.

Now, what if we want a gain of 100? This time aquick glance at the chart says that we cannot get thisfrom a single transistor. We might need to either usemultiple stages, or perhaps try a cascode circuit inorder to increase the gain. Those are problems wecan solve. The important thing is that we know thisstuff now. We do not have to waste time trying tomake the design work with a single transistor, onlyto find out through several Spice iterations that itcannot be done.

In summary, these two charts give a fairly completepicture of transistor behavior based on gm/ID as adesign variable. We know how both fT and gmroare affected by both gm/ID and L. Because of thiswe can choose the best L and gm/ID for the job.And because the charts are simulation-based, we areconfident that they are accurate.

A small warning is in order before we move on. Beaware that ro is very dependent on Vds. The valuespresented in the charts are for Vds = VDD/2. If Vdsstarts to drop to near Vdsat (in other words, if youdo not have much headroom), then the intrinsic gainmay drop substantially (perhaps as much as 4 to 5).

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Biasing Using gm/ID

There is one final chart that I want to introduce.Figs. 16 and 19 are design charts. This new chart,shown in Fig. 20, is a biasing chart. You use Figs. 16and 19 to decide values for L and gm/ID. We canthen easily use Fig. 20 to look up the value of Wrequired to bias the transistor at our desired gm/IDvalue. W? Thats right! By the time we get tothis chart, everything else is determined. We know Lfrom gain requirements. We picked gm/ID in orderto guarantee some particular fT . And ID is pickedsuch that we get the right value for gm. The onlything left is W .

0.4.5 A Deeper Understanding of thegm/ID Method

What is the magic of the gm/ID-based designmethodology? For example, why does a specific valueof gm/ID always result in the same fT , no matterwhat else you do? Doesnt that seem strange? Whileunderstanding this is not critical to using the method-ology, it is worthwhile to have an intuitive idea ofwhy it works. A simple thought experiment actuallymakes this rather easy.

Fig. 21 shows a progression of transistor circuits.Suppose we measure both gm and Cgs for the transis-tor in circuit a. Logically, because the terminal volt-ages and bias currents remain unchanged, each of thetransistors in circuit b will also have these same val-ues for gm and Cgs. But, since there are two of themworking in parallel, the composite behavior presents adoubling of ID, gm, and Cgs. The key is that, becauseall of three of those things scaled together, circuit b asa whole has exactly the same gm-to-ID and gm-to-Cgs(i.e. fT ) ratios as circuit a. In fact, no matter howmany we put in parallel, we will always get the samegm/ID and fT . Do not move on until you convinceyourself that this is true.

Next, we need to make the step from circuit b tocircuit c. I actually think that you should find thisquite natural. For example in a current mirror, weexpect that we can use width ratios to create specificcurrent ratios. In fact sometimes these ratios are im-plemented with parallel unit elements anyway.

Finally, to complete the thought experiment, we mustagree that we can generalize this idea to say that anyratio will work, not just integers. This generalizationmeans that gm, ID and Cgs all scale linearly with W .If W increases by 25%, then we expect gm, ID and

Figure 21: A progression of transistor circuits thatall have the same value of gm/ID and fT .

Cgs to all increase by 25%, which always maintainsthe same ratios of gm-to-ID and gm-to-Cgs.

Intrinsic gain scales in the same way. The compositebehavior of circuit b presents twice the gm of circuit a,but it also puts two ros in parallel. You get twice thegm but half the ro, resulting in a composite intrinsicgain that is exactly the same as the transistor in a.No matter how many we put in parallel, the intrinsicgain will be the same. So, like fT , if we plot intrinsicgain as a function of the ratio gm/ID, then it becomesindependent ofW . It is this width-independence thatmakes intrinsic gain preferable to ro in terms of designconvenience.

This is the way to think about the gm/ID-based de-sign methodology. We basically characterize a singletransistor of width W . For this one device, we sweepthe gate voltage and measure the resulting values forgm, ID, Cgs and ro. Once we know the relationshipsbetween these parameters for the transistor of widthW , we can rely on linear scaling to determine thebehavior of a transistor of width W .

That is all there is to it. As long as everything scaleswith W , then the gm/ID methodology will hold. Ofcourse, we also know that these ratios are not perfect.Two transistors in parallel of widthW do not performexactly the same as one transistor of width 2W , butthey are within a few percent. Remember Fig. 4: weonly expect to get within 10-20% anyway, becausethe final tweaks will be done in Spice. And this ismuch closer than we can get trying to rely on thelong-channel model.

0.5 A Top-to-Bottom DesignExample

In the previous two sections, we have developed thegm/ID-based design methodology. Now I want to do

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Figure 22: Method of making design charts.

a complete design example so that you can see exactlyhow it is used.

0.5.1 Problem Description

You are tasked with creating a differential amplifierin a 0.18m process. The amplifier must have thefollowing characteristics:

1. Gain of 102. Bandwidth of 200MHz3. Drive a 1pF load

4. Be driven by a 300 source

5. Lowest possible power

0.5.2 Characterize the Technology

The first step is to characterize the technology target,which just means that we need to create some designand biasing charts (Note that, in this case, Figs. 16,19, and 20 were generated based on this technologytarget, so we will simply refer to them). The circitthat you will simulate in order to create these chartsis shown in Fig. 22.

In order to fill in the curves, you need to sweep thevoltage source while monitoring the transistor, andyou need to repeat that sweep for a variety of channellengths. Feel free to use the following (Hspice) linesto access the necessary internal transistor character-istics.

.probe gmid = par(gmo(m1)/i(m1))

.probe ft = par(gmo(m1)/(2*3.14*cggbo(m1)))

.probe gmro = par(gmo(m1)/gdso(m1))

.probe idw = par(i(m1)/w(m1))

Figure 23: Potential topology for our design example.

Using a plotting tool such as Matlab, you can thenread all these variables from the filename.SW0 filethat contains all the sweep data and create plots sim-ilar to Figs. 16, 19, and 20. Also, it will benefit youto consult these charts as we go along in order to getused to picking off the values.

0.5.3 Choose a Topology

Fig. 23 pictures a potential circuit that we can usefor this design. Will this topology work? We can bepretty confident that it will. According to Fig. 19,we might need a longer-than-minimum-length chan-nel and a gm/ID of at least 10 in order to makesure that intrinsic gain (which isnt extremely reli-able) is not the dominant gain determinant, but evenunder these conditions, Fig. 16 shows that we can stillachieve high fT .

Actually, the very first thing we can get out of the wayis L, because we have hard constraints on intrinsicgain. For example, we can choose L = 0.22m, whichwill keep the intrinsic gain around 50 (for moderatevalues of gm/ID), meaning that it will only have a20% effect on overall gain.

L = 0.22m

The next thing we can calculate is a value for R. Thisis a straightforward Signals-and-Systems calculation.Each resistor forms a pole with the 1pF capacitiveload, and we want that pole at 200MHz.

R =1

2pi C 200MHz = 800

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and knowing R, we can calculate the gm required toachieve a gain of 10.

gm =10R

= 12.5mS

Unfortunately, the 200MHz pole is not the only onein our system. Each 300 input resistor forms asecondary pole with Cgs, which can complicate thefrequency response if it lies in the vicinity of the200MHz pole. In order to keep this secondary polefrom affecting the frequency response, we can pushit to a higher frequency. For example, a 10 marginbeyond the dominant pole should allow our circuit tomaintain approximate single-pole behavior. This setsthe value for Cgs.

Cgs =1

2pi 300 2GHz = 265fF

Knowing gm and Cgs, we can calculate the transitfrequency

fT =12pi

gmCgs

=12pi

12.5mS265fF

= 7.5GHz

Now that we know L and fT , we have fixed the valuefor gm/ID. This can simply be read off the fT designchart.

gm/ID = 16.5mS/mA

And since we know both gm and gm/ID, we can de-termine ID

ID =gm

gm/ID=

12.516.5

0.76mA

Of course, our current source will need to deliver dou-ble this current because we need to power two tran-sistors. Finally, the very last step is to determinethe value of W that ensures that we operate at ourdesired transconductor efficiency of 16.5. Accordingto the biasing chart, a transconductor efficiency of16.5mS/mA and a length of 0.22m corresponds toa current density of 6.5A/m. So we can calculateW .

W =0.76mA6.5 Am

= 117m

The final design is shown in Fig. 24, and a Frequencyresponse plot is shown in Fig. 25. How do you think

Figure 24: Final version of our design example.

Figure 25: Performance of our design example.

we did? The gain is a little low. We were shootingfor 10 (20dB), but we only achieved about 8.5. Also,we did not quite hit 200MHz bandwidth. What hap-pened?

First of all, both shortcomings can be explained eas-ily. We expected to underachieve in gain because wedid not account for finite ro in the hand calculations.Remember we were working with an intrinsic gainof only about 50. We could have been a little moreconservative and maybe tried to overshoot the gaintarget by 20% or so. The shortcoming in bandwidthis easy to understand as well. First of all, CL is notthe only capacitive load we have to drive! In parallelwith CL is the transistor itself, which of course hassome drain capacitance. In addition, the secondarypole is only a factor of 10 above this pole. This makesits effect small, but still noticeable.

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The gm/ID-based design methodology actually didvery well. We know a few things that we mightwant to take into account if we performed anotherdesign iteration (we could estimate drain capacitancebased on W and include intrinsic gain limitations forstarters). But the methodology did correctly predictthe things that we should expect. For example, fromthe simulation output file, we can read off the actualvalues for gm and Cgs calculated by Hspice.

gm 12.6378mcgtot 264.2388f

As you can see, these are extremely close to the val-ues we requested. In other words, we do not haveanything to complain about regarding the methodol-ogy! The fact that we did not meet the design goals issimply our own fault. The methodology cannot makeup for obvious oversights in the design process. Westill need to consider things like Miller capacitance,drain capacitance, feedthrough, etc. But those areall things we can account for in Signals-and-Systemsanalyses. And now with the help of the gm/ID-basedmethodology, we can actually be confident that thesmall signal paremeters that we work with in Signals-and-Systems analyses will be correctly realized in thefinal design.

Finally, there are more sophisticated approaches youmay try. I have been presenting the gm/ID designdata in the form of charts, but there is no reasonwhy you could not import them as tables into your fa-vorite mathematics package. Once you can program-matically retrieve these data from lookup tables, youare free to employ all manner of design procedures.You could even wrap an optimization engine aroundeverything in order to maximize some particular per-formance parameter.

0.6 Conclusion

In conclusion, the gm/ID-based design methodologyis the best tool we have for linking small signal values,such as gm and fT , to physical parameters such asW , L, and Vgs. It encapsulate the gm vs. fT trade-offs compactly and predicts simulated performancevery accurately. In addition, it gives the designer anidea of the limitations of the technology target, whichhelps drive architectural decitions early in the designcycle. Finally, the data can be imported as tablesinto mathematics packages so that designers can usesohpisticated optimization routines, giving it all theadvantages of an equation-based approach, but yield-

ing much more accurate results.

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