A 60MHz 50W Fine-Grain Package-Integrated VR Powering … · A 60MHz 50W Fine-Grain...

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A 60MHz 50W Fine A 60MHz 50W Fine - - Grain Grain Package Package - - Integrated VR Integrated VR Powering a CPU from 3.3V Powering a CPU from 3.3V Gerhard Schrom, Fabrice Paillet, Jaehong Hahn Gerhard Schrom, Fabrice Paillet, Jaehong Hahn Circuit Research Lab, Intel Labs, Intel Corporation Circuit Research Lab, Intel Labs, Intel Corporation

Transcript of A 60MHz 50W Fine-Grain Package-Integrated VR Powering … · A 60MHz 50W Fine-Grain...

Page 1: A 60MHz 50W Fine-Grain Package-Integrated VR Powering … · A 60MHz 50W Fine-Grain Package-Integrated VR Powering a CPU from 3.3V Gerhard Schrom, Fabrice Paillet, Jaehong Hahn Circuit

A 60MHz 50W FineA 60MHz 50W Fine--Grain Grain PackagePackage--Integrated VRIntegrated VR

Powering a CPU from 3.3V Powering a CPU from 3.3V

Gerhard Schrom, Fabrice Paillet, Jaehong HahnGerhard Schrom, Fabrice Paillet, Jaehong Hahn

Circuit Research Lab, Intel Labs, Intel CorporationCircuit Research Lab, Intel Labs, Intel Corporation

Page 2: A 60MHz 50W Fine-Grain Package-Integrated VR Powering … · A 60MHz 50W Fine-Grain Package-Integrated VR Powering a CPU from 3.3V Gerhard Schrom, Fabrice Paillet, Jaehong Hahn Circuit

2 Intel LabsIntel Labs

MotivationMotivation

Reduce platform power delivery complexity & areaReduce platform power delivery complexity & area

Reduce load line & save powerReduce load line & save power

Enable fineEnable fine--grain power managementgrain power management

Example: Dell* XPS* M1210Example: Dell* XPS* M1210

Power delivery

top bottom

*Other names and brands may be claimed as the property of others*Other names and brands may be claimed as the property of others

Page 3: A 60MHz 50W Fine-Grain Package-Integrated VR Powering … · A 60MHz 50W Fine-Grain Package-Integrated VR Powering a CPU from 3.3V Gerhard Schrom, Fabrice Paillet, Jaehong Hahn Circuit

3 Intel LabsIntel Labs

PackagePackage--Integrated VRIntegrated VRProof of ConceptProof of Concept

Advantage of onAdvantage of on--package 2package 2ndnd VR stageVR stage

–– Single 3.3V input, lower current going into the packageSingle 3.3V input, lower current going into the package

–– 22--stage conversion is more efficientstage conversion is more efficient

–– NearNear--load VR allows fast response, reduced load lineload VR allows fast response, reduced load line

VR test chip on the CPU package (MCP)VR test chip on the CPU package (MCP)–– VR chip/w cascode bridges manufactured in 130nm CMOSVR chip/w cascode bridges manufactured in 130nm CMOS

–– 60MHz switching frequency allows miniaturization60MHz switching frequency allows miniaturization

–– Mounted on modified CPU package/w package trace inductorsMounted on modified CPU package/w package trace inductors

or powderedor powdered--iron core inductorsiron core inductors

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4 Intel LabsIntel Labs

PackagePackage--Integrated VR with Integrated VR with IntelIntel®® CoreCore™™2 Duo Processor2 Duo Processor

Vin=3.3V, Vout=0...1.6V (VID), 10MHz...100MHz, Vin=3.3V, Vout=0...1.6V (VID), 10MHz...100MHz, TDC=50A / 75A peak, size=37.6mmTDC=50A / 75A peak, size=37.6mm22, 130nm CMOS, 130nm CMOSInductors: 0508Inductors: 0508--size discrete powdered iron core or size discrete powdered iron core or packagepackage--trace air coretrace air core

discrete inductorsdiscrete inductorsCP

U

IVR

CPU

IVR

package trace inductorspackage trace inductors

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5 Intel LabsIntel Labs

Integrated VRIntegrated VRArchitectureArchitecture

Four voltage domains,Four voltage domains,16 phases (4x4)16 phases (4x4)

SingleSingle--output 16output 16--phasephasemode/w load balancingmode/w load balancing

Digital voltage controlDigital voltage control

Cascode bridges [*]Cascode bridges [*]

TypeType--3 compensator3 compensator

Progr. ramp rateProgr. ramp rate

Progr. load lineProgr. load line

Spread spectrum Spread spectrum EMI controlEMI control

VSNS0

VSNS1

VSNS2

VSNS3

GSNS2

GSNS3

GSNS1

GSNS0

XBR[0]

XBR[1]

XBR[2]

XBR[3]

XBR[4]

XBR[5]

XBR[6]

XBR[7]

XBR[8]

XBR[9]

XBR[10]

XBR[11]

XBR[12]

XBR[13]

XBR[14]

XBR[15]XCLK

XDPSLP

XPSI_B

XPWGD

XVRON

XVID[6]

XVID[5]

XVID[4]

XVID[3]

XVID[2]

XVID[1]

XVID[0]

VIN

GND

VID Decoder

1.65V Bandap Reference

Delay

PWGD0

VDA[7:0]

PWGD1

PWGD2

PWGD3

EN

VIN/2 LVR

1.65V LVR

1.65V LVR

ControlRegisters

2x Digital

Test Port2x Analog

Power ModeLUT

Spread SpectrumGenerator

8b DAC

compensator

PWM VRefVDA[7:0] +/- off.

UV

OV

Ramp Gen.

x0.8

x0.8

8b DAC

compensator

PWMVRefVDA[7:0] +/- off.

UV

OV

Ramp Gen.

x0.8

x0.8

8b DAC

compensator

PWM VRefVDA[7:0] +/- off.

UV

OV

Ramp Gen.

x0.8

x0.8

8b DAC

compensator

PWMVRefVDA[7:0] +/- off.

UV

OV

Ramp Gen.

x0.8

x0.8

FUNCTIONAL BLOCK DIAGRAM

[*] [*] G.SchromG.Schrom et al. APEC 2007et al. APEC 2007

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6 Intel LabsIntel Labs

Efficiency MeasurementsEfficiency Measurements

Package embedded air core inductors: 84.9% Package embedded air core inductors: 84.9% Discrete powdered Fe core inductors: 87.9% Discrete powdered Fe core inductors: 87.9% Load adaptive bridge activation improves by >10% Load adaptive bridge activation improves by >10%

70%

75%

80%

85%

90%

0 10 20 30 40 50 60 70 80Load Current [A]

Effic

ienc

y

100% activationload adaptive

70%

75%

80%

85%

90%

0 10 20 30 40 50 60 70 80Load Current [A]

Effic

ienc

y

100% activationload adaptive

Pkg. air core inductorsPkg. air core inductors 0508 pwdr Fe core inductors0508 pwdr Fe core inductors

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7 Intel LabsIntel Labs

Output Voltage Ramp RateOutput Voltage Ramp Rate

Fast output voltage ramp rate: >500mV/Fast output voltage ramp rate: >500mV/μμssTimeTime--domain finedomain fine--grain power management grain power management saves powersaves power

1µs

0.5V

1V

SpeedStep® Voltage Transitions

CRL Time

Perf

orm

ance

Time

Perf

orm

ance

demanddemandavailableavailablewastedwasted

low latency:low latency:less wasteless waste

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8 Intel LabsIntel Labs

Transient PerformanceTransient Performance

LoadLoad--line set to line set to ““00””

22ndnd droop: droop: reduced to 10mV reduced to 10mV

33rdrd droop: droop: eliminated eliminated

Reduced load lineReduced load linesaves powersaves power

Integrated VR

MBVR

3rd droop52mV

2nd droop29mV

10mV

2µs

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9 Intel LabsIntel Labs

Impedance MeasurementImpedance Measurement

Load line set to 0.5mLoad line set to 0.5mΩ, Ω, measured 0.42mmeasured 0.42mΩΩusing IFDIM method using IFDIM method [[A.WaizmanA.Waizman et al. EPEP 2004]et al. EPEP 2004]

0.000

0.002

0.004

0.006

0.008

0.010

0.012

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09Frequency [Hz]

Impe

danc

e [O

hm]

CPU/w package-integrated VR

CPU on std. package

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10 Intel LabsIntel Labs

EMI PerformanceEMI Performance

Laptop modified to use IVRLaptop modified to use IVR--powered CPUpowered CPUCISPR 22B test in 3m EMI chamber, EMC worstCISPR 22B test in 3m EMI chamber, EMC worst--casecaseCompliant with spreadCompliant with spread--spectrum enabledspectrum enabled

510

20

30

40

50

60EM

I Lev

el [d

BµV

/m]

30M 50M 70M 100M 200M 300M 500M 700M 1GFrequency [Hz]

FCC Limit

Laptop with IVR/w discrete ferrite inductorsLaptop with IVR/w package trace air-core inductorsUnmodified laptop

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11 Intel LabsIntel Labs

ConclusionConclusion

A highA high--performance packageperformance package--integrated VR integrated VR was demonstrated powering an was demonstrated powering an IntelIntel®® CoreCore™™2 Duo processor from 3.3V2 Duo processor from 3.3V

–– Peak efficiency of 85Peak efficiency of 85--88%88%

–– Fast slew rate of >500mV/Fast slew rate of >500mV/μμs s

–– Excellent droop & load line of <0.5mExcellent droop & load line of <0.5mΩΩ

A laptop modified to use the IVRA laptop modified to use the IVR--powered powered CPU booted successfullyCPU booted successfully

The power density at 50W is 11.8kW/inThe power density at 50W is 11.8kW/in33

Page 12: A 60MHz 50W Fine-Grain Package-Integrated VR Powering … · A 60MHz 50W Fine-Grain Package-Integrated VR Powering a CPU from 3.3V Gerhard Schrom, Fabrice Paillet, Jaehong Hahn Circuit