Nuclear Instruments and Methods in Physics Research A 659 (2011) 422–427

Contents lists available at SciVerse ScienceDirect

Nuclear Instruments and Methods inPhysics Research A

0168-90

doi:10.1

n Corr

E-m

journal homepage: www.elsevier.com/locate/nima

A 41 ps ASIC time-to-digital converter for physics experiments

Stefano Russo a,n, Nicola Petra b, Davide De Caro b, Giancarlo Barbarino a, Antonio G.M. Strollo b

a Department of Physics, University of Napoli ‘‘Federico II’’, Via Cintia Complesso Univ. Monte S. Angelo 80126, Naples, Italyb Department of Electronic Engineer, University of Napoli ‘‘Federico II’’, Via Caludio 21 80125, Naples, Italy

a r t i c l e i n f o

Article history:

Received 5 April 2011

Received in revised form

18 July 2011

Accepted 9 August 2011Available online 22 August 2011

Keywords:

TDC

ToF

Delay line

ASIC

02/$ - see front matter & 2011 Elsevier B.V. A

016/j.nima.2011.08.031

esponding author.

ail address: srusso@na.infn.it (S. Russo).

a b s t r a c t

We present a novel Time-to-Digital (TDC) converter for physics experiments. Proposed TDC is based on

a synchronous counter and an asynchronous fine interpolator. The fine part of the measurement is

obtained using NORA inverters that provide improved resolution. A prototype IC was fabricated in

180 nm CMOS technology. Experimental measurements show that proposed TDC features 41 ps

resolution associated with 0.35LSB differential non-linearity, 0.77LSB integral non-linearity and a

negligible single shot precision. The whole dynamic range is equal to 18 ms. The proposed TDC is

designed using a flash architecture that reduces dead time. Data reported in the paper show that our

design is well suited for present and future particle physics experiments.

& 2011 Elsevier B.V. All rights reserved.

1. Introduction

Time measurements, with very high precision, are required in awide range of physics experiments; for this reason Time-to-digitalconverters (TDC) are very useful instruments for this kind ofscience. A TDC measures a time and provides a digital representa-tion of the measurement result.

In the high energy physics TDCs are, for example, used forparticle identification in Time of Flight (ToF) systems. In thesedetectors particle’s energy is determined measuring the timeneeded to cross a specified distance. Hence the time-measurementprecision is directly connected to particle’s energy measurement.Many present and future experiments use this kind of technology.A few examples follow. The next Compressed Barionic Matter(CBM) experiment at GSI [1] will make hadron identificationsusing a ToF based on RPC concept. The time-to-digital converterhas to handle a 100 kHz event rate with a double hit resolutionbetter than 5 ns. In the NA62 experiment at CERN [2] severalsub-detectors will provide the measurement of the crossing timefor each particle, to be exploited for both off-line data analysis andthe definition of trigger primitives. For this purpose a TDC with a100 ps resolution on a 20 ns dynamic is needed [3].

Timing measurement are also widely used in the astroparticlephysics experiments in space. One of the most important subdetectors of PAMELA (Payload for Antimatter Matter Explorationand Light nuclei Astrophysics) experiment [4], a space borntelescope launched in 2006, is a Time of Flight system [5]. Since

ll rights reserved.

the PAMELA telescope is mounted on a satellite, it has to be verycompact and hence the total length of the ToF detector is about0.8 m. With such a small distance, to discriminate electrons toantiprotons up to 2 GeV, the total detector time resolution has tobe less than 200 ps. As usual in this kind of experiments, theelectronics has to give a negligible contribution to the totaluncertainty, so the TDC itself has a resolution of 50 ps [6].

The Time of Flight method is also widely used in the PositronEmission Tomography (PET) scanners where the time resolutionis directly connected to the signal-to-noise ratio of the recon-structed image. In this field a huge effort is dedicated to enhancelight detection timing performance. Recent studies show that,with new scintillator’s materials and Silicon PhotomultplierTubes, 100 ps coincidence resolving time is reachable [7]. Withthis figure a very high precision timing measurement is needed.

In this paper we present a new Time-to-Digital converterarchitecture able to reach a very high time resolution associatedwith a low power consumption. The proposed TDC is also verysimple to implement and is based on a flash architecture thatallows to obtain measurements with reduced dead time. Thesefeatures make that scheme suitable for a wide range of physicsexperiments. The paper is organized as follows. In Section 2 thedeveloped TDC architecture is described and its benefits arehighlighted. Section 3 discusses the experimental measurementsof the TDC’s parameters. Conclusions are carried out in Section 4.

2. TDC architecture

Fig. 1 shows the architecture of the proposed TDC. It measuresthe delay between the Start and Stop signals. When the Start

D Q D QD Q

Start

Stop

synchronouscounter

StartStop

N P P

Fig. 1. Proposed TDC architecture.

0 0.5 1 1.5

0

1

2

ns

0 0.5 1 1.5ns

0 0.5 1 1.5ns

tratSS

OM

CA

RO

N

0

1

2

0

1

2

1.17 ns

0.77 ns

3rd inverter 37th inverter

Fig. 2. NORA vs. CMOS comparison.

PreN

EnN

EnP

PreP

InputN

InputP

OutputN

OutputP

N

P

Fig. 3. NORA logic inverters.

Table 1Relation between the status of the ith inverter and the status of the iþkth inverter.

k is a design parameter.

Global (iþk)th inverter ith inverter

Reset OutputN OutputP Status PreP PreN EnP EnN

Vdd – – Precharge Vdd 0 Vdd 0

0 0 Vdd Precharge Vdd 0 Vdd 0

0 Vdd 0 Enabled 0 Vdd 0 Vdd

S. Russo et al. / Nuclear Instruments and Methods in Physics Research A 659 (2011) 422–427 423

signal goes high the inverters act as a free running ring oscillator.The periodic signal at the output of the final inverter can be usedas the clock of the synchronous counter reported in the figure. Assoon as the Stop signal goes high the counter is disabled and itsvalue represents a coarse estimate of the delay between Start andStop. At the same time flip-flops latch the inverters state. Fromthis data pattern the measure’s fine part can be calculated.

The TDC dynamic range depends on the synchronous counterlength. On the other hand, the resolution is equal to the singleinverter delay. In order to improve the resolution with respect toTDCs based on standard CMOS inverters we propose the use ofNORA [8] logic. NORA is a dynamic logic that allows to implementfast circuits reducing the capacitive load on the logic signals.A preliminary analysis to evaluate the advantage of NORA logicagainst the CMOS logic was carried out. We implemented twodelay lines in UMC 180 nm technology: the first based on theCMOS logic and the second using the NORA logic. In both casesthe inverters were designed in order to exhibit minimum area.Simulation results are reported in Fig. 2. During this test the sameSTART signal was fed into both delay lines.

The figure reports the waveform at the output of the 3rd andthe 37th inverter of both the CMOS and the NORA delay lines. Ascan be seen, the NORA logic allows reducing the delay by 34%.

In the NORA logic two inverters types exist, as shown in Fig. 3.The n-type inverter pulls down the output (OutputN) when itsinput goes high (InputN). The p-type inverter pulls up the output(OutputP) when its input goes low (InputP). Hence the OutputP canbe used to drive the InputN of the subsequent inverter (see Fig. 1)whereas the OutputN can be used to drive the InputP of thesubsequent inverter.

As shown in Fig. 3 the two NORA inverters need to beprecharged and enabled [8] through the signals PreP, PreN, EnP

and EnN. When the NORA inverters are precharged (PreP¼Vdd,PreN¼0, EnP¼Vdd, EnN¼0) they exhibit a fixed output (Out-

putP¼0, OutputN¼Vdd). When the NORA inverters are enabled

(EnP¼0, EnN¼Vdd, PreP¼0, PreN¼Vdd) they let the Start signalpropagate through the ring.

In signal processing circuits the precharging and enablingsignals are obtained as the two phases of the clock signal.However, in order to use the NORA inverters within a ringstructure the precharging and enabling signals must be handledin an asynchronous way.

For this reason in our design each inverter is precharged orenabled depending on the status of another inverter positionedahead along the ring and on a Global Reset signal. When theGlobal Reset is high, the whole ring is reset. When the GlobalReset is low the inverters are enabled and the Start signal canpropagate through the ring. Once the Start signal has gonethrough kþ1 inverters (k is a design parameter) the first invertercan be precharged again to its initial status. Once the Start signalhas reached the (2kþ1)th inverter, the kþ1th inverter can beprecharged, while the first inverter can be enabled. When theStart signal completes the propagation through the ring it returnsback to the input of the first inverter, which has been prechargedand is in the enabled state. In general, the values of the signalsPreP, PreN, EnN and EnP of the generic ith inverter, can becomputed as a boolean function of the outputs OutputP andOutputN of the (iþk)th inverter according to the truth tablereported in Table 1.

As an example Fig. 4 shows a possible connections for theprecharge signals among the ith, iþkth and the iþ2kth inverters.In the figure k is assumed to be odd so that a n-type inverter isresponsible for the precharge of the p-type inverter. As can beseen, when the iþkth inverter switches ðOutputNiþk ¼ 0Þ, the ithinverter is precharged through the signal PrePi. On the other hand,when the iþ2kth inverter switches ðOutputPiþ2k ¼ VddÞ, the iþkthinverter is precharged through the signal PreNiþk. Once the signalOutputNiþk has been pulled-up the precharge of the ith inverter isstopped (through the signal PrePi) and this same inverter isenabled through the signal EnPi.

PreNi+k

GpreOutputPi+k-1

OutputNi+k

EnNi+k

EnPi+2k

OutputP i+2k

PrePi+2k

Gpre

PrePi

PreNi+k

Gpre

EnPi

OutputPiPrePi

PreNi-k

PrePi

Global Reset GpreGpre

Stop Stop

Stop

Fig. 4. Example of the precharge connections among the inverters.

PreN

EnN

InputN

OutputN

Start

Fig. 5. Topology of the first inverter of the ring.

Fig. 6. Chip micrograph.

S. Russo et al. / Nuclear Instruments and Methods in Physics Research A 659 (2011) 422–427424

It is worth pointing out that the capacitive load on the net PrePi

can be very large since this wire connects two distant inverters.However the parasitic load of this net does not influence the delayof the inverters thanks to the decoupling effect of the NAND gate.In a similar way the delay of the p-type inverter is decoupled bythe capacitive load of the net PreN thanks to the NOR gate.

The first inverter of the ring (colored in grey in Fig. 1) is theonly one connected to the Start signal and is implemented asshown in Fig. 5. The MOSFET with the Start signal on its gate isused to start the ring. This is the only difference with respect tothe n-type inverter of Fig. 3. In terms of non-linearity, the onlyeffect of the added MOSFET is a little increase in the capacitiveload on the nodes OutputN of the first inverter.

3. Test bench and measurements

We have fabricated an IC prototype to test the achievableperformance of the proposed architecture using a 180 nm CMOStechnology. Fig. 6 shows the chip micrograph. The prototypecomprises two TDCs (TDC1 and 2 in Fig. 6). The two TDCs areidentical. Both feature a free running oscillator composed by 54inverters and a synchronous counter of 13 bits.

TDC1 is controlled by a sequential synchronous logic. The logicis used to assert the Global Reset signal and to accumulate thevalue measured by the TDC. Hence, in case of a repetitive timemeasurement, the accumulator allows to obtain a mean value ofthe required measure.

The TDC1 measures the clock period used by the synchronouslogic. Furthermore, through the logic, it is possible to set the TDC1in order to measure a multiple of the clock period. For a fixedclock period, different values measured by TDC1 imply a changeof the inverter’s delay, which can happen due to temperature and

voltage variations. As a consequence, the TDC1 can be used totrack voltage and temperature variations and to correct themeasurement of the TDC2 accordingly.

On the other hand the TDC2 is directly controlled by theexternal pads. It is used to measure a user-defined time interval.

For both TDCs, a decoder translates the value latched by theflip-flops in Fig. 1 to an integer value. A multiplier-and-add unit isused to obtain the final result of the measure as a multiple of thedelay of one inverter.

The fabricated chip has been tested with the aid of a customrealized test board (see Fig. 7). Two different lines are used todrive the I/O and CORE power. A socket allows the connection ofdifferent chips to the board. Several external digital connectorsare used to probe all the significant signals.

The 81134A pulse pattern generator from Agilent generatesthe timing intervals to be measured, the TLA721 logic analyzer byTektronix acquires the digital outputs of the circuit whereas theTLA 7PG2 pattern generator is used to drive the digital inputs.

In order to characterize the TDC, TDC2 was used to extract thecharacteristic and TDC1 to check that no power and temperaturedrift occurred during the measurement. Using the pulse patterngenerator we have progressively increased the measured time insteps of 5 ps. Four measures have been taken at each step. Themean value of each set of measurements has been used to buildthe characteristic. The TDC exhibits a resolution of 41 ps. Pleasenote that, since the measurement’s step is 5 ps and since fourmeasurements per point have been taken, one tap of the delay

Fig. 7. Test board.

11 11.5 12 12.5 130

20

40

60

measured time (ns)

fine

inte

rpol

ator

out

put

Fig. 8. TDC characteristic.

0 10 20 30 40 50 60-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

fine interpolator output

)BS

L(L

ND

Fig. 9. TDC differential non-linearity.

0 10 20 30 40 50 60-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

fine interpolator output

INL

(L

SB)

Fig. 10. TDC integral non-linearity.

S. Russo et al. / Nuclear Instruments and Methods in Physics Research A 659 (2011) 422–427 425

line has been described with eight points obtained by 32 mea-surements. Fig. 8 shows a part of the entire characteristic thatcovers the whole delay of all the inverters in the ring of Fig. 1.X-axis reports the measured time (ranging from about 11 ns toabout 13 ns) while the Y-axis reports the position in the ring ofthe last switched inverter.

Starting from these results the integral non-linearity (INL) anddifferential non-linearity (DNL) have been computed. As shown inFig. 9 the maximum DNL is as low as 0.35LSB. Furthermore itsvalue is well distributed around zero. As a consequence the INL(Fig. 10) has a value of 0.77LSB.

Beside non-linearity the measurement’s accuracy depends onthe single-shot precision. Some TDCs can give different results

when the same time value is measured repeatedly. The reason isthat the TDC intrinsic jitter might be larger than the LSB. Thisphenomenon is frequent in Vernier-based TDCs or TDCs based ontime expansion, where the time amplification can be non-con-stant and a measurement jitter can be added. However the meanoperation used to extract the non-linearity of the TDC can hidesuch measurement jitter. In order to compute the single-shotprecision for the proposed TDC we have repeated the measure offive time values about 2000 times. The values we analyzed are5 ns, 10 ns, 20 ns, 40 ns and 60 ns and for each measured value anhistogram was plotted. As shown in Fig. 11(a) for 5 ns time valuethe most frequent result is 120. Only 41 measurements returned adifferent result (119, 1LSB error). The standard deviation, in thiscase is as low as 0.02LSB. For the measured time 10 ns (Fig. 11(b))the value 240 has been returned by the TDC the most of the times,while 168 times the result has been 239. In this case the standarddeviation is as low as 0.07LSB. The measurement of 20 ns and40 ns (Fig. 11(c) and (d)) exhibits a standard deviation equal tozero (all the measurements have given the same result). Finallythe measurement of 60 ns (Fig. 12) results equal to 370 tapsalways but in one single case.

The analysis reported in Figs. 11 and 12 demonstrates that ourTDC jitter does not worsen the measurement accuracy and thatthe TDC LSB (41 ps) is equal to its resolution.

Another important parameter is the measurement’s tempera-ture stability. Temperature can change the delay of each delayelement and, hence, the TDC characteristic. To test this kind of

117 118 119 120 121 122 1230

200

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600

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1000

1200

1400

1600

1800

2000

result of the measure

num

ber

of h

itsnu

mbe

r of

hits

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of h

itsnu

mbe

r of

hits

5ns

41 hits

237 238 239 240 241 242 2430

200

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1400

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10ns

168 hits

467 468 469 470 471 472 4730

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20ns

929 930 931 932 933 934 9350

200

400

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1000

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1400

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result of the measure

40ns

Fig. 11. single shot precision analysis. Histogram of the results obtained measuring 5 ns (a), 10 ns (b), 20 ns (c) and 40 ns (d).

367 368 369 370 371 372 3730

200

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600

800

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1200

result of the measure

num

ber

of h

its

60ns

1 hit

Fig. 12. Histogram of the results obtained measuring 60 ns.

0 10ns 20ns 30ns 40ns 50ns 60ns 70ns0

500

1000

1500

measured time

taps

Fig. 13. Results of the single-shot precision analysis made in two different

moments. The squares and the circles correspond to the mean values reported

by the TDC for a given measured time.

S. Russo et al. / Nuclear Instruments and Methods in Physics Research A 659 (2011) 422–427426

effect on our chip we have repeated the measure of 5 ns, 10 ns,20 ns, 40 ns and 60 ns several hours after the measurementsreported in Figs. 11 and 12. Fig. 13 compares the results achievedin the two cases.

The temperature variation introduce a very small drift in thecharacteristic slope that can be seen only when larger time valuesare measured. The measured relative error is as low as 0.5%.

Despite this error could be considered negligible in most of theTDC applications our architecture is able to track this variation bymeans of the two delay lines. Measuring a known delay with oneTDC, PVT variations can be tracked and used to correct the resultsof the second TDC. Several algorithms can be used offline toachieve compensations.

The overall dynamic range can be evaluated as 41 ps�54 taps� 213C18 ms. In principle the dynamic range can beincreased by increasing the number of bits of the counter.

However the counter must be fast enough to commutate at thespeed of the free running ring oscillator ð � 5oo MHz in ourdesign) that feeds the clock signal for the counter. As a conse-quence the number of bits of the counter is limited.

During the tests the power dissipation has been measured andthe core power consumption was estimated as 25 mW.

The TDC performance is summarized in Table 2. As can be seenthe proposed TDC, while exhibiting good resolution, is able tomeasure a wide time intervals range. The low power dissipation,the non-linearities below 1LSB and the very good temperaturestability make the proposed TDC a good candidate to be used inphysics experiments.

TDC performance can be better evaluated comparing them withnowadays physics experiment requirements. For that purpose we

Table 2Summary of TDC performance.

Technology Resolution Range Area Power INL DNL

180 nm 41 ps 18 ms 0.09 mm2 25 mW 0.77LSB 0.35LSB

Table 3Impact of the proposed TDC accuracy on present and future experiments.

Experiment Total detector

resolution

Error component using proposed

TDC (%)

NA62 [2] 20 ns 0.2

CBM [9] 5 ns 0.82

PAMELA [4] 200 ps 20.5

future PET

detectors [7]

100 ps 41

S. Russo et al. / Nuclear Instruments and Methods in Physics Research A 659 (2011) 422–427 427

have estimated the impact on the measurement error that theproposed TDC could add in present and future particle detectors.With reference to the experiments cited in the introduction, wehave imagined to use the proposed TDC within those detectors.Starting from the declared target resolution, we have estimated thecontribution added by our TDC on the overall uncertainty. Asreported in Table 3 for some experiments (e.g. [9,2]) the resolutionof the proposed TDC adds a negligible error contribution. For thesekinds of experiments cheaper and less accurate TDCs could be alsoused. However in some experiments the critical environmentalconditions call for an extremely accurate time measure. Forinstance ToF systems in satellite born particle experiments (e.g.[4]) are based on the measure of the time needed by a particle tocross a very small distance. Hence the time to be measured is verysmall, which, in turns, calls for a very accurate TDC. New high-speed detectors will allow the design of future ToF systems withvery stringent requirements for the time measurement. As anexample in the [7] a 100 ps detector resolution is claimed. In orderto avoid introducing a large error contribution a TDC with morethan 50 ps is not an option.

Beside resolution, an important feature of the proposed TDC isits reduced dead time. For several high accuracy TDCs based on

Vernier-like techniques the dead time is quite large due to thetime needed to compute the result after the measurement. Deadtimes of few milliseconds are typical for this kind of detectors.The dead time impacts on the time needed to accumulatestatistically relevant data. On the other hand, the proposed TDCallows to achieve great accuracy while requiring a measurementtime which is very close to the measured time. Once the Stopsignal is asserted, the circuit computes the result in the timeneeded to latch the status of the NORA inverters. Hence the deadtime is negligible. An overall dead time of a few nanoseconds wasmeasured in our tests.

4. Conclusion

We present a TDC based on a novel architecture. The proposedcircuit uses NORA inverters in order to achieve good accuracy.Measurement speed is another important feature of proposedTDC which exhibits the reduced dead time of the flash architec-tures. Experimental results are reported in the paper. The fabri-cated IC is a good candidate for physics experiments since it joinsa 41 ps resolution on 18 ms measurement range with 0.8LSBintegral non-linearity.

References

[1] CMB collaboration, Compressed Baryonic Matter Experiment—Technical Sta-tus Report, 2005, /http://www.gsi.de/onTEAM/dokumente/public/DOC-2005-Feb-447.htmlS.

[2] NA62 collaboration, NA62 proposal. CERN-SPSC-2005-013 SPSC-P-236, 2005.[3] G. Collazuol, et al., A Pixel Front-End ASIC in 0:13 mm CMOS for the NA62

Experiment with on Pixel 100 ps Time-to-Digital Converter, in: IEEE NuclearScience Symposium Conference Record, 2009.

[4] P. Picozza, et al., PAMELA—A Payload for Antimatter Matter Exploration andLight-nuclei Astrophysics, astro-ph/0608697/v2. 2007.

[5] G. Barbarino, et al., Nuclear Instruments and Methods, Section A 584 (2008)319.

[6] G. Osteria, S. Russo, Nuclear Instruments and Methods, Section A 589 (2008)465.

[7] D. Schaart, et al., Physics in Medicine and Biology 55 (2010) N179.[8] N.F. Goncalves, H. De Man, IEEE Journal of Solid-State Circuits 18 (3) (1983)

261.[9] H. Flemming, H. Deppe, The GSI Event-Driven TDC with 4 Channels GET4, in:

IEEE Nuclear Science Symposium Conference Record, 2009.