A 300-mm Wafer-Level Three-Dimensional Integration...

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A 300-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hybrid Cu-Adhesive Bonding F. Liu 1 , R. R. Yu 1 , A. M. Young 1 , J. P. Doyle 1 , X. Wang 2 , L. Shi 1 , K.-N. Chen 1 , X. Li 2 , D. A. Dipaola 2 , D. Brown 2 , C. T. Ryan 2 , J. A. Hagan 2 , K. H. Wong 2 , M. Lu 1 , X. Gu 1 , N. R. Klymko 2 , E. D. Perfecto 2 , A. G. Merryman 2 , K. A. Kelly 2 , S. Purushothaman 1 , S. J. Koester 1 , R. Wisnieff 1 , and W. Haensch 1 1 IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, USA 2 IBM Semiconductor Research and Development Center, 2070 Route 52, Hopewell Junction, NY 12533, USA Phone: 1-914-945-2234 Email: [email protected] Abstract A 300-mm wafer-level three-dimensional integration (3DI) process using tungsten (W) through-silicon vias (TSVs) and hybrid Cu/adhesive wafer bonding is demonstrated. The W TSVs have fine pitch (5 μm), small critical dimension (1.5 μm), and high aspect ratio (17:1). A hybrid Cu/adhesive bonding approach, also called transfer-join (TJ) method, is used to interconnect the TSVs to a Cu BEOL in a bottom wafer. The process also features thinning of the top wafer to 20 μm and a Cu backside BEOL on the thinned top wafer. The electrical and physical properties of the TSVs and bonded interconnect are presented and show RLC values that satisfy both the power delivery and high-speed signaling requirements for high-performance 3D systems. Introduction 3DI is a promising technology to further improve the performance of computational systems [1-3]. 3DI enables increased functions per physical die area, and can dramatically increase the available cache memory in multi- core architectures. Previously, W TSVs for silicon carrier applications have been demonstrated with both high yield and reliability [4]. In addition, a hybrid metal/adhesive TJ process has been shown to be a highly reliable inter-chip connection process in multi-chip modules [5]. However, neither of these technologies has been demonstrated in a full integrated process on a 300-mm platform. In this paper, we utilize the combination of W TSVs and transfer-join assembly on 300- mm wafers, and demonstrate the functionality and robustness of this process. Process Description Fig. 1 presents the integration flow of our 3D wafer-level process. After W TSV formation, insulation and Cu studs are formed on the top wafer, followed by a planarized deposition of a polymer adhesive. The bottom wafer utilizes Cu pads with recessed dielectric openings. The wafers are then aligned and bonded in vacuum using a Cu-Cu thermocompression process. After bonding, the top wafer is thinned, and backside Cu metallization is patterned. The TSVs are formed by continuous duty reactive ion etching (RIE) and have 25 μm depth and 17:1 aspect ratio. The TSVs are rectangular with area of 1.5 μm x 6 μm. Fig. 2 summarizes the TSV etch depth as a function of TSV width at the center and edge of a wafer. At fixed via width, a cross- wafer depth variation of less than 0.8 μm is achieved. The TSVs use thermal SiO 2 and high density plasma (HDP) oxide as the insulating liner, and chemical vapor deposition (CVD) W metal which has good fill characteristics as shown in Fig. 3. Strain values of ~0.1% are measured between a TSV array Fig. 1. Schematic diagram of 3D process flow. (a) Top/Bottom Wafers (b) Bonding (d) Backside Top wafer Bottom wafer (c) Thinning Top wafer Bottom wafer Top wafer Bottom wafer Top wafer Bottom wafer Cu Adhesive Cu Cu W Fig. 2. Plot of TSV etch depth vs. TSV width for center (solid red squares) and edge (empty blue dots) dies on a 300-mm wafer. For a fixed width, the center to edge variation is less than 0.8 μm. 0.0 0.5 1.0 1.5 2.0 15 20 25 30 TSVs at wafer edge TSVs at wafer center TSV depth (μm) TSV width (μm)

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Page 1: A 300-mm Wafer-Level Three-Dimensional Integration ...people.ece.umn.edu/users/skoester/04796762.pdfA 300-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through-Silicon

A 300-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hybrid Cu-Adhesive Bonding

F. Liu 1, R. R. Yu 1, A. M. Young 1, J. P. Doyle 1, X. Wang 2, L. Shi 1, K.-N. Chen 1, X. Li 2, D. A. Dipaola 2, D. Brown 2, C. T. Ryan 2, J. A. Hagan 2, K. H. Wong 2, M. Lu 1, X. Gu 1, N. R. Klymko 2, E. D. Perfecto 2, A. G.

Merryman 2, K. A. Kelly 2, S. Purushothaman 1, S. J. Koester 1, R. Wisnieff 1, and W. Haensch 1 1 IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, USA

2 IBM Semiconductor Research and Development Center, 2070 Route 52, Hopewell Junction, NY 12533, USA Phone: 1-914-945-2234 Email: [email protected]

Abstract A 300-mm wafer-level three-dimensional integration

(3DI) process using tungsten (W) through-silicon vias (TSVs) and hybrid Cu/adhesive wafer bonding is demonstrated. The W TSVs have fine pitch (5 μm), small critical dimension (1.5 μm), and high aspect ratio (17:1). A hybrid Cu/adhesive bonding approach, also called transfer-join (TJ) method, is used to interconnect the TSVs to a Cu BEOL in a bottom wafer. The process also features thinning of the top wafer to 20 μm and a Cu backside BEOL on the thinned top wafer. The electrical and physical properties of the TSVs and bonded interconnect are presented and show RLC values that satisfy both the power delivery and high-speed signaling requirements for high-performance 3D systems.

Introduction

3DI is a promising technology to further improve the performance of computational systems [1-3]. 3DI enables increased functions per physical die area, and can dramatically increase the available cache memory in multi-core architectures. Previously, W TSVs for silicon carrier applications have been demonstrated with both high yield and reliability [4]. In addition, a hybrid metal/adhesive TJ process has been shown to be a highly reliable inter-chip connection process in multi-chip modules [5]. However, neither of these technologies has been demonstrated in a full integrated process on a 300-mm platform. In this paper, we utilize the combination of W TSVs and transfer-join assembly on 300-mm wafers, and demonstrate the functionality and robustness of this process.

Process Description

Fig. 1 presents the integration flow of our 3D wafer-level process. After W TSV formation, insulation and Cu studs are formed on the top wafer, followed by a planarized deposition of a polymer adhesive. The bottom wafer utilizes Cu pads with recessed dielectric openings. The wafers are then aligned and bonded in vacuum using a Cu-Cu thermocompression process. After bonding, the top wafer is thinned, and backside Cu metallization is patterned.

The TSVs are formed by continuous duty reactive ion etching (RIE) and have 25 μm depth and 17:1 aspect ratio. The TSVs are rectangular with area of 1.5 μm x 6 μm. Fig. 2 summarizes the TSV etch depth as a function of TSV width at the center and edge of a wafer. At fixed via width, a cross-wafer depth variation of less than 0.8 μm is achieved. The

TSVs use thermal SiO2 and high density plasma (HDP) oxide as the insulating liner, and chemical vapor deposition (CVD) W metal which has good fill characteristics as shown in Fig. 3. Strain values of ~0.1% are measured between a TSV array

Fig. 1. Schematic diagram of 3D process flow.

(a) Top/Bottom Wafers (b) Bonding

(d) Backside

Top wafer

Bottom wafer

(c) Thinning

Top wafer

Bottom wafer

Top wafer

Bottom wafer

Top wafer

Bottom wafer

Cu Adhesive Cu

Cu

W

Fig. 2. Plot of TSV etch depth vs. TSV width for center (solid red squares) and edge (empty blue dots) dies on a 300-mm wafer. For a fixed width, the center to edge variation is less than 0.8 μm.

0.0 0.5 1.0 1.5 2.015

20

25

30 TSVs at wafer edge TSVs at wafer center

TSV

dept

h (μ

m)

TSV width (μm)

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of 5-μm-pitch using UV Raman spectroscopy with a penetration depth of 10 nm (Fig. 4). The metallization on top of the W vias consists of square Cu capture pads and circular studs fabricated using standard Cu BEOL processes. The bonding pad on the bottom wafer is made such that the top of the Cu metallization is below the oxide surface (see Fig. 1(a)).

A variation of the TJ adhesive/metal hybrid bonding method [5] has been utilized to bond the wafers and interconnect the TSVs. The TJ bonding technique involves the use of mechanical lock-and-key structures with metal/adhesive hybrid bonding to create a 3D interconnect suitable for fine pitch chip-chip, chip-wafer and wafer-wafer connections. In our process, a layer of polyimide adhesive is coated onto the top wafer. A timed blanket RIE removes polyimide at the top of Cu studs. Next, the top wafer is aligned face-to-face with the bottom wafer using an IR imaging system. The top-wafer studs fit inside the oxide recesses in the bottom wafer, forming lock-and-key structures.

The wafer bonding is performed in vacuum under isostatic pressure. An important feature of this process is that the lock-and-key structures safeguard the wafer pair from lateral shifts during bonding. Post bonding alignment accuracy is observed to be within 2 μm across the entire 300-mm wafer. Fig. 5 shows a cross-sectional SEM of a typical Cu stud and capture pad before and after bonding. The structural effect of the Cu-Cu thermocompression process is clearly observed. Subsequent characterization of the bonding interface by scanning acoustic microscopy showed no apparent macroscopic bonding defects in both orthogonal zigzag 80-

Fig. 3. SEM image of high aspect ratio TSVs (AR: 17:1). The TSVs utilize oxide liner and CVD tungsten.

5μm

Fig. 4. Lateral strain profile of Si regions near W TSVs as determined by UV (λ=325 nm) micro-Raman spectroscopy. Regions within ~ 1 μm of TSVs show 0.1% tensile strain, while compressive strain is observed in field regions.

Length Y (µm)

20 30 40 50

x10 -3

1.5

1.0

0.5

0.0

-0.5

-1.0

-1.5

% Strain from Raman shift

20 25 30 35 40 45

Length X (µm)

Strain (%)

5μm

20 30 40 50

-0.1

0

0.1

Length (μm)

Fig. 5. SEM cross-section of a TJ structure before and after bonding. A lock-and-key structure is formed using a matched stud (top wafer) and a recess (bottom wafer). Polyimide material fills in regions between the wafers. The thermo-compression effect on the bonding structure is apparent.

Fig. 6. High resolution scanning acoustic images of a portion of an 80-μm-pitch 3D via chain (a) and of a 28.8-μm-pitch 3D via chain (b). The uniformly distributed bright spots (Cu joining) and dark areas (adhesive bonding) indicate a good TJ joining interface with no macroscopic defects detectable.

Cu stud Cu capture pad

Bondinginterface

Si

5μm

PolyimideBottom wafer recess SiO2

Before bonding

After bonding

Cu stud Cu capture pad

Top wafer

Top wafer

Bottom wafer

250μm (a) (b)

Bottom wafer metallization

50μm20μm

Top wafer metallization

200μm

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μm-pitch via chains (Fig. 6(a)) and linear 28.8-μm-pitch via chains (Fig. 6(b)).

After bonding, the backside of the top wafer is ground and chem-mechanical polished (CMP) to a thickness of approximately 40 μm. Five-point thickness measurements of the post-CMP bonded pair indicated a wafer thickness standard deviation to be 3 μm, and no pronounced global dishing. The topside of the bonded pair is further RIE trimmed down to 20 μm to expose the TSVs. An AFM scan

of the trimmed surface is shown in Fig. 7, which indicates an RMS roughness of 25 nm. As shown in Fig. 8, the TSVs have a notably different appearance on the backside of the wafer as compared to the front. A photograph of a completed 300-mm 3DI wafer after depositing and patterning of the backside Cu BEOL metallization is shown in Fig. 9.

Results

Electrical characterization has been carried out on the completed 3D via chains. The dotted blue line in the inset of Fig. 10 shows a typical I-V curve recorded on an 80-μm-pitch via chain (shown in Fig. 6(a)) with 1032 connecting nodes. The patterned bars in Fig. 10 shows a histogram of the resistance per node of the connected 80-μm-pitch via chains on an entire 300-mm wafer. The average resistance per node is extracted to be 1.0 Ω, where each node consists of banks of 8 TSVs. The resistance variation is attributed to differences in the TSV protrusion height across the wafer (Fig. 11). After extracting the resistance of the interconnecting metal and the resistance of the via to the backside metallization, the intrinsic via and bonded interface resistance is determined to be ~ 0.1 Ω, indicating that a considerable portion of the total node resistance is due to the excess protrusion of the via from the backside of the top wafer. To minimize the TSV protrusion, a mechanical knock-off was utilized to approximately level the vias with the backside wafer surface. The knock-off process reduced the average node resistance for 80-μm-pitch via chains from 1.0 to 0.8 Ω, as illustrated by both the I-V curves and the node resistance distribution histograms shown in Fig. 10.

0 10 20 300

10

20

30

X distance (μm)

Y di

stan

ce (μ

m)

Fig. 7. AFM scan of a region of a 300-mm wafer after grinding, polishing and RIE trimming down to 20 μm. The RMS roughness is 25 nm.

Fig. 8. Top-down images of a bank of eight W TSVs from (a) the front side of the top wafer, and (b) from the back side of the top wafer after polishing and RIE trimming.

5μm (a) 5μm(b)

Fig. 9. Photograph of a completed 300-mm 3DI wafer.

0.6 0.8 1.0 1.2 1.4 1.6 1.80.0

0.1

0.2

0.3

0.4

Resistance per node (Ohm)Prob

abili

ty h

isto

gram

(%)

Fig. 10. Histogram of node resistance of 80-μm-pitch 3D via chains of 1032 nodes without backside knock-off process (patterned blue bars) and with backside knock-off process (solid red bars). Inset: I-V curve of a typical 80-μm-pitch via chain with (solid red line) and without (dotted blue line) backside knock-off process.

-1.0 -0.5 0.0 0.5 1.0

-1.0

-0.5

0.0

0.5

1.0

w/o knock-offR=1020Ω

with knock-offR=805Ω

Cur

rent

(mA

)

Voltage (V)

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The inset of Fig. 12 is a typical I-V curve recorded on a 28.8-μm-pitch via chain (shown in Fig. 6(b)) of 2724 connecting nodes with backside knock-off process. Fig. 12 shows a linear relationship between the resistance of the via chain and the number of connecting nodes. The resistance per node is extracted to be 0.51 Ω, where each node consists of

banks of 2 TSVs. The yielding of the tighter-pitch via chains demonstrates the scalability of our W TSV, hybrid Cu-adhesive bonding process.

The measured and simulated RLC parameters for our 3D technology have been compared with the system-level requirements. The TSVs provide an areal conductivity of 2.5*10-2 Ω-1μm-2, and have calculated capacitance and inductance values of 3 fF and 13 pH. As shown in Table 1, these values meet the power delivery and interlayer signaling requirements anticipated for high-performance 3D systems.

Conclusion A general-purpose CMOS-compatible 300-mm wafer-

level 3D integration process is successfully demonstrated by combining high aspect ratio tungsten TSVs at tight pitches and a transfer-join adhesive/metal hybrid connection method to form a robust bonding interface. The TSV meets both the power and signaling requirements for computational systems.

Acknowledgements

The authors thank Dae-gyu Park and Ghavam Shahidi for management support. This work was partially supported by DARPA under contract # N66001-04-C-8032.

References

[1] P. Morrow, M. J. Kobrinsky, S. Ramanathan, C.-M. Partk, M. Harmes, V. Ramachandrarao, H.-M. Park, G. Kloster, S. List, and S. Kim, Proceedings of the UC Berkeley Extension Advanced Metallization Conference (AMC), 2004. [2] B. Swinnen, W. Ruythooren, P. De Moor, L. Bogaerts, L. Carbonell, K. De Munck, B. Eyckens, S. Stoukatch, D. Sabuncuoglu Tezcan, Z. Tőkei, J. Vaes, J. Van Aelst, E. Beyne, International Electron Devices Meeting (IEDM), 2006. [3] H. J. Tu, W. J. Wu, J. C. Hu, K. F. Yang, H. B. Chang, W. C. Chiou and C. H. Yu, International Interconnect Technology Conference( IITC), 2008. [4] C. K. Tsang, P. S. Andry, E. J. Sprogis, C. S. Patel, B. C. Webb, D. G. Manzer, J. U. Knickerbocker, Material Research Society, (MRS), Fall 2006. [5] R. Yu, VLSI/ULSI Multilevel Interconnection Conference, (VMIC), 2007.

TSV Parameters

System Requirement

This 3DI Technology

Power Delivery

Conductance per area

> 1.5*10-3 Ω-1μm-2

2.5*10-2

Ω-1μm-2

Signal Delivery

Capacitance per TSV < 100 fF 3 fF*

Delay per TSV < 10-14 s 2.4*10-15 s*

Inductance per TSV

< 200 pH for digital

< 26 pH for 60GHz RF

13 pH*

0 2 4 6 80.0

0.4

0.8

1.2

1.6

TSV + bond resistance = 0.1 Ω

TSV protrusionresistance= 0.08 Ω/μm

Resistance ofconnecting leads= 0.5 Ω

R

esis

tanc

e (O

hm)

TSV protrusion (μm)Fig. 11. Plot showing via chain node resistance breakdown. Three major components are: 1) Resistance from thin Cu connections at TSV protrusion, 2) Resistance from Cu connecting metallization, and 3) TSV and TJ bond resistance. Inset: Schematic drawing of TSV protrusion.

TSV protrusion

Table 1. A comparison between system requirements and TSV RLC values determined from this work. *Indicates values in table are simulated parameters based upon measured structural values.

0 1000 2000 3000

500

1000

1500

2000

R per node= 0.51 Ω

Res

ista

nce

(Ohm

)

Number of via chain nodesFig. 12. A 28.8-μm-pitch via chain resistance as a function of TSV node number. Resistance per node is extracted to be 0.51 Ω. Inset: I-V curve of a typical 28.8-μm-pitch via chain of 2724 nodes.

-1.0 -0.5 0.0 0.5 1.0-1.0

-0.5

0.0

0.5

1.0R=1.4 kΩ

Cur

rent

(mA

)

Voltage (V)