IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO. 10, OCTOBER 2018 1315

A 1.2-V 108.9-dB A-Weighted DR 101.4-dB SNDRAudio �� ADC Using a Multi-Rate

Noise-Shaping QuantizerJun Soo Cho , Member, IEEE, Cyuyeol Rhee, Susie Kim , Youngtae Yang , Jaehoon Jun,

Suhwan Kim , Senior Member, IEEE, and Hyunjoong Lee , Member, IEEE

Abstract—Along with the trend to reduce the power consump-tion of mobile devices, interface circuits such as analog-to-digitalconverters (ADCs) should also be designed to operate reliablyat low supply voltages without compromising production yield.We present a high-fidelity audio �� ADC suitable for low-voltage mobile applications, based on a new multi-bit quantizer.Its effective resolution is increased economically by augmentingan internal low-resolution quantizer with the proposed multi-ratenoise-shaping technique. Fabricated in a 0.13-μm CMOS technol-ogy, our ADC uses 3.5 mW at 1.2 V, and achieved an A-weightedDR of 108.9 dB and a peak signal-to-noise and distortion ratioof 101.4 dB.

Index Terms—CMOS, audio, mobile application, analog-to-digital conversion, multi-rate noise-shaping, quantizer.

I. INTRODUCTION

AS THE performance of mobile devices increases andmobile applications using them become more diverse

than before, the quality of contents to be covered is also rapidlyincreasing. To support such changes, input and output devicesfor mobile hardware are required to have higher performance.This direction also applies to mobile audio applications. Forexample, recent trends in the mobile microphone market aretargeting 70 dB A-weighted signal-to-noise ratio (SNR) at94dB sound pressure level (SPL) and higher acoustic over-load points. In the readout circuit of microphones, an ADChaving a dynamic range (DR) far above 100dB A-weightedcan meet this condition [1], [2]. In addition, a high value ofsignal-to-noise and distortion ratio (SNDR) is also preferred

Manuscript received March 30, 2018; revised June 14, 2018; acceptedJune 25, 2018. Date of publication July 5, 2018; date of current versionSeptember 27, 2018. This work was supported by the grant from GwanakAnalog Technologies, Seoul, South Korea. This brief was recommended byAssociate Editor P. Desgreys. (Corresponding author: Hyunjoong Lee.)

J. S. Cho was with the Department of Electrical and Computer Engineering,Seoul National University, Seoul 08826, South Korea. He is now with theInter-University Semiconductor Research Center, Seoul National University,Seoul 08826, South Korea.

C. Rhee, S. Kim, Y. Yang, J. Jun, and S. Kim are with the Department ofElectrical and Computer Engineering, Seoul National University, Seoul 08826,South Korea.

H. Lee was with the Department of Electrical and ComputerEngineering, Seoul National University, Seoul 08826, South Korea. He isnow with the Multidisciplinary Sensor Research Group, Electronics andTelecommunications Research Institute, Daejeon 34129, South Korea (e-mail:hyunjoong.lee@etri.re.kr).

Color versions of one or more of the figures in this brief are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSII.2018.2853189

so as to preserve the fidelity of acoustic signal source at highsound pressure levels above 94dB SPL.

To achieve such performance, �� modulators with multi-bitquantizer have been preferred because of their many advan-tages. When �� modulating small or DC-biased input signals,limit cycles due to low-resolution quantization introduce tonalnoise, to which the human ear is very sensitive [3]. Multi-bitquantizer with higher resolution reduces the quantizationnoise, and hence this tonal noise [4]. Multi-bit quantizationalso reduces the effect of non-ideality in circuits since a finerquantization step reduces the changes in voltages and cur-rents that occur at each time-step. In addition, opamps in ��

modulators having multi-bit quantization require less energyto respond to the smaller changes in signals.

However, to reduce the power consumption of digital cir-cuits including application processor (AP) in mobile devices,the supply voltage is getting lower, and thus interface circuitssuch as the ADC having high DR and SNR should also bedesigned to operate at a low supply voltage. Thus it becomesmore challenging to straightforwardly implement a multi-bitquantizer with higher resolution; the comparator offsets andclock noise make it difficult to improve the resolution of aflash-type quantizer within a lowered supply voltage.

These problems have motivated the introduction of multi-bit quantizers with higher resolution based on other structures,leading to some brilliant designs. A single-slope quantizercharges a capacitor with the incoming voltage signal [5],and the time required for a constant charging current toreach a target value is measured by a small number ofcomparators and counters. A quantizer with a successiveapproximation register (SAR) achieves a higher resolution byrepeatedly measuring the voltage sampled by capacitors con-nected to appropriate reference voltages [6]. A quantizer usinga voltage-controlled oscillator (VCO) transforms the voltagesignal into a change in frequency which can more easily bemeasured [7]. Surveying these different types of quantizer,we observe that improvements in resolution are achieved intime-domain operations: a smaller time-step, rather than asmaller voltage-step, can then be introduced to improve theresolution.

Quantizers with these features may be able to overcomethe limited range of signal amplitudes inherent in low-voltageoperation, but not all of them are appropriate for high-fidelityaudio ADCs operating at a lowered supply voltage. For exam-ple, the good performance of the bi-directional single-slopequantizer is likely to be compromised by process variations,

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1316 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO. 10, OCTOBER 2018

Fig. 1. Proposed quantizer and its operation: (a) behavioral diagram; (b) simplified diagram and its linear model; (c) resolution enhancement; (d) time-domainplot of the output. The unit delay following the input differentiator in Fig. 1(b) is an inherent characteristic of the operation of the quantizer that we propose.

because its accuracy largely depends on the accuracy ofcapacitor values and current sources. With the SAR quan-tizer, its clock frequency needs to be raised disproportion-ately to increase resolution, and higher frequencies limit theefficiency of the quantizer and related circuits. With theVCO-based quantizer, the oscillating signal has to be muchfaster than the sampling frequency. Other problems with thisdesign are the limited linearity of the tuning gain and thelarge changes in oscillation frequency resulting from processvariations.

In this brief, we introduce a structure suitable for a low-voltage high-fidelity audio �� ADC, in which a new type ofmulti-bit quantizer plays a key role. This design uses a multi-rate noise-shaping technique, in which the integrators andquantizer operate at different frequencies. The effective reso-lution of this quantizer, and thus that of the ADC, is increasedeconomically by augmenting an internal low-resolution quan-tizer with an oversampling and internal noise-shaping loop,which incorporates an analog differentiator and a digital inte-grator to improve its stability. Even with this technique, thestructural efficiency of the ADC is achieved by using anamalgamated adder.

In Section II, we present the structure of the quantizer. InSection III, the �� ADC using the proposed quantizer isdescribed. Measurement results are presented in Section IV.We conclude this brief in Section V.

II. MULTI-RATE NOISE-SHAPING QUANTIZER

To improve the resolution of the quantizer itself, oversam-pling and noise-shaping can also be used inside a quantizerwhich is a part of a �� ADC. We can implement it by intro-ducing a small number of comparators with a feedback looparound them, and then by increasing the operating speed of thisinternal loop a few fold by using the multi-rate technique [8].

The multi-rate noise-shaping quantizer proposed in this briefis shown in Fig. 1(a). Instead of using the classical feedbackstructure, first-order noise-shaping inside the quantizer can beimplemented using the error-feedback structure, which elimi-nates an integrator and uses an opamp as an adder. This choicefacilitates the structural optimization of our ADC.

If the design includes very few comparators, directly apply-ing the error-feedback technique would cause a problem; thequantizer would saturate quickly as the amplitude of the inputsignal increases, and the main �� loop in the ADC would beunstable even at low levels of input. To prevent this problem,we introduce a differentiator at the input of the quantizer andan integrator at its output [9], as shown in Fig. 1(a). Usingthe linear model in Fig. 1(b), we can see that differentiatingthe input and integrating the output of a quantizer allows sig-nals to pass through without modification besides one sampledelay. Because the input to the quantizer in a �� ADC isalready oversampled at a much higher rate than the samplingfrequency, the difference between the input and the output isapproximately the quantization error. This difference signal

CHO et al.: 1.2-V 108.9-dB A-WEIGHTED DR 101.4-dB SNDR AUDIO �� ADC USING MULTI-RATE NOISE-SHAPING QUANTIZER 1317

Fig. 2. Structurally optimized behavioral diagram of the proposed �� ADC incorporating the multi-rate noise-shaping quantizer.

is modulated by the internal �� modulator without causingsaturation, improving the stability of the whole �� ADC.

After noise-shaping, the signal has to be down-sampledto the operating frequency of the other components. A dig-ital finite impulse response (FIR) filter is used to remove theout-of-band noise. To simplify the structure of the filter andlimit its use of resources, we use a (N-1)-tap averaging filter,which imposes only a small delay on the signal. After filter-ing, the signal is down-sampled to the original oversamplingratio (OSR) of the main �� loop by simply discarding thesurplus N-1 samples. The down-sampled output is then sentto a simple non-delaying digital integrator.

Fig. 1(c) illustrates this resolution enhancement process.First, the differentiated input signal (shown as circles inFig. 1(c)) is N-times oversampled (in this example, the valueof N is 4) by repetition (the oversampled signal is shown assolid disks). Then the signal is modulated (the modulated sig-nal is shown as hollow squares). As the modulated signal isbeing processed through the 3-tap averaging filter, the outputof the filter (the solid squares) converges into its final values(shown as solid stars). The quantization errors before and afterthis process are both drawn as blue lines in Fig. 1(c), whichshows that the quantization noise is substantially reduced.

With two comparators, 4-fold oversampling and a 3-tapaveraging filter as a minimal implementation of the proposedconcept, the output of the new quantizer is a 9-level signal, asshown in Fig. 1(d). Note that the effective resolution of thisquantizer is not determined by this number of levels, becauseof the noise-shaping applied to its output. The effective res-olution of the quantizer has been evaluated by comparingthe values of the signal-to-quantization noise ratio (SQNR) inbehavioral simulation, and the proposed quantizer in a second-order �� ADC with an OSR of 64 shows a resolution similarto that of a conventional 255-level flash quantizer, the effectivenumber of bits (ENOB) of which is almost 8.

III. STRUCTURE OF THE �� ADC USING THE

MULTI-RATE NOISE-SHAPING QUANTIZER

A. Structural Optimization

Merging the structure of the proposed quantizer directly intoa second-order feedforward noise-shaping loop may lead toan inefficient structure. Thus we make a number of changesto improve its efficiency, leading to the structure of Fig. 2.Considering that our quantizer has an intrinsic one-sampledelay, as shown in Fig. 1(b), analog integrators are used witha delaying integrator following a non-delaying integrator. The

proposed quantizer is then placed after these integrators. At theboundary of the quantizer and the integrators, the signals fromthe feedforward paths should be summed and up-sampled.

Because 4-fold up-sampling is implemented as signal repe-tition, it can take place before the adder (marked blue in Fig. 2that replaces three adders. One of the adders is an adder usedas a differentiator in the proposed quantizer, another is anadder used in the error feedback structure, and the other is anadder used as a summing amplifier in feedforward structures.The output of this amalgamated adder is fed into the internal3-level quantizer. This adder also determines the differencebetween the delayed samples of the input and the output ofthe 3-level quantizer. The delayed samples are provided sepa-rately on the analog and digital paths to further facilitate theimplementation. The feedforward paths of the �� ADC arealso merged into the amalgamated adder.

The interface between the analog and the digital circuitry isprovided by the comparators in the 3-level quantizer. An adderand a sample repeater are implemented in the analog domain,while an averaging filter, a down-sampler, a delay and a clipperare all implemented in the digital domain. Because averagingis performed by a simple FIR filter with a coefficient of 1,no multiplier is required, which greatly simplifies the circuit.Down-sampling is performed by storing the filtered output onflip-flops at a reduced rate. The number of levels provided bythe internal DAC is the same as the number of levels output bythe internal quantizer, which is three in our implementation.

Component mismatches in DACs can introduce nonlinear-ity into the feedback signals, and this problem is relievedby dynamic element matching (DEM). We applied a data-weighted averaging (DWA) DEM scheme to the feedbackpath [10]. This path only requires an 8-level thermometer code,because the output of our circuit has a shaped-noise character-istic. This is helpful because the complexity of DEM circuitsgrows quickly with the number of levels [11].

B. Switched-Capacitor Circuit Implementation

Our design differs slightly from typical switched-capacitor�� ADC circuits because the integrator and quantizer oper-ate at two different frequencies. Thus, the correct alignmentof the timing of each integrator stage and the quantizer is akey consideration in this approach. Additionally, while adjust-ing relative timings among the stages, we can reduce themagnitude of the feedforward coefficient A1 as detailed below.

Using the feedforward structure, the input to the quantizery[n] is determined by the outputs of the integrators x1[n] and

1318 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO. 10, OCTOBER 2018

Fig. 3. Switched-capacitor implementation and timing diagram of the proposed �� ADC (only half of the differential circuit is shown for clarity). P1, P2are non-overlapping clocks for 64-times oversampling operations. P1M, P2M, etc. are non-overlapping clocks for up-sampled multi-rate operations. The nodeY denotes the sum of the signals coming from two feedforward paths with the coefficients A1 and A2.

x2[n], and their respective coefficients, A1 and A2, as follows:

y[n] = A1x1[n] + A2x2[n]. (1)

Here, if we use a next sample x2[n + 1] from the secondintegrator instead of a current sample x2[n] as that shown inFig. 3, we can set x2[n] = x2[n + 1] − C2x1[n], then

y[n] = A1x1[n] + A2(x2[n + 1] − C2x1[n])

= (A1 − A2C2)x1[n] + A2x2[n + 1]. (2)

In effect, we are replacing the coefficient of x1[n], which wasA1, by A1 − A2C2. Because both A2 and C2 are positive, andA1 > A2C2, this new coefficient is smaller, which reduces thesize of capacitor required to realize the coefficient of x1[n]in a switched-capacitor circuit to roughly 1/3 of its originalvalue.

Transition from low to high frequency is made using capac-itors as a timing buffer. Three capacitors are added to the paththat includes A1 to hold the output of the first integrator, andthen each of these four capacitors is successively used for thehigh-frequency operation. This avoids the first integrator hav-ing to run as fast as the quantizer. Since the coefficient of theA1 path has been reduced to around 1/3 of its previous value,these extra capacitors do not increase the loading on the firstintegrator so much. Our design of quantizer does increase thebandwidth required from the opamps in the second integratorand the adder, but this can be achieved economically becausethe capacitive loads on these two opamps are much lower thanthat on the opamp in the first integrator. The noise performanceof these switched-capacitor circuits is not critical, and so thecapacitors in them can be kept small.

The 3-level digital-to-analog conversion process constitutesthe feedback loop around the internal quantizer, and it is real-ized by two pairs of DACs that perform double-buffering tofeed the quantized values back to the analog adder. The out-put of the digital integrator is shuffled by the DWA and thenpassed through the DAC to the analog adder in front of thequantizer.

Fig. 4. Die photograph of the prototype audio �� ADC.

Although the proposed multi-bit implementation reduces thepossibility of slewing, we used two-stage class-AB opamps tominimize the effect of any residual slewing and thus to reducedistortion. We realized the switches in the switched-capacitorcircuits as a simple CMOS analog transmission gates.

IV. EXPERIMENTAL RESULTS

A prototype �� ADC incorporating a quantizer with thedesign described above was fabricated in a 0.13 μm CMOSmixed-signal process, and the die photograph of the ADC isshown in Fig. 4. To facilitate performance measurements, adecimator with a serial audio interface was configured on anFPGA, and this was linked to an AP2722 audio analyzer fromAudio Precision Inc. The measured SNDR and SNR versusinput signal level is shown in Fig. 5(a). The DR is 105.7 dB(108.9 dB A-weighted), and the design stably operates to thefull scale input. The peak SNR is 103.8 dB near the inputmagnitude of −1.4 dBFS, and the peak SNDR are 101.4 dBnear the input magnitude of −3.4 dBFS. The ADC’s outputspectrum at 1 kHz input with the magnitude of −3.4 dBFSis shown in Fig. 5(b), which proves that the proposed designstably operates and exhibits a good harmonic distortion (HD)characteristics at large input signal levels. The chip consumes3.5mW in total: 51% for the first opamp, 9% for the second

CHO et al.: 1.2-V 108.9-dB A-WEIGHTED DR 101.4-dB SNDR AUDIO �� ADC USING MULTI-RATE NOISE-SHAPING QUANTIZER 1319

Fig. 5. Measurements of our audio ADC: (a) SNDR and SNR vs. inputsignal level; (b) FFT of the ADC output.

TABLE ICOMPARATIVE PERFORMANCE OF OUR PROTOTYPE ADC

AND OTHER SWITCHED-CAPACITOR CIRCUIT-BASED

HIGH-FIDELITY AUDIO ADCS

opamp, 17% for the new quantizer including the amalgamatedadder, and 23% for the clock, DWA, bias, and reference.

The measurements are summarized in Table I, in com-parison with several CMOS switched-capacitor circuit-basedhigh-fidelity audio ADCs with DRs and SNRs both above or

around 100 dB [12]–[15]. Our design, stably operating with asupply voltage near 1V, achieves a Schreier’s figure-of-merit(FoMS) of 173.3 dB (176.5 dB A-weighted), which shows acompetitive performance among the compared ADCs.

V. CONCLUSION

Even at a lowered supply voltage to reduce the powerconsumption of mobile devices, the performance of interfacecircuits between the analog and digital domains cannot becompromised. We presented an audio �� ADC using theproposed multi-rate noise-shaping quantizer, which achievedsufficient resolution for high-fidelity audio in mobile appli-cations operating at a low supply voltage. The ADC isimplemented as a switched-capacitor circuit which maintainsgood matching accuracy, and thus we can expect that the pro-posed structure is relatively free from the issue of productionyield.

REFERENCES

[1] J. Lewis, “Microphone specifications explained,” InvensenseInc., San Jose, CA, USA, Application Note AN-1112, 2016.[Online]. Available: https://www.invensense.com/wp-content/uploads/2015/02/AN-1112-v1.1.pdf

[2] C. D. Berti, P. Malcovati, L. Crespi, and A. Baschirotto, “A 106 dBa-weighted DR low-power continuous-time �� modulator forMEMS microphones,” IEEE J. Solid-State Circuits, vol. 51, no. 7,pp. 1607–1618, Jul. 2016.

[3] L. D. Fielder, “Human auditory capabilities and their consequences ondigital-audio converter design,” in Proc. 7th AES Int. Conf., May 1989,pp. 45–62.

[4] J. de la Rosa, “Sigma-delta modulators: Tutorial overview, design guide,and state-of-the-art survey,” IEEE Trans. Circuits Syst. I, Reg. Papers,vol. 58, no. 1, pp. 1–21, Jan. 2011.

[5] N. Maghari and U.-K. Moon, “A third-order DT �� modulator usingnoise-shaped bi-directional single-slope quantizer,” IEEE J. Solid-StateCircuits, vol. 46, no. 12, pp. 2882–2891, Dec. 2011.

[6] L. Samid and Y. Manoli, “A multibit continuous time sigma delta mod-ulator with successive-approximation quantizer,” in Proc. IEEE Inter.Symp. Circuits Sys. (ISCAS), May 2006, pp. 2965–2968.

[7] M. Z. Straayer and M. H. Perrott, “A 12-bit, 10-MHz bandwidth,continuous-time �� ADC with a 5-bit, 950-MS/s VCO-based quan-tizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805–814,Apr. 2008.

[8] F. Colodro and A. Torralba, “Multirate �� modulators,” IEEE Trans.Circuits Syst. II, Exp. Briefs, vol. 49, no. 3, pp. 170–176, Mar. 2002.

[9] E. Bonizzoni, A. P. Perez, F. Maloberti, and M. A. Garcia-Andrade,“Two op-amps third-order sigma–delta modulator with 61-dB SNDR, 6-MHz bandwidth and 6-mW power consumption,” Analog Integr. CircuitsSignal Process., vol. 66, no. 3, pp. 381–388, Mar. 2011.

[10] R. T. Baird and T. S. Fiez, “Linearity enhancement of multibit ��

A/D and D/A converters using data weighted averaging,” IEEE Trans.Circuits Syst. II, Exp. Briefs, vol. 42, no. 12, pp. 753–762, Dec. 1995.

[11] Y. Cheng, C. Petrie, B. Nordick, and D. Comer, “Multibit delta-sigmamodulator with two-step quantization and segmented DAC,” IEEE Trans.Circuits Syst. II, Exp. Briefs, vol. 53, no. 9, pp. 848–852, Sep. 2006.

[12] B. Gönen, F. Sebastiano, R. van Veldhoven, and K. A. A. Makinwa, “A1.65-mW 0.16-mm2 dynamic zoom-ADC with 107.5 dB DR in 20-kHzBW,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers,2016, pp. 282–283.

[13] H. Park, K. Y. Nam, D. K. Su, K. Vleugels, and B. A. Wooley, “A0.7-V 870-μW digital-audio CMOS sigma-delta modulator,” IEEE J.Solid-State Circuits, vol. 44, no. 4, pp. 1078–1088, Apr. 2009.

[14] J.-Y. Wu, Z. Zhang, R. Subramoniam, and F. Maloberti, “A 107.4 dBSNR multi-bit sigma delta ADC with 1-PPM THD at -0.12 dBfrom full scale input,” IEEE J. Solid-State Circuits, vol. 44, no. 11,pp. 3060–3066, Nov. 2009.

[15] S.-H. Liao and J.-T. Wu, “A 1 V 175 μW 94.6 dB SNDR 25 kHz band-width delta-sigma modulator using segmented integration techniques,”in Proc. IEEE Custom Integr. Circuits Conf. (CICC), San Diego, CA,USA, 2018, pp. 1–4.