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Transcript of 9/18/2015 1 VLSI Physical Design Automation Prof. David Pan [email protected] Office: ACES 5.434...
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04/21/23 1
VLSI Physical Design Automation
Prof. David Pan
Office: ACES 5.434
Placement (1)
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Problem formulation
• Input:– Blocks (standard cells and macros) B1, ... , Bn
– Shapes and Pin Positions for each block Bi
– Nets N1, ... , Nm
• Output:– Coordinates (xi , yi ) for block Bi.
– No overlaps between blocks– The total wire length is minimized– The area of the resulting block is minimized or given a fixed die
• Other consideration: timing, routability, clock, buffering and interaction with physical synthesis
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Different Wire Length
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404/21/23
Different Routability/Chip Area
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504/21/23
Placement can Make a Difference• MCNC Benchmark circuit e64 (contains 230 4-LUT).
Placed to a FPGA.
Random InitialPlacement
FinalPlacement
After DetailedRouting
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Importance of Placement
• Placement is a fundamental problem for physical design • Glue of the physical synthesis• Becomes very active again in recent years:
– Many new academic placers for WL min since 2000– Many other publications to handle timing, routability, etc.
• Reasons:– Serious interconnect issues (delay, routability, noise) in deep-
submicron design• Placement determines interconnect to the first order • Need placement information even in early design stages (e.g., logic
synthesis)
– Placement problem becomes significantly larger– Cong et al. [ASPDAC-03, ISPD-03, ICCAD-03] point out that
existing placers are far from optimal, not scalable, and not stable
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Design Types• ASICs
– Lots of fixed I/Os, few macros, millions of standard cells– Placement densities : 40-80% (IBM)– Flat and hierarchical designs
• SoCs– Many more macro blocks, cores– Datapaths + control logic– Can have very low placement densities : < 40%
• Micro-Processor (P) Random Logic Macros(RLM)– Hierarchical partitions are placement instances (5-30K)– High placement densities : 80%-98% (low whitespace)– Many fixed I/Os, relatively few standard cells
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Requirements for Placers (1)
• Must handle 4-10M cells, 1000s macros – 64 bits + near-linear asymptotic complexity– Scalable/compact design database (OpenAccess)
• Accept fixed ports/pads/pins + fixed cells• Place macros, esp. with var. aspect ratios
– Non-trivial heights and widths(e.g., height=2rows)
• Honor targets and limits for net length• Respect floorplan constraints• Handle a wide range of placement densities
(from <25% to 100% occupied), ICCAD `02
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904/21/23
Requirements for Placers (2)
• Add / delete filler cells and Nwell contacts• Ignore clock connections • ECO placement
– Fix overlaps after logic restructuring– Place a small number of unplaced blocks
• Datapath planning services – E.g., for cores
• Provide placement dialog servicesto enable cooperation across tools– E.g., between placement and synthesis
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1004/21/23
A B C
Optimal Relative Order:
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A B C
To spread ...
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1204/21/23
A B C
.. or not to spread
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1304/21/23
A B C
Place to the left
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A B C
… or to the right
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1504/21/23
A B C
Optimal Relative Order:
Without “free” space the problem is dominated by order
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Placement Footprints:
Standard Cell:
Data Path:
IP - Floorplanning
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Core
ControlIO
Reserved areas
Mixed Data Path & sea of gates:
Placement Footprints:
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Perimeter IO
Area IO
Placement Footprints:
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UnconstrainedPlacement
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Floor plannedPlacement
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VLSI Global Placement Examples
bad placement good placement
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Major Placement Techniques
• Simulated Annealing– Timberwolf package [JSSC-85, DAC-86]
– Dragon [ICCAD-00]
• Partitioning-Based Placement– Capo [DAC-00]
– Fengshui [DAC-2001]
• Analytical Placement– Gordian [TCAD-91]
– Kraftwerk [DAC-98]• FastPlace [ISPD-04]
• Hall’s Quadratic Placement
• Genetic Algorithm
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Outline
• Wire length driven placement• Main methods
– Simulated Annealing• Gate-Array: Timberwolf package
• Standard-Cell: Timberwolf package, Dragon
– Partition-based methods– Analytical methods– Timing, congestion and other considerations
• Global placement (rough location)• Detailed placement (legalization)
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A down-to-the-earth method
• Clustering growth– Select unplaced components and place them in slots– SELECT: choose the unplaced component that is most
strongly connected to all (or any single) of the placed component
– PLACE: place the selected component at a slot such that a certain “cost” of the partial placement is minimized
– Simple and fast: ideal for initial placement
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Simulated Annealing Based Placement
( I ) “ The Timberwolf Placement and Routing Package”, Sechen, Sangiovanni; IEEE Journal of Solid-State Circuits, vol SC-20, No. 2(1985) 510-522
“Timber wolf 3.2: A New Standard Cell Placement and Global Routing Package” Sechen, Sangiovanni, 23rd DAC, 1986, 432-439
Timber wolf
Stage 1 Modules are moved between different rows as well as within the same
row modules overlaps are allowed when the temperature is reduced below a certain value, stage 2 begins
Stage 2 Remove overlaps Annealing process continues, but only interchanges adjacent modules
within the same row
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Solution Space
All possible arrangements of modules into rows possibly with overlaps
overlaps
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Neighboring Solutions
M3: Change the orientation of a module
1 2
3 4
2 1
3 4
1 2
3 4
Axis of reflections
M1: Displace a module to a new location
M2: Interchange two modules
.
.
Three types of moves:
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Move Selection
Timber wolf first try to select a move betwee M1 and M2
Prob(M1)=4/5
Prob(M2)=1/5
If a move of type M1 is chosen ( for certain module) and it is rejected, then a move of type M3 (for the same module) will be chosen with probability 1/10
Restriction on:
How far a module can be displaced
What pairs of modules can be interchanged
M1: Displacement
M2: Interchange
M3: Reflection
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2904/21/23
Move Restriction
Range Limiter
At the beginning, R is very large, big enough to contain the whole chip
Window size shrinks slowly as the temperature decreases. In fact, height and width of R log(T)
Stage 2 begins when window size are so small that no inter-row modules interchanges are possible
Rectangular window R
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Cost Function
= C1+C2+C3
net i
hi
wi
)( :1 iiii
i hC w i, i are horizontal and vertical weights, respectively
i =1, i =1 1/2 •perimeter of bounding box
Critical nets: Increase both i and i
Preferred metal layer routing: if vertical wirings are “cheaper” than horizontal wirings, we can use smaller vertical weights, i.e. i< i
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Cost Function (Cont’d)
C2: Penalty function for module overlaps
O(i,j) = amount of overlaps in the X-dimension between modules i and j
— offset parameter to ensure C2 0 when T 0
ji
jiOC2
2 ),(
C3: Penalty function that controls the row lengths
Desired row length = d( r )
l( r ) = sum of the widths of the modules in row r
r
rdrlC )()(3
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Annealing Schedule
• Tk = r(k)•T k-1 k= 1, 2, 3, ….
r(k) increase from 0.8 to max value 0.94 and then decrease to 0.1
• At each temperature, a total number of K•n attempts is made
n= number of modules
K= user specified constant
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04/21/23 33
Dragon2000: Standard-Cell Placement Tool for Large
Industry Circuits
M. Wang, X. Yang, and M. Sarrafzadeh,
ICCAD-2000
pages 260-263
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Main Idea
• Simulated annealing based– 1.9x faster than iTools 1.4.0 (commerical version of TimberWolf)
– Comparable wirelength to iTools (i.e., very good)
– Performs better for larger circuits
– Still very slow compared with than other approaches
– Also shown to have good routability
• Top-down hierarchical approach– hMetis to recursively quadrisect into 4h bins at level h
– Swapping of bins at each level by SA to minimize WL
– Terminates when each bin contains < 7 cells
– Then swap single cells locally to further minimize WL
• Detailed placement is done by greedy algorithm
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Outline
• Wire length driven placement• Main methods
– Simulated Annealing• Gate-Array: Timberwolf package
• Standard-Cell: Timberwolf package, Grover, Dragon
– Partition-based methods– Analytical methods
• Timing and congestion consideration• Newer trends
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Partition based methods
• Partitioning methods– FM– Multilevel techniques, e.g., hMetis
• Two academic open source placement tools– Capo (UCLA/UCSD/Michigan): multilevel FM– Feng-shui (SUNY Binghamton): use hMetis
• Pros and cons– Fast– Not stable
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Partitioning-based Approach
• Try to group closely connected modules together.• Repetitively divide a circuit into sub-circuits such that the
cut value is minimized.• Also, the placement region is partitioned (by cutlines)
accordingly.• Each sub-circuit is assigned to one partition of the
placement region.
Note: Also called min-cut placement approach.
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An Example
Circuit
Placement
Cutline
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Variations
• There are many variations in the partitioning-based approach. They are different in:– The objective function used.– The partitioning algorithm used.– The selection of cutlines.
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Partitioning:
Objective:
Given a set of interconnected blocks, produce two sets thatare of equal size, and such that the number of nets connecting the two sets is minimized.
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FM Partitioning:
Initial Random Placement
After Cut 1
After Cut 2
list_of_sets = entire_chip;while(any_set_has_2_or_more_objects(list_of_sets)){
for_each_set_in(list_of_sets){
partition_it();}/* each time through this loop the number of *//* sets in the list doubles. */
}
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FM Partitioning:
-1
-2
-1
1
0
0
0
2
0
0
1
-1
-1
-2
- each object is assigned a gain- objects are put into a sorted gain list- the object with the highest gain from the larger of the two sides is selected and moved.- the moved object is "locked"- gains of "touched" objects are recomputed- gain lists are resorted
Object Gain: The amount of change in cut crossings that will occur if an object is moved from its current partition into the other partition
Moves are made based on object gain.
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-1
-2
-1
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FM Partitioning:
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-1
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-20
0
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-1
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-1
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-1
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-1
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0
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-2 0
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-1
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-1
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Quadrature Placement Procedure
• Very suitable for circuits with high routing density in the centre.
1
2
3a
3b
4a 4b
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5804/21/23
Bisection Placement Procedure
• Good for standard-cell placement.
1
4
2a
2b
5a 5b
3a
3b
3c
3d
6a 6b 6c 6d
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04/21/23 59
Terminal Propagation Algorithm by Dunlop and Kernighan
“A Procedure for Placement of Standard-Cell VLSI Circuits”,TCAD, 4(1):92-98, Jan. 1985.
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Problem of Partitioning Subcircuits
A B
A B
A
B
Cost of these 2 partitionings are not the same.
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Terminal Propagation• Need to consider nets connecting to external terminals or
other modules as well.• Do partitioning in a breath-first manner (i.e., finish all
higher-level partitioning first).
A BA
B
Dummy Terminal
A B
The Dummy Terminal will try to pull B to the top partition.
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Terminal Propagation
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Creating Circuit Rows
• Terminal propagation reduce overall area by ~30%• Creating rows
– Choose α and β preferably to balance row to balance row length (during re-arrangement )
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04/21/23 64
Can Recursive Bisection Alone Produce Routable Placement?
(Name of placer: Capo)
Andrew Caldwell, Andrew Kahng, and Igor Markov
DAC-2000
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Capo Overview
• Standard cell placement, Fixed-die context• Pure recursive bisectioning placer
– Several minor techniques to produce good bisections
• Produce good results mainly because:– Improvement in mincut bisection using multi-level idea in the
past few years– Pay attention to details in implementation
• Implementation with good interface (LEF/DEF and GSRC bookshelf) available on web
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Capo Approach
• Recursive bisection framework:– Multi-level FM for instances with >200 cells– Flat FM for instances with 35-200 cells– Branch-and-bound for instances with <35 cells
• Careful handling partitioning tolerance:– Uncorking: Prevent large cells from blocking smaller cells to
move– Repartitioning: Several FM calls with decreasing tolerance– Block splitting heuristics: Higher tolerance for vertical cut– Hierarchical tolerance computation: Instance with more
whitespace can have a bigger partitioning tolerance
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Partitioning:
Pros:- very fast- great quality- scales nearly linearly with problem size
Cons:- non-trivial to implement- very directed algorithm, but this limits the ability to deal with miscellaneous constraints- Not stable (if there is minor change)
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Summary for Partition Based Placement
• Improvement in mincut partitioning are conducive to better wirelength and congestion
• Routable placements can be produced in most cases without explicit congestion management– Explicit congestion control may still be useful in some cases
• Better weighted wirelength often implies better routed wirelength, but not always