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1

The Energy Efficient Photonics

Revolution

John BowersDirector, Institute for Energy Efficiency

Collaborators

UCSB: Dan Blumenthal, Larry Coldren, Martijn Heck, Jock Bovington, Molly Piels, Yongbo Tang,Daoxin Dai, Sid Jain, Jon PetersIntel : Richard Jones, Mike Morse, Yimin Kang, Mario Paniccia, Brian KochAurrion: Eric Hall, Alex Fang, Greg FishHewlett Packard: Di Liang, Marco Fiorentino, Raymond G. Beausoleil

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Focused Solutions - Research

Lighting

A $1 LED light bulb 20x more efficient than an incandescent bulbElectronics and Photonics

Wireless and optical technologies for super-high-performance communicationsComputing A new Moores Law for more energy-efficient computing

Buildings and Design

Economically viable zero net-energy building systemsProduction and Storage

Solar cells with double efficiency at one-tenth the costEconomics and Policy

Worldwide energy efficiency policy direction, measurements and standards

2

Institute of Energy Efficiency

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Global Data TimelineSlide Courtesy Intel

2007 2008 2009 2010 2011

1ZB

500EB

1.5ZB

2ZB

Generated dataexceeds global

storagecapacity

A Zetabyte of

data isgenerated in

one year

Twice as muchdata generated

than can bestored

126 million blogs234 million websites

1.73 billion web users

90 trillion emails sent

A Flood of Data is being created at a60% growth rate may become more than we can handle!

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That Date Needs to be Accessed:IP Traffic Growth

Inte

rnettraffic(exabit/ps1MillionT

bps)

5

Internet video to pc

File sharing

Source: Cisco VNI June, 2009

Cisco forecast

Minnesota

Traffic Study

2 dB/year

Internet traffic

R. W. Tkach, Bell Labs Tech. J., 2009.

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Transmission Research records

1986 1990 1994 1998 2002 200610

100

1

10

100

Capac

ity

on

a

singlef

iber

Gb/s

Tb

/s

2010

Plot courtesy of P. Winzer and Chris Doerr

WDM started PDM started

Space Division Multiplexing(SDM) startingPhase diversity

started

1980: 50 Mbit/s

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How do we get to Terabit Optical Ethernet?

100G standards being commercialized 200G and 400G are

next then onto Terabit

Complex, highly integrated

circuits are needed

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8

100 Gb/s Transmit

100 Gb/s Receive

Value of Photonic Integration: Size,Weight and Power Reduction

100 Gb/sReceive

100 Gb/sTransmit

R. Nagarajan, Infinera ECOC 2007

InfineraSolution

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Photonic Integration for Coherent Optics(PICO)

Create a new generation of photonic integration engines that provideunprecedented and practical control of optical frequency and phase, driving alevel of sophistication that is routine today for RF into the optical domain.

Goal:

2009 2010 2011 2012 2013 2014

Capability

1Tb/s Integrated

Tx/Rx Capacity

100Gb/s All-Optical

Coherent Regeneration

256 QAM

Coherent PICs

Ultra-Narrow andTunable InP/Si Lasers

& Laser Arrays

Epitaxial InP on Si

PICs

THz-Bandwidth ChirpedLidar & mmW Sources

QPSK Coherent

PICs

100Gb/s IntegratedTx/Rx Capacity

1st Gen Optical

Phase-Locked Loops

1st Gen Hybrid InP/Si

Laser Technology

350 GHz fmax HBT

OPLL ASICs

2009 2010 2011 2012 2013 2014

Capability

1Tb/s Integrated

Tx/Rx Capacity

100Gb/s All-Optical

Coherent Regeneration

256 QAM

Coherent PICs

Ultra-Narrow andTunable InP/Si Lasers

& Laser Arrays

Epitaxial InP on Si

PICs

THz-Bandwidth ChirpedLidar & mmW Sources

QPSK Coherent

PICs

100Gb/s IntegratedTx/Rx Capacity

1st Gen Optical

Phase-Locked Loops

1st Gen Hybrid InP/Si

Laser Technology

350 GHz fmax HBT

OPLL ASICs

Coldren, Bowers, Rodwell, Johansson (UCSB),

Yariv (Caltech), Koch (Lehigh), Campbell (UVA), Ram (MIT)

LIDAREthernet Rx

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Terabit Optical Ethernet CenterBlumenthal, Bowers, Coldren, Rodwell

Mission Statement: To lead the way in a new roadmap for multi Tbps Optical Ethernet Create new energy efficient photonic integrated technologies

1020202015

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Monolithic Integration

UCSBMOTOR

Switch + diagnostic elements

Switch elements

PLSI

S. C. Nicholes, et al.

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Why Silicon Photonics?

Utilize advanced fabrication technologies for low cost, high volume integrated photonics.

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The Solution: Optical Interconnects

3D layer stacking will beprevalent in the 22nmtimeframe

Intra-chip optics can takeadvantage of thistechnology

Photonics layer (withsupporting electricalcircuits) more easilyintegrated with high

performance logic andmemory layers

Layers can be separatelyoptimized for performanceand yield

Opti

ca

lI/O

Logic Plane

O

ff-c

hip

opti

ca

l

sig

na

ls

On

-chip

optic

altr

affic

Photonic PlaneMemory Plane

Kash, Photonics in Supercomputing:

the Road to Exascale, IPNRA, 2009

BUT: Silicon has an indirect gap and doesnt emit light!So, how to integrate sources?

BUT: Silicon has an indirect gap and is a poor absorber (not1.55 m)! So, what about photodetectors?

BUT: Silicon is centrosymmetric (not electro-optic)!So, how to integrate modulators?

BUT: SiO2 is thermally resistive. So, power dissipation ofactive devices is a problem, particularly for rings and DWDM

BUT: Silicon is reciprocal. How to make an isolator?

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Hybrid Silicon Photonics

Silicon rib waveguide onSOI wafer

III-V active region

Optical gain from III-V Material Efficient coupling to silicon passive photonic devices No bonding alignment necessary: suitable for high volume CMOS All back end processing low temperature (

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Silicon Evanescent DFB Lasers

16

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Arrays of 16 DFBs with ElectroabsorptionModulators and Photodetectors

17

Laser Abandgap

Laser Bbandgap

16 DFB/PDlaser array

8 IntegratedPD-DFB-EAM

EAMbandgap

EAMbandgap

ISLC 2010, Kyoto , JapanWA3 9.15 - 9.30 Integrated Broadband Hybrid Silicon DFB Laser Array using Quantum Well Intermixing

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Hybrid Silicon Microring Laser: Path to lowthreshold and low power

III-V

Si

D. Liang, et al. Optics Express , 17 ( 22 ), 20355-20364 , October 23 , 2009

0.4 pJ/bit10 mA, 1 V =10 mW25 Gbit/s

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TW-EAM Structure

Small Footprint: 240 x 430mLarge bandwidth: 42 GHz

430m

240

m

-6

-5

-4

-3

-2

-1

0

1

0 10 20 30 40 50

E/Ore

sponse[dB]

Frequency [GHz]

42GHz

Bitrate:50 Gb/sER: 9.8 dBVpp: 2 V 20ps

Tang et al. OFC 2011

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20

Rattner, IPR Plenary,

Postdeadline (2010)

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21Rattner, IPR 2010

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22

Next Generation Optical USB

Every computer, SAN, Display,Rattner, IPR 2010

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Maximum configuration for CRS-1 92 Tbps (80 racks)

~1 Megawatt!!!

Problem: Bandwidth demands scaling faster than both silicon andcooling technologies

State-of-the Art Electronic IP Router

*Courtesy of Steve Nicholes

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D. J. Blumenthal,

Director, LASOR25

UCSB LASOR:a Label Switched Optical Router

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International Symposium on Ultra-high Capacity Optical Communication and Related OpticalSignal Processing and Devices Technical University of Denmark, Lyngby, Sept. 16 17, 2010

26

LASOR PIC Technologies

An 8x8 InP Monolithic Tunable Optical Router (MOTOR) Packet ForwardingChip, S. C. Nicholes, et. al., IEEE JLT, Special Issue on OFC, (2009)

(Invited).

M. J. R. Heck et al., "Integrated Recirculating OpticalBuffers," in SPIE Photonics West 2010, Proc., CA, 2010.

Optical BuffersMOTOR

Packet Forwarding Chip

CAM All-Photonic Wavelength Converter

Tauke-Pedretti, A., et. al., "Separate Absorption and Modulation Mach-Zehnder Wavelength Converter," Lightwave Technology, Journal of , vol.26,

no.1, pp.91-98, Jan.1, 2008

Vikrant Lal, et. al., "Monolithic Wavelength Converters for High-SpeedPacket-Switched Optical Networks," Selected Topics in Quantum Electronics,

IEEE Journal of , vol.13, no.1, pp.49-57, Jan.-feb. 2007

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Si3N4 waveguides on Si platform

iPhoD at UCSB (Blumenthal, Bowers)

iPhod = Fiber Like Losses on Chip -> 10x, 100x, 1000x reduction over todays losses

20 meter spiral delay line

3 cm

Q of >10 million. 30 MHz linewidth

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Data Centers:

Higher Capacity switchingSmaller size, weight and power

28

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Network Interface Rate

*Courtesy of R. W. Tkach,OIDA Annual Forum 2009

100 Gbit/s Interfacesare available.

100 Gbit/s switchingdoes not exist yet.

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Eliminating the OEO conversion and eliminating theelectronic switch reduces power and scales to highercapacity.

Power dominated by optical amplifiers (to make up forloss) and FPGA controller

Power Savings

1.E04

1.E03

1.E02

1.E01

1.E+00

1.E+01

1.E+02

1.E+03

FastOptical

Switch

Fast

Electrical

Switch

Ethernet

Switch

CoreRouter P ONONU IPTVServer

Energy

perbit(nJ)

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Port speeds increasing rapidly 1Tb/s coming in near term Fabric radix increasing

Fibers connecting more nodes

Trends in Switching and HPC

At 1Tb/s line speed and 100s of nodes, 100Tb/ssystem needed

Fibers connecting boards.Moving to fibers connecting chips...Switching is critical...

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0 5 10 15 20

-18

-12

-6

0

6

12

18

3 m @ 20oC

4.4

3.01.75

1.0

0.7

Frequency

response

(dB)

Frequency (GHz)

0.35 35 Gb/s

semi-insulating GaAs substrateAR coating

injector

pad

oxide

aperture

BCBgate contact

channel contact

active

region

gate pad

channel

pad

SiN sidewall

i-DBR

p-DBR

n-DBR

semi-insulating GaAs substrateAR coating

injector

pad

oxide

aperture

BCBgate contact

channel contact

active

region

gate pad

channel

pad

SiN sidewall

i-DBR

p-DBR

n-DBR

Novel Vertical-Cavity Surface-Emitting Lasers (VCSELs)

Coldren

State-of-the-Art diode VCSEL 25 and 35 Gbit/s Field-Induced Charge-

Separation Laser50 and 100 Gbit/s?

0 1 2 3 40

1

2

3

4

5

0 1 2 3 40

0. 2

0. 4

0. 6

0. 8

1

0V

-1 V

-2 V

-3 V

-4 V

Bias current, Ibias (mA)

Diodevoltage,Vpn

(V)

Lightou

tput(mW)

Vgate

DC and RFmeasurement

Channel

Injector

GateIbias

VpnVgate

FICSL

0 5 10 1 5-20

-15

-10

-5

0

5

10

15

20

Frequency(GHz)

Response(

dB)

Ibias = 4 mA

f 3dB ~ 11 G Hz

V gate = 0V

5 m @ 20C

~ 11GHz

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s.j.wallach.super2000.11.200033

PetaFlop System

I/O

ALL-OPTICALSWITCH

Multi-DieMulti-Processor

1

2 3

64

63

49

48

4 5

16

17

18

32

3347

46

128 die/box4 CPU/die

10 meters= 50 NS Delay

...

...

...

...

LAN/WAN

High Performance Computing Scaling

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Power Consumption

Co

mputationalThrough

put

1 kW10 kW100 kW1 MW10 MW

Peta-FLOPS in

a rack

HPC performance spaceexpanded by Chip-to-Chip

Optical Interconnects

electrical inter-chipinterconnect barrier

overcome by OI

OI at ~100 fJ/bit*

*D. A. B. Miller, IEEE Proc., 2009

High Performance Computing Scalingenabled by Optical Interconnects

100GFLOPS

1TFLOPS

10TFLOPS

100TFLOPS

1 Peta-FLOPS

10 Peta-FLOPS

OI at ~1 pJ/bit

100 x lower power!

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Summary

Photonics provides lower power, more efficient waysto communicateon a wide area, local area, andwithin data centers and supercomputers.

Integration is essential for size, weight, power andcost reduction and improved yield and reliability

Hybrid silicon photonics can integrate thistechnology with CMOS.

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